arch/arm/cpu/armv8/fsl-lsch3/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ifc.h>
   9 #include <nand.h>
  10 #include <spl.h>
  11 #include <asm/arch-fsl-lsch3/soc.h>
  12 #include <asm/io.h>
  13 #include <asm/global_data.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static void erratum_a008751(void)
  18 {
  19 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
  20         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  21
  22         writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
  23 #endif
  24 }
  25
  26 static void erratum_rcw_src(void)
  27 {
  28 #if defined(CONFIG_SPL)
  29         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  30         u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  31         u32 val;
  32
  33         val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  34         val &= ~DCFG_PORSR1_RCW_SRC;
  35         val |= DCFG_PORSR1_RCW_SRC_NOR;
  36         out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  37 #endif
  38 }
  39
  40 void fsl_lsch3_early_init_f(void)
  41 {
  42         erratum_a008751();
  43         erratum_rcw_src();
  44         init_early_memctl_regs();       /* tighten IFC timing */
  45 }
  46
  47 #ifdef CONFIG_SPL_BUILD
  48 void board_init_f(ulong dummy)
  49 {
  50         /* Clear global data */
  51         memset((void *)gd, 0, sizeof(gd_t));
  52
  53         arch_cpu_init();
  54         board_early_init_f();
  55         timer_init();
  56         env_init();
  57         gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
  58
  59         serial_init();
  60         console_init_f();
  61         dram_init();
  62
  63         /* Clear the BSS. */
  64         memset(__bss_start, 0, __bss_end - __bss_start);
  65
  66         board_init_r(NULL, 0);
  67 }
  68
  69 u32 spl_boot_device(void)
  70 {
  71         return BOOT_DEVICE_NAND;
  72 }
  73 #endif