arch/arm/cpu/armv8/zynqmp/spl.c

   1 /*
   2  * Copyright 2015 - 2016 Xilinx, Inc.
   3  *
   4  * Michal Simek <michal.simek@xilinx.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <debug_uart.h>
  11 #include <spl.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/spl.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17
  18 void board_init_f(ulong dummy)
  19 {
  20         psu_init();
  21         board_early_init_r();
  22
  23 #ifdef CONFIG_DEBUG_UART
  24         /* Uart debug for sure */
  25         debug_uart_init();
  26         puts("Debug uart enabled\n"); /* or printch() */
  27 #endif
  28         /* Delay is required for clocks to be propagated */
  29         udelay(1000000);
  30
  31         /* Clear the BSS */
  32         memset(__bss_start, 0, __bss_end - __bss_start);
  33
  34         /* No need to call timer init - it is empty for ZynqMP */
  35         board_init_r(NULL, 0);
  36 }
  37
  38 static void ps_mode_reset(ulong mode)
  39 {
  40         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  41                mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  42                &crlapb_base->boot_pin_ctrl);
  43         udelay(1);
  44         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  45                &crlapb_base->boot_pin_ctrl);
  46         udelay(5);
  47         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  48                mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  49                &crlapb_base->boot_pin_ctrl);
  50 }
  51
  52 /*
  53  * Set default PS_MODE1 which is used for USB ULPI phy reset
  54  * Also other resets can be connected to this certain pin
  55  */
  56 #ifndef MODE_RESET
  57 # define MODE_RESET     PS_MODE1
  58 #endif
  59
  60 #ifdef CONFIG_SPL_BOARD_INIT
  61 void spl_board_init(void)
  62 {
  63         preloader_console_init();
  64         ps_mode_reset(MODE_RESET);
  65         board_init();
  66 }
  67 #endif
  68
  69 u32 spl_boot_device(void)
  70 {
  71         u32 reg = 0;
  72         u8 bootmode;
  73
  74 #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
  75         /* Change default boot mode at run-time */
  76         writel(BOOT_MODE_USE_ALT |
  77                CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
  78                &crlapb_base->boot_mode);
  79 #endif
  80
  81         reg = readl(&crlapb_base->boot_mode);
  82         bootmode = reg & BOOT_MODES_MASK;
  83
  84         switch (bootmode) {
  85         case JTAG_MODE:
  86                 return BOOT_DEVICE_RAM;
  87 #ifdef CONFIG_SPL_MMC_SUPPORT
  88         case EMMC_MODE:
  89         case SD_MODE:
  90         case SD_MODE1:
  91                 return BOOT_DEVICE_MMC1;
  92 #endif
  93 #ifdef CONFIG_SPL_DFU_SUPPORT
  94         case USB_MODE:
  95                 return BOOT_DEVICE_DFU;
  96 #endif
  97         default:
  98                 printf("Invalid Boot Mode:0x%x\n", bootmode);
  99                 break;
 100         }
 101
 102         return 0;
 103 }
 104
 105 u32 spl_boot_mode(const u32 boot_device)
 106 {
 107         switch (spl_boot_device()) {
 108         case BOOT_DEVICE_RAM:
 109                 return 0;
 110         case BOOT_DEVICE_MMC1:
 111                 return MMCSD_MODE_FS;
 112         default:
 113                 puts("spl: error: unsupported device\n");
 114                 hang();
 115         }
 116 }
 117
 118 __weak void psu_init(void)
 119 {
 120          /*
 121           * This function is overridden by the one in
 122           * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
 123           */
 124 }
 125
 126 #ifdef CONFIG_SPL_OS_BOOT
 127 int spl_start_uboot(void)
 128 {
 129         return 0;
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_SPL_LOAD_FIT
 134 int board_fit_config_name_match(const char *name)
 135 {
 136         /* Just empty function now - can't decide what to choose */
 137         debug("%s: %s\n", __func__, name);
 138
 139         return 0;
 140 }
 141 #endif