arch/arm/cpu/lh7a40x/start.S

   1 /*
   2  *  armboot - Startup Code for ARM920 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <config.h>
  29 #include <version.h>
  30
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 .globl _TEXT_BASE
  76 _TEXT_BASE:
  77         .word   TEXT_BASE
  78
  79 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  80 .globl _armboot_start
  81 _armboot_start:
  82         .word _start
  83 #endif
  84
  85 /*
  86  * These are defined in the board-specific linker script.
  87  */
  88 .globl _bss_start
  89 _bss_start:
  90         .word __bss_start
  91
  92 .globl _bss_end
  93 _bss_end:
  94         .word _end
  95
  96 #ifdef CONFIG_USE_IRQ
  97 /* IRQ stack memory (calculated at run-time) */
  98 .globl IRQ_STACK_START
  99 IRQ_STACK_START:
 100         .word   0x0badc0de
 101
 102 /* IRQ stack memory (calculated at run-time) */
 103 .globl FIQ_STACK_START
 104 FIQ_STACK_START:
 105         .word 0x0badc0de
 106 #endif
 107
 108 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 109 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 110 .globl IRQ_STACK_START_IN
 111 IRQ_STACK_START_IN:
 112         .word   0x0badc0de
 113
 114 .globl _datarel_start
 115 _datarel_start:
 116         .word __datarel_start
 117
 118 .globl _datarelrolocal_start
 119 _datarelrolocal_start:
 120         .word __datarelrolocal_start
 121
 122 .globl _datarellocal_start
 123 _datarellocal_start:
 124         .word __datarellocal_start
 125
 126 .globl _datarelro_start
 127 _datarelro_start:
 128         .word __datarelro_start
 129
 130 .globl _got_start
 131 _got_start:
 132         .word __got_start
 133
 134 .globl _got_end
 135 _got_end:
 136         .word __got_end
 137
 138 /*
 139  * the actual reset code
 140  */
 141
 142 reset:
 143         /*
 144          * set the cpu to SVC32 mode
 145          */
 146         mrs     r0,cpsr
 147         bic     r0,r0,#0x1f
 148         orr     r0,r0,#0xd3
 149         msr     cpsr,r0
 150
 151 #define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 152 #define pINTENC         0x8000050C  /* Interupt-Controller enable clear register */
 153 #define pCLKSET         0x80000420  /* clock divisor register */
 154
 155         /* disable watchdog, set watchdog control register to
 156          * all zeros (default reset)
 157          */
 158         ldr     r0, =pWDTCTL
 159         mov     r1, #0x0
 160         str     r1, [r0]
 161
 162         /*
 163          * mask all IRQs by setting all bits in the INTENC register (default)
 164          */
 165         mov     r1, #0xffffffff
 166         ldr     r0, =pINTENC
 167         str     r1, [r0]
 168
 169         /* FCLK:HCLK:PCLK = 1:2:2 */
 170         /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 171         ldr     r0, =pCLKSET
 172         ldr r1, =0x0004ee39
 173 @       ldr r1, =0x0005ee39     @ 1: 2: 4
 174         str     r1, [r0]
 175
 176         /*
 177          * we do sys-critical inits only at reboot,
 178          * not when booting from ram!
 179          */
 180 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 181         bl      cpu_init_crit
 182 #endif
 183
 184 /* Set stackpointer in internal RAM to call board_init_f */
 185 call_board_init_f:
 186         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 187         ldr     r0,=0x00000000
 188         bl      board_init_f
 189
 190 /*------------------------------------------------------------------------------*/
 191
 192 /*
 193  * void relocate_code (addr_sp, gd, addr_moni)
 194  *
 195  * This "function" does not return, instead it continues in RAM
 196  * after relocating the monitor code.
 197  *
 198  */
 199         .globl  relocate_code
 200 relocate_code:
 201         mov     r4, r0  /* save addr_sp */
 202         mov     r5, r1  /* save addr of gd */
 203         mov     r6, r2  /* save addr of destination */
 204         mov     r7, r2  /* save addr of destination */
 205
 206         /* Set up the stack                                                 */
 207 stack_setup:
 208         mov     sp, r4
 209
 210         adr     r0, _start
 211         ldr     r2, _TEXT_BASE
 212         ldr     r3, _bss_start
 213         sub     r2, r3, r2              /* r2 <- size of armboot            */
 214         add     r2, r0, r2              /* r2 <- source end address         */
 215         cmp     r0, r6
 216         beq     clear_bss
 217
 218 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 219 copy_loop:
 220         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 221         stmia   r6!, {r9-r10}           /* copy to   target address [r1]    */
 222         cmp     r0, r2                  /* until source end address [r2]    */
 223         blo     copy_loop
 224
 225 #ifndef CONFIG_PRELOADER
 226         /* fix got entries */
 227         ldr     r1, _TEXT_BASE          /* Text base */
 228         mov     r0, r7                  /* reloc addr */
 229         ldr     r2, _got_start          /* addr in Flash */
 230         ldr     r3, _got_end            /* addr in Flash */
 231         sub     r3, r3, r1
 232         add     r3, r3, r0
 233         sub     r2, r2, r1
 234         add     r2, r2, r0
 235
 236 fixloop:
 237         ldr     r4, [r2]
 238         sub     r4, r4, r1
 239         add     r4, r4, r0
 240         str     r4, [r2]
 241         add     r2, r2, #4
 242         cmp     r2, r3
 243         bne     fixloop
 244 #endif
 245 #endif  /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 246
 247 clear_bss:
 248 #ifndef CONFIG_PRELOADER
 249         ldr     r0, _bss_start
 250         ldr     r1, _bss_end
 251         ldr     r3, _TEXT_BASE          /* Text base */
 252         mov     r4, r7                  /* reloc addr */
 253         sub     r0, r0, r3
 254         add     r0, r0, r4
 255         sub     r1, r1, r3
 256         add     r1, r1, r4
 257         mov     r2, #0x00000000         /* clear                            */
 258
 259 clbss_l:str     r2, [r0]                /* clear loop...                    */
 260         add     r0, r0, #4
 261         cmp     r0, r1
 262         bne     clbss_l
 263 #endif
 264
 265 /*
 266  * We are done. Do not return, instead branch to second part of board
 267  * initialization, now running from RAM.
 268  */
 269         ldr     r0, _TEXT_BASE
 270         ldr     r2, _board_init_r
 271         sub     r2, r2, r0
 272         add     r2, r2, r7      /* position from board_init_r in RAM */
 273         /* setup parameters for board_init_r */
 274         mov     r0, r5          /* gd_t */
 275         mov     r1, r7          /* dest_addr */
 276         /* jump to it ... */
 277         mov     lr, r2
 278         mov     pc, lr
 279
 280 _board_init_r: .word board_init_r
 281
 282 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 283 /*
 284  * the actual reset code
 285  */
 286
 287 reset:
 288         /*
 289          * set the cpu to SVC32 mode
 290          */
 291         mrs     r0,cpsr
 292         bic     r0,r0,#0x1f
 293         orr     r0,r0,#0xd3
 294         msr     cpsr,r0
 295
 296 #define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 297 #define pINTENC         0x8000050C  /* Interupt-Controller enable clear register */
 298 #define pCLKSET         0x80000420  /* clock divisor register */
 299
 300         /* disable watchdog, set watchdog control register to
 301          * all zeros (default reset)
 302          */
 303         ldr     r0, =pWDTCTL
 304         mov     r1, #0x0
 305         str     r1, [r0]
 306
 307         /*
 308          * mask all IRQs by setting all bits in the INTENC register (default)
 309          */
 310         mov     r1, #0xffffffff
 311         ldr     r0, =pINTENC
 312         str     r1, [r0]
 313
 314         /* FCLK:HCLK:PCLK = 1:2:2 */
 315         /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 316         ldr     r0, =pCLKSET
 317         ldr r1, =0x0004ee39
 318 @       ldr r1, =0x0005ee39     @ 1: 2: 4
 319         str     r1, [r0]
 320
 321         /*
 322          * we do sys-critical inits only at reboot,
 323          * not when booting from ram!
 324          */
 325 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 326         bl      cpu_init_crit
 327 #endif
 328
 329 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 330 relocate:                               /* relocate U-Boot to RAM           */
 331         adr     r0, _start              /* r0 <- current position of code   */
 332         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 333         cmp     r0, r1                  /* don't reloc during debug         */
 334         beq     stack_setup
 335
 336         ldr     r2, _armboot_start
 337         ldr     r3, _bss_start
 338         sub     r2, r3, r2              /* r2 <- size of armboot            */
 339         add     r2, r0, r2              /* r2 <- source end address         */
 340
 341 copy_loop:
 342         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 343         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 344         cmp     r0, r2                  /* until source end address [r2]    */
 345         blo     copy_loop
 346 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 347
 348         /* Set up the stack                                                 */
 349 stack_setup:
 350         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 351         sub     r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area                      */
 352         sub     r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
 353 #ifdef CONFIG_USE_IRQ
 354         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 355 #endif
 356         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 357         bic     sp, sp, #7              /* 8-byte alignment for ABI compliance */
 358
 359 clear_bss:
 360         ldr     r0, _bss_start          /* find start of bss segment        */
 361         @add    r0, r0, #4              /* start at first byte of bss       */
 362                                         /*   why inc. 4 bytes past then?    */
 363         ldr     r1, _bss_end            /* stop here                        */
 364         mov     r2, #0x00000000         /* clear                            */
 365
 366 clbss_l:str     r2, [r0]                /* clear loop...                    */
 367         add     r0, r0, #4
 368         cmp     r0, r1
 369         blo     clbss_l
 370
 371         ldr     pc, _start_armboot
 372
 373 _start_armboot: .word start_armboot
 374 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
 375
 376 /*
 377  *************************************************************************
 378  *
 379  * CPU_init_critical registers
 380  *
 381  * setup important registers
 382  * setup memory timing
 383  *
 384  *************************************************************************
 385  */
 386
 387
 388 cpu_init_crit:
 389         /*
 390          * flush v4 I/D caches
 391          */
 392         mov     r0, #0
 393         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 394         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 395
 396         /*
 397          * disable MMU stuff and caches
 398          */
 399         mrc     p15, 0, r0, c1, c0, 0
 400         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 401         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 402         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 403         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 404         orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
 405         mcr     p15, 0, r0, c1, c0, 0
 406
 407
 408         /*
 409          * before relocating, we have to setup RAM timing
 410          * because memory timing is board-dependend, you will
 411          * find a lowlevel_init.S in your board directory.
 412          */
 413         mov     ip, lr
 414         bl      lowlevel_init
 415         mov     lr, ip
 416
 417         mov     pc, lr
 418
 419
 420 /*
 421  *************************************************************************
 422  *
 423  * Interrupt handling
 424  *
 425  *************************************************************************
 426  */
 427
 428 @
 429 @ IRQ stack frame.
 430 @
 431 #define S_FRAME_SIZE    72
 432
 433 #define S_OLD_R0        68
 434 #define S_PSR           64
 435 #define S_PC            60
 436 #define S_LR            56
 437 #define S_SP            52
 438
 439 #define S_IP            48
 440 #define S_FP            44
 441 #define S_R10           40
 442 #define S_R9            36
 443 #define S_R8            32
 444 #define S_R7            28
 445 #define S_R6            24
 446 #define S_R5            20
 447 #define S_R4            16
 448 #define S_R3            12
 449 #define S_R2            8
 450 #define S_R1            4
 451 #define S_R0            0
 452
 453 #define MODE_SVC 0x13
 454 #define I_BIT    0x80
 455
 456 /*
 457  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 458  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 459  */
 460
 461         .macro  bad_save_user_regs
 462         sub     sp, sp, #S_FRAME_SIZE
 463         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 464 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 465         ldr     r2, _armboot_start
 466         sub     r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 467         sub     r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 468 #else
 469         ldr     r2, IRQ_STACK_START_IN
 470 #endif
 471         ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 472         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 473
 474         add     r5, sp, #S_SP
 475         mov     r1, lr
 476         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 477         mov     r0, sp
 478         .endm
 479
 480         .macro  irq_save_user_regs
 481         sub     sp, sp, #S_FRAME_SIZE
 482         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 483         add     r8, sp, #S_PC
 484         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 485         str     lr, [r8, #0]                    @ Save calling PC
 486         mrs     r6, spsr
 487         str     r6, [r8, #4]                    @ Save CPSR
 488         str     r0, [r8, #8]                    @ Save OLD_R0
 489         mov     r0, sp
 490         .endm
 491
 492         .macro  irq_restore_user_regs
 493         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 494         mov     r0, r0
 495         ldr     lr, [sp, #S_PC]                 @ Get PC
 496         add     sp, sp, #S_FRAME_SIZE
 497         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 498         .endm
 499
 500         .macro get_bad_stack
 501 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 502         ldr     r13, _armboot_start             @ setup our mode stack
 503         sub     r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 504         sub     r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 505 #else
 506         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 507 #endif
 508
 509         str     lr, [r13]                       @ save caller lr / spsr
 510         mrs     lr, spsr
 511         str     lr, [r13, #4]
 512
 513         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 514         @ msr   spsr_c, r13
 515         msr     spsr, r13
 516         mov     lr, pc
 517         movs    pc, lr
 518         .endm
 519
 520         .macro get_irq_stack                    @ setup IRQ stack
 521         ldr     sp, IRQ_STACK_START
 522         .endm
 523
 524         .macro get_fiq_stack                    @ setup FIQ stack
 525         ldr     sp, FIQ_STACK_START
 526         .endm
 527
 528 /*
 529  * exception handlers
 530  */
 531         .align  5
 532 undefined_instruction:
 533         get_bad_stack
 534         bad_save_user_regs
 535         bl      do_undefined_instruction
 536
 537         .align  5
 538 software_interrupt:
 539         get_bad_stack
 540         bad_save_user_regs
 541         bl      do_software_interrupt
 542
 543         .align  5
 544 prefetch_abort:
 545         get_bad_stack
 546         bad_save_user_regs
 547         bl      do_prefetch_abort
 548
 549         .align  5
 550 data_abort:
 551         get_bad_stack
 552         bad_save_user_regs
 553         bl      do_data_abort
 554
 555         .align  5
 556 not_used:
 557         get_bad_stack
 558         bad_save_user_regs
 559         bl      do_not_used
 560
 561 #ifdef CONFIG_USE_IRQ
 562
 563         .align  5
 564 irq:
 565         get_irq_stack
 566         irq_save_user_regs
 567         bl      do_irq
 568         irq_restore_user_regs
 569
 570         .align  5
 571 fiq:
 572         get_fiq_stack
 573         /* someone ought to write a more effiction fiq_save_user_regs */
 574         irq_save_user_regs
 575         bl      do_fiq
 576         irq_restore_user_regs
 577
 578 #else
 579
 580         .align  5
 581 irq:
 582         get_bad_stack
 583         bad_save_user_regs
 584         bl      do_irq
 585
 586         .align  5
 587 fiq:
 588         get_bad_stack
 589         bad_save_user_regs
 590         bl      do_fiq
 591
 592 #endif
 593
 594         .align  5
 595 .globl reset_cpu
 596 reset_cpu:
 597         bl      disable_interrupts
 598
 599         /* Disable watchdog */
 600         ldr     r1, =pWDTCTL
 601         mov     r3, #0
 602         str     r3, [r1]
 603
 604         /* reset counter */
 605         ldr     r3, =0x00001984
 606         str     r3, [r1, #4]
 607
 608         /* Enable the watchdog */
 609         mov     r3, #1
 610         str     r3, [r1]
 611
 612 _loop_forever:
 613         b       _loop_forever