arch/arm/cpu/s3c44b0/start.S

   1 /*
   2  * Startup Code for S3C44B0 CPU-core
   3  *
   4  * (C) Copyright 2004
   5  * DAVE Srl
   6  *
   7  * http://www.dave-tech.it
   8  * http://www.wawnet.biz
   9  * mailto:info@wawnet.biz
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm-offsets.h>
  31 #include <config.h>
  32 #include <version.h>
  33
  34 /*
  35  * Jump vector table
  36  */
  37
  38
  39 .globl _start
  40 _start: b       reset
  41         add     pc, pc, #0x0c000000
  42         add     pc, pc, #0x0c000000
  43         add     pc, pc, #0x0c000000
  44         add     pc, pc, #0x0c000000
  45         add     pc, pc, #0x0c000000
  46         add     pc, pc, #0x0c000000
  47         add     pc, pc, #0x0c000000
  48
  49         .balignl 16,0xdeadbeef
  50
  51
  52 /*
  53  *************************************************************************
  54  *
  55  * Startup Code (reset vector)
  56  *
  57  * do important init only if we don't start from memory!
  58  * relocate u-boot to ram
  59  * setup stack
  60  * jump to second stage
  61  *
  62  *************************************************************************
  63  */
  64
  65 .globl _TEXT_BASE
  66 _TEXT_BASE:
  67 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  68         .word   CONFIG_SPL_TEXT_BASE
  69 #else
  70         .word   CONFIG_SYS_TEXT_BASE
  71 #endif
  72
  73 /*
  74  * These are defined in the board-specific linker script.
  75  * Subtracting _start from them lets the linker put their
  76  * relative position in the executable instead of leaving
  77  * them null.
  78  */
  79 .globl _bss_start_ofs
  80 _bss_start_ofs:
  81         .word __bss_start - _start
  82
  83 .globl _bss_end_ofs
  84 _bss_end_ofs:
  85         .word __bss_end - _start
  86
  87 .globl _end_ofs
  88 _end_ofs:
  89         .word _end - _start
  90
  91 #ifdef CONFIG_USE_IRQ
  92 /* IRQ stack memory (calculated at run-time) */
  93 .globl IRQ_STACK_START
  94 IRQ_STACK_START:
  95         .word   0x0badc0de
  96
  97 /* IRQ stack memory (calculated at run-time) */
  98 .globl FIQ_STACK_START
  99 FIQ_STACK_START:
 100         .word 0x0badc0de
 101 #endif
 102
 103 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 104 .globl IRQ_STACK_START_IN
 105 IRQ_STACK_START_IN:
 106         .word   0x0badc0de
 107
 108 /*
 109  * the actual reset code
 110  */
 111
 112 reset:
 113         /*
 114          * set the cpu to SVC32 mode
 115          */
 116         mrs     r0,cpsr
 117         bic     r0,r0,#0x1f
 118         orr     r0,r0,#0xd3
 119         msr     cpsr,r0
 120
 121         /*
 122          * we do sys-critical inits only at reboot,
 123          * not when booting from ram!
 124          */
 125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 126         bl      cpu_init_crit
 127         /*
 128          * before relocating, we have to setup RAM timing
 129          * because memory timing is board-dependend, you will
 130          * find a lowlevel_init.S in your board directory.
 131          */
 132         bl      lowlevel_init
 133 #endif
 134
 135         bl      _main
 136
 137 /*------------------------------------------------------------------------------*/
 138
 139         .globl  c_runtime_cpu_setup
 140 c_runtime_cpu_setup:
 141
 142         bx      lr
 143
 144 /*
 145  *************************************************************************
 146  *
 147  * CPU_init_critical registers
 148  *
 149  * setup important registers
 150  * setup memory timing
 151  *
 152  *************************************************************************
 153  */
 154
 155 #define INTCON (0x01c00000+0x200000)
 156 #define INTMSK (0x01c00000+0x20000c)
 157 #define LOCKTIME (0x01c00000+0x18000c)
 158 #define PLLCON (0x01c00000+0x180000)
 159 #define CLKCON (0x01c00000+0x180004)
 160 #define WTCON (0x01c00000+0x130000)
 161 cpu_init_crit:
 162         /* disable watch dog */
 163         ldr     r0, =WTCON
 164         ldr     r1, =0x0
 165         str     r1, [r0]
 166
 167         /*
 168          * mask all IRQs by clearing all bits in the INTMRs
 169          */
 170         ldr     r1,=INTMSK
 171         ldr     r0, =0x03fffeff
 172         str     r0, [r1]
 173
 174         ldr     r1, =INTCON
 175         ldr     r0, =0x05
 176         str     r0, [r1]
 177
 178         /* Set Clock Control Register */
 179         ldr     r1, =LOCKTIME
 180         ldrb    r0, =800
 181         strb    r0, [r1]
 182
 183         ldr     r1, =PLLCON
 184
 185 #if CONFIG_S3C44B0_CLOCK_SPEED==66
 186         ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
 187 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
 188         ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 189 #else
 190 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
 191 #endif
 192
 193         str     r0, [r1]
 194
 195         ldr     r1,=CLKCON
 196         ldr     r0, =0x7ff8
 197         str     r0, [r1]
 198
 199         mov     pc, lr
 200
 201
 202 /*************************************************/
 203 /*      interrupt vectors       */
 204 /*************************************************/
 205 real_vectors:
 206         b       reset
 207         b       undefined_instruction
 208         b       software_interrupt
 209         b       prefetch_abort
 210         b       data_abort
 211         b       not_used
 212         b       irq
 213         b       fiq
 214
 215 /*************************************************/
 216
 217 undefined_instruction:
 218         mov     r6, #3
 219         b       reset
 220
 221 software_interrupt:
 222         mov     r6, #4
 223         b       reset
 224
 225 prefetch_abort:
 226         mov     r6, #5
 227         b       reset
 228
 229 data_abort:
 230         mov     r6, #6
 231         b       reset
 232
 233 not_used:
 234         /* we *should* never reach this */
 235         mov     r6, #7
 236         b       reset
 237
 238 irq:
 239         mov     r6, #8
 240         b       reset
 241
 242 fiq:
 243         mov     r6, #9
 244         b       reset