arch/arm/cpu/sa1100/start.S

   1 /*
   2  *  armboot - Startup Code for SA1100 CPU
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <asm-offsets.h>
  29 #include <config.h>
  30 #include <version.h>
  31
  32 /*
  33  *************************************************************************
  34  *
  35  * Jump vector table as in table 3.1 in [1]
  36  *
  37  *************************************************************************
  38  */
  39
  40
  41 .globl _start
  42 _start: b       reset
  43         ldr     pc, _undefined_instruction
  44         ldr     pc, _software_interrupt
  45         ldr     pc, _prefetch_abort
  46         ldr     pc, _data_abort
  47         ldr     pc, _not_used
  48         ldr     pc, _irq
  49         ldr     pc, _fiq
  50
  51 _undefined_instruction: .word undefined_instruction
  52 _software_interrupt:    .word software_interrupt
  53 _prefetch_abort:        .word prefetch_abort
  54 _data_abort:            .word data_abort
  55 _not_used:              .word not_used
  56 _irq:                   .word irq
  57 _fiq:                   .word fiq
  58
  59         .balignl 16,0xdeadbeef
  60
  61
  62 /*
  63  *************************************************************************
  64  *
  65  * Startup Code (reset vector)
  66  *
  67  * do important init only if we don't start from memory!
  68  * relocate armboot to ram
  69  * setup stack
  70  * jump to second stage
  71  *
  72  *************************************************************************
  73  */
  74
  75 .globl _TEXT_BASE
  76 _TEXT_BASE:
  77 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  78         .word   CONFIG_SPL_TEXT_BASE
  79 #else
  80         .word   CONFIG_SYS_TEXT_BASE
  81 #endif
  82
  83 /*
  84  * These are defined in the board-specific linker script.
  85  * Subtracting _start from them lets the linker put their
  86  * relative position in the executable instead of leaving
  87  * them null.
  88  */
  89 .globl _bss_start_ofs
  90 _bss_start_ofs:
  91         .word __bss_start - _start
  92
  93 .globl _image_copy_end_ofs
  94 _image_copy_end_ofs:
  95         .word __image_copy_end - _start
  96
  97 .globl _bss_end_ofs
  98 _bss_end_ofs:
  99         .word __bss_end - _start
 100
 101 .globl _end_ofs
 102 _end_ofs:
 103         .word _end - _start
 104
 105 #ifdef CONFIG_USE_IRQ
 106 /* IRQ stack memory (calculated at run-time) */
 107 .globl IRQ_STACK_START
 108 IRQ_STACK_START:
 109         .word   0x0badc0de
 110
 111 /* IRQ stack memory (calculated at run-time) */
 112 .globl FIQ_STACK_START
 113 FIQ_STACK_START:
 114         .word 0x0badc0de
 115 #endif
 116
 117 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 118 .globl IRQ_STACK_START_IN
 119 IRQ_STACK_START_IN:
 120         .word   0x0badc0de
 121
 122 /*
 123  * the actual reset code
 124  */
 125
 126 reset:
 127         /*
 128          * set the cpu to SVC32 mode
 129          */
 130         mrs     r0,cpsr
 131         bic     r0,r0,#0x1f
 132         orr     r0,r0,#0xd3
 133         msr     cpsr,r0
 134
 135         /*
 136          * we do sys-critical inits only at reboot,
 137          * not when booting from ram!
 138          */
 139 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 140         bl      cpu_init_crit
 141 #endif
 142
 143         bl      _main
 144
 145 /*------------------------------------------------------------------------------*/
 146
 147 /*
 148  * void relocate_code(addr_moni)
 149  *
 150  * This function relocates the monitor code.
 151  */
 152         .globl  relocate_code
 153 relocate_code:
 154         mov     r6, r0  /* save addr of destination */
 155
 156         adr     r0, _start
 157         subs    r9, r6, r0              /* r9 <- relocation offset */
 158         beq     relocate_done           /* skip relocation */
 159         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 160         ldr     r3, _image_copy_end_ofs
 161         add     r2, r0, r3              /* r2 <- source end address         */
 162
 163 copy_loop:
 164         ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
 165         stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
 166         cmp     r0, r2                  /* until source end address [r2]    */
 167         blo     copy_loop
 168
 169 #ifndef CONFIG_SPL_BUILD
 170         /*
 171          * fix .rel.dyn relocations
 172          */
 173         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 174         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 175         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 176         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 177         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 178         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 179         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 180 fixloop:
 181         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 182         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 183         ldr     r1, [r2, #4]
 184         and     r7, r1, #0xff
 185         cmp     r7, #23                 /* relative fixup? */
 186         beq     fixrel
 187         cmp     r7, #2                  /* absolute fixup? */
 188         beq     fixabs
 189         /* ignore unknown type of fixup */
 190         b       fixnext
 191 fixabs:
 192         /* absolute fix: set location to (offset) symbol value */
 193         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 194         add     r1, r10, r1             /* r1 <- address of symbol in table */
 195         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 196         add     r1, r1, r9              /* r1 <- relocated sym addr */
 197         b       fixnext
 198 fixrel:
 199         /* relative fix: increase location by offset */
 200         ldr     r1, [r0]
 201         add     r1, r1, r9
 202 fixnext:
 203         str     r1, [r0]
 204         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 205         cmp     r2, r3
 206         blo     fixloop
 207 #endif
 208
 209 relocate_done:
 210
 211         mov     pc, lr
 212
 213 _rel_dyn_start_ofs:
 214         .word __rel_dyn_start - _start
 215 _rel_dyn_end_ofs:
 216         .word __rel_dyn_end - _start
 217 _dynsym_start_ofs:
 218         .word __dynsym_start - _start
 219
 220         .globl  c_runtime_cpu_setup
 221 c_runtime_cpu_setup:
 222
 223         mov     pc, lr
 224
 225 /*
 226  *************************************************************************
 227  *
 228  * CPU_init_critical registers
 229  *
 230  * setup important registers
 231  * setup memory timing
 232  *
 233  *************************************************************************
 234  */
 235
 236
 237 /* Interrupt-Controller base address */
 238 IC_BASE:        .word   0x90050000
 239 #define ICMR    0x04
 240
 241
 242 /* Reset-Controller */
 243 RST_BASE:               .word   0x90030000
 244 #define RSRR    0x00
 245 #define RCSR    0x04
 246
 247
 248 /* PWR */
 249 PWR_BASE:               .word   0x90020000
 250 #define PSPR    0x08
 251 #define PPCR    0x14
 252 cpuspeed:               .word   CONFIG_SYS_CPUSPEED
 253
 254
 255 cpu_init_crit:
 256         /*
 257          * mask all IRQs
 258          */
 259         ldr     r0, IC_BASE
 260         mov     r1, #0x00
 261         str     r1, [r0, #ICMR]
 262
 263         /* set clock speed */
 264         ldr     r0, PWR_BASE
 265         ldr     r1, cpuspeed
 266         str     r1, [r0, #PPCR]
 267
 268         /*
 269          * before relocating, we have to setup RAM timing
 270          * because memory timing is board-dependend, you will
 271          * find a lowlevel_init.S in your board directory.
 272          */
 273         mov     ip,     lr
 274         bl      lowlevel_init
 275         mov     lr,     ip
 276
 277         /*
 278          * disable MMU stuff and enable I-cache
 279          */
 280         mrc     p15,0,r0,c1,c0
 281         bic     r0, r0, #0x00002000     @ clear bit 13 (X)
 282         bic     r0, r0, #0x0000000f     @ clear bits 3-0 (WCAM)
 283         orr     r0, r0, #0x00001000     @ set bit 12 (I) Icache
 284         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 285         mcr     p15,0,r0,c1,c0
 286
 287         /*
 288          * flush v4 I/D caches
 289          */
 290         mov     r0, #0
 291         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 292         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 293
 294         mov     pc, lr
 295
 296
 297 /*
 298  *************************************************************************
 299  *
 300  * Interrupt handling
 301  *
 302  *************************************************************************
 303  */
 304
 305 @
 306 @ IRQ stack frame.
 307 @
 308 #define S_FRAME_SIZE    72
 309
 310 #define S_OLD_R0        68
 311 #define S_PSR           64
 312 #define S_PC            60
 313 #define S_LR            56
 314 #define S_SP            52
 315
 316 #define S_IP            48
 317 #define S_FP            44
 318 #define S_R10           40
 319 #define S_R9            36
 320 #define S_R8            32
 321 #define S_R7            28
 322 #define S_R6            24
 323 #define S_R5            20
 324 #define S_R4            16
 325 #define S_R3            12
 326 #define S_R2            8
 327 #define S_R1            4
 328 #define S_R0            0
 329
 330 #define MODE_SVC 0x13
 331 #define I_BIT    0x80
 332
 333 /*
 334  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 335  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 336  */
 337
 338         .macro  bad_save_user_regs
 339         sub     sp, sp, #S_FRAME_SIZE
 340         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 341         add     r8, sp, #S_PC
 342
 343         ldr     r2, IRQ_STACK_START_IN
 344         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 345         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 346
 347         add     r5, sp, #S_SP
 348         mov     r1, lr
 349         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 350         mov     r0, sp
 351         .endm
 352
 353         .macro  irq_save_user_regs
 354         sub     sp, sp, #S_FRAME_SIZE
 355         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 356         add     r8, sp, #S_PC
 357         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 358         str     lr, [r8, #0]                    @ Save calling PC
 359         mrs     r6, spsr
 360         str     r6, [r8, #4]                    @ Save CPSR
 361         str     r0, [r8, #8]                    @ Save OLD_R0
 362         mov     r0, sp
 363         .endm
 364
 365         .macro  irq_restore_user_regs
 366         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 367         mov     r0, r0
 368         ldr     lr, [sp, #S_PC]                 @ Get PC
 369         add     sp, sp, #S_FRAME_SIZE
 370         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 371         .endm
 372
 373         .macro get_bad_stack
 374         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 375
 376         str     lr, [r13]                       @ save caller lr / spsr
 377         mrs     lr, spsr
 378         str     lr, [r13, #4]
 379
 380         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 381         msr     spsr_c, r13
 382         mov     lr, pc
 383         movs    pc, lr
 384         .endm
 385
 386         .macro get_irq_stack                    @ setup IRQ stack
 387         ldr     sp, IRQ_STACK_START
 388         .endm
 389
 390         .macro get_fiq_stack                    @ setup FIQ stack
 391         ldr     sp, FIQ_STACK_START
 392         .endm
 393
 394 /*
 395  * exception handlers
 396  */
 397         .align  5
 398 undefined_instruction:
 399         get_bad_stack
 400         bad_save_user_regs
 401         bl      do_undefined_instruction
 402
 403         .align  5
 404 software_interrupt:
 405         get_bad_stack
 406         bad_save_user_regs
 407         bl      do_software_interrupt
 408
 409         .align  5
 410 prefetch_abort:
 411         get_bad_stack
 412         bad_save_user_regs
 413         bl      do_prefetch_abort
 414
 415         .align  5
 416 data_abort:
 417         get_bad_stack
 418         bad_save_user_regs
 419         bl      do_data_abort
 420
 421         .align  5
 422 not_used:
 423         get_bad_stack
 424         bad_save_user_regs
 425         bl      do_not_used
 426
 427 #ifdef CONFIG_USE_IRQ
 428
 429         .align  5
 430 irq:
 431         get_irq_stack
 432         irq_save_user_regs
 433         bl      do_irq
 434         irq_restore_user_regs
 435
 436         .align  5
 437 fiq:
 438         get_fiq_stack
 439         /* someone ought to write a more effiction fiq_save_user_regs */
 440         irq_save_user_regs
 441         bl      do_fiq
 442         irq_restore_user_regs
 443
 444 #else
 445
 446         .align  5
 447 irq:
 448         get_bad_stack
 449         bad_save_user_regs
 450         bl      do_irq
 451
 452         .align  5
 453 fiq:
 454         get_bad_stack
 455         bad_save_user_regs
 456         bl      do_fiq
 457
 458 #endif
 459
 460         .align  5
 461 .globl reset_cpu
 462 reset_cpu:
 463         ldr     r0, RST_BASE
 464         mov     r1, #0x0                        @ set bit 3-0 ...
 465         str     r1, [r0, #RCSR]                 @ ... to clear in RCSR
 466         mov     r1, #0x1
 467         str     r1, [r0, #RSRR]                 @ and perform reset
 468         b       reset_cpu                       @ silly, but repeat endlessly