arch/arm/cpu/tegra-common/board.c

   1 /*
   2  *  (C) Copyright 2010,2011
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/funcmux.h>
  12 #include <asm/arch/tegra.h>
  13 #include <asm/arch-tegra/board.h>
  14 #include <asm/arch-tegra/pmc.h>
  15 #include <asm/arch-tegra/sys_proto.h>
  16 #include <asm/arch-tegra/warmboot.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 enum {
  21         /* UARTs which we can enable */
  22         UARTA   = 1 << 0,
  23         UARTB   = 1 << 1,
  24         UARTC   = 1 << 2,
  25         UARTD   = 1 << 3,
  26         UARTE   = 1 << 4,
  27         UART_COUNT = 5,
  28 };
  29
  30 /*
  31  * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
  32  * so we are using this value to identify memory size.
  33  */
  34
  35 unsigned int query_sdram_size(void)
  36 {
  37         struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  38         u32 reg;
  39
  40         reg = readl(&pmc->pmc_scratch20);
  41         debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
  42
  43 #if defined(CONFIG_TEGRA20)
  44         /* bits 30:28 in OdmData are used for RAM size on T20  */
  45         reg &= 0x70000000;
  46
  47         switch ((reg) >> 28) {
  48         case 1:
  49                 return 0x10000000;      /* 256 MB */
  50         case 0:
  51         case 2:
  52         default:
  53                 return 0x20000000;      /* 512 MB */
  54         case 3:
  55                 return 0x40000000;      /* 1GB */
  56         }
  57 #else   /* Tegra30/Tegra114 */
  58         /* bits 31:28 in OdmData are used for RAM size on T30  */
  59         switch ((reg) >> 28) {
  60         case 0:
  61         case 1:
  62         default:
  63                 return 0x10000000;      /* 256 MB */
  64         case 2:
  65                 return 0x20000000;      /* 512 MB */
  66         case 3:
  67                 return 0x30000000;      /* 768 MB */
  68         case 4:
  69                 return 0x40000000;      /* 1GB */
  70         case 8:
  71                 return 0x7ff00000;      /* 2GB - 1MB */
  72         }
  73 #endif
  74 }
  75
  76 int dram_init(void)
  77 {
  78         /* We do not initialise DRAM here. We just query the size */
  79         gd->ram_size = query_sdram_size();
  80         return 0;
  81 }
  82
  83 #ifdef CONFIG_DISPLAY_BOARDINFO
  84 int checkboard(void)
  85 {
  86         printf("Board: %s\n", sysinfo.board_string);
  87         return 0;
  88 }
  89 #endif  /* CONFIG_DISPLAY_BOARDINFO */
  90
  91 static int uart_configs[] = {
  92 #if defined(CONFIG_TEGRA20)
  93  #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  94         FUNCMUX_UART1_UAA_UAB,
  95  #elif defined(CONFIG_TEGRA_UARTA_GPU)
  96         FUNCMUX_UART1_GPU,
  97  #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  98         FUNCMUX_UART1_SDIO1,
  99  #else
 100         FUNCMUX_UART1_IRRX_IRTX,
 101 #endif
 102         FUNCMUX_UART2_UAD,
 103         -1,
 104         FUNCMUX_UART4_GMC,
 105         -1,
 106 #elif defined(CONFIG_TEGRA30)
 107         FUNCMUX_UART1_ULPI,     /* UARTA */
 108         -1,
 109         -1,
 110         -1,
 111         -1,
 112 #else   /* Tegra114 */
 113         -1,
 114         -1,
 115         -1,
 116         FUNCMUX_UART4_GMI,      /* UARTD */
 117         -1,
 118 #endif
 119 };
 120
 121 /**
 122  * Set up the specified uarts
 123  *
 124  * @param uarts_ids     Mask containing UARTs to init (UARTx)
 125  */
 126 static void setup_uarts(int uart_ids)
 127 {
 128         static enum periph_id id_for_uart[] = {
 129                 PERIPH_ID_UART1,
 130                 PERIPH_ID_UART2,
 131                 PERIPH_ID_UART3,
 132                 PERIPH_ID_UART4,
 133                 PERIPH_ID_UART5,
 134         };
 135         size_t i;
 136
 137         for (i = 0; i < UART_COUNT; i++) {
 138                 if (uart_ids & (1 << i)) {
 139                         enum periph_id id = id_for_uart[i];
 140
 141                         funcmux_select(id, uart_configs[i]);
 142                         clock_ll_start_uart(id);
 143                 }
 144         }
 145 }
 146
 147 void board_init_uart_f(void)
 148 {
 149         int uart_ids = 0;       /* bit mask of which UART ids to enable */
 150
 151 #ifdef CONFIG_TEGRA_ENABLE_UARTA
 152         uart_ids |= UARTA;
 153 #endif
 154 #ifdef CONFIG_TEGRA_ENABLE_UARTB
 155         uart_ids |= UARTB;
 156 #endif
 157 #ifdef CONFIG_TEGRA_ENABLE_UARTC
 158         uart_ids |= UARTC;
 159 #endif
 160 #ifdef CONFIG_TEGRA_ENABLE_UARTD
 161         uart_ids |= UARTD;
 162 #endif
 163 #ifdef CONFIG_TEGRA_ENABLE_UARTE
 164         uart_ids |= UARTE;
 165 #endif
 166         setup_uarts(uart_ids);
 167 }
 168
 169 #ifndef CONFIG_SYS_DCACHE_OFF
 170 void enable_caches(void)
 171 {
 172         /* Enable D-cache. I-cache is already enabled in start.S */
 173         dcache_enable();
 174 }
 175 #endif