arch/arm/cpu/tegra20-common/clock.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /* Tegra20 Clock control functions */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/tegra.h>
  13 #include <asm/arch-tegra/clk_rst.h>
  14 #include <asm/arch-tegra/timer.h>
  15 #include <div64.h>
  16 #include <fdtdec.h>
  17
  18 /*
  19  * Clock types that we can use as a source. The Tegra20 has muxes for the
  20  * peripheral clocks, and in most cases there are four options for the clock
  21  * source. This gives us a clock 'type' and exploits what commonality exists
  22  * in the device.
  23  *
  24  * Letters are obvious, except for T which means CLK_M, and S which means the
  25  * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  26  * datasheet) and PLL_M are different things. The former is the basic
  27  * clock supplied to the SOC from an external oscillator. The latter is the
  28  * memory clock PLL.
  29  *
  30  * See definitions in clock_id in the header file.
  31  */
  32 enum clock_type_id {
  33         CLOCK_TYPE_AXPT,        /* PLL_A, PLL_X, PLL_P, CLK_M */
  34         CLOCK_TYPE_MCPA,        /* and so on */
  35         CLOCK_TYPE_MCPT,
  36         CLOCK_TYPE_PCM,
  37         CLOCK_TYPE_PCMT,
  38         CLOCK_TYPE_PCMT16,      /* CLOCK_TYPE_PCMT with 16-bit divider */
  39         CLOCK_TYPE_PCXTS,
  40         CLOCK_TYPE_PDCT,
  41
  42         CLOCK_TYPE_COUNT,
  43         CLOCK_TYPE_NONE = -1,   /* invalid clock type */
  44 };
  45
  46 enum {
  47         CLOCK_MAX_MUX   = 4     /* number of source options for each clock */
  48 };
  49
  50 /*
  51  * Clock source mux for each clock type. This just converts our enum into
  52  * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
  53  * is special as it has 5 sources. Since it also has a different number of
  54  * bits in its register for the source, we just handle it with a special
  55  * case in the code.
  56  */
  57 #define CLK(x) CLOCK_ID_ ## x
  58 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
  59         { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC)        },
  60         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO)      },
  61         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC)        },
  62         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE)       },
  63         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC)        },
  64         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC)        },
  65         { CLK(PERIPH),  CLK(CGENERAL),  CLK(XCPU),      CLK(OSC)        },
  66         { CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC)        },
  67 };
  68
  69 /*
  70  * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
  71  * not in the header file since it is for purely internal use - we want
  72  * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
  73  * confusion bewteen PERIPH_ID_... and PERIPHC_...
  74  *
  75  * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
  76  * confusing.
  77  *
  78  * Note to SOC vendors: perhaps define a unified numbering for peripherals and
  79  * use it for reset, clock enable, clock source/divider and even pinmuxing
  80  * if you can.
  81  */
  82 enum periphc_internal_id {
  83         /* 0x00 */
  84         PERIPHC_I2S1,
  85         PERIPHC_I2S2,
  86         PERIPHC_SPDIF_OUT,
  87         PERIPHC_SPDIF_IN,
  88         PERIPHC_PWM,
  89         PERIPHC_SPI1,
  90         PERIPHC_SPI2,
  91         PERIPHC_SPI3,
  92
  93         /* 0x08 */
  94         PERIPHC_XIO,
  95         PERIPHC_I2C1,
  96         PERIPHC_DVC_I2C,
  97         PERIPHC_TWC,
  98         PERIPHC_0c,
  99         PERIPHC_10,     /* PERIPHC_SPI1, what is this really? */
 100         PERIPHC_DISP1,
 101         PERIPHC_DISP2,
 102
 103         /* 0x10 */
 104         PERIPHC_CVE,
 105         PERIPHC_IDE0,
 106         PERIPHC_VI,
 107         PERIPHC_1c,
 108         PERIPHC_SDMMC1,
 109         PERIPHC_SDMMC2,
 110         PERIPHC_G3D,
 111         PERIPHC_G2D,
 112
 113         /* 0x18 */
 114         PERIPHC_NDFLASH,
 115         PERIPHC_SDMMC4,
 116         PERIPHC_VFIR,
 117         PERIPHC_EPP,
 118         PERIPHC_MPE,
 119         PERIPHC_MIPI,
 120         PERIPHC_UART1,
 121         PERIPHC_UART2,
 122
 123         /* 0x20 */
 124         PERIPHC_HOST1X,
 125         PERIPHC_21,
 126         PERIPHC_TVO,
 127         PERIPHC_HDMI,
 128         PERIPHC_24,
 129         PERIPHC_TVDAC,
 130         PERIPHC_I2C2,
 131         PERIPHC_EMC,
 132
 133         /* 0x28 */
 134         PERIPHC_UART3,
 135         PERIPHC_29,
 136         PERIPHC_VI_SENSOR,
 137         PERIPHC_2b,
 138         PERIPHC_2c,
 139         PERIPHC_SPI4,
 140         PERIPHC_I2C3,
 141         PERIPHC_SDMMC3,
 142
 143         /* 0x30 */
 144         PERIPHC_UART4,
 145         PERIPHC_UART5,
 146         PERIPHC_VDE,
 147         PERIPHC_OWR,
 148         PERIPHC_NOR,
 149         PERIPHC_CSITE,
 150
 151         PERIPHC_COUNT,
 152
 153         PERIPHC_NONE = -1,
 154 };
 155
 156 /*
 157  * Clock type for each peripheral clock source. We put the name in each
 158  * record just so it is easy to match things up
 159  */
 160 #define TYPE(name, type) type
 161 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 162         /* 0x00 */
 163         TYPE(PERIPHC_I2S1,      CLOCK_TYPE_AXPT),
 164         TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
 165         TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
 166         TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
 167         TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCXTS),
 168         TYPE(PERIPHC_SPI1,      CLOCK_TYPE_PCMT),
 169         TYPE(PERIPHC_SPI22,     CLOCK_TYPE_PCMT),
 170         TYPE(PERIPHC_SPI3,      CLOCK_TYPE_PCMT),
 171
 172         /* 0x08 */
 173         TYPE(PERIPHC_XIO,       CLOCK_TYPE_PCMT),
 174         TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
 175         TYPE(PERIPHC_DVC_I2C,   CLOCK_TYPE_PCMT16),
 176         TYPE(PERIPHC_TWC,       CLOCK_TYPE_PCMT),
 177         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 178         TYPE(PERIPHC_SPI1,      CLOCK_TYPE_PCMT),
 179         TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PDCT),
 180         TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PDCT),
 181
 182         /* 0x10 */
 183         TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
 184         TYPE(PERIPHC_IDE0,      CLOCK_TYPE_PCMT),
 185         TYPE(PERIPHC_VI,        CLOCK_TYPE_MCPA),
 186         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 187         TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
 188         TYPE(PERIPHC_SDMMC2,    CLOCK_TYPE_PCMT),
 189         TYPE(PERIPHC_G3D,       CLOCK_TYPE_MCPA),
 190         TYPE(PERIPHC_G2D,       CLOCK_TYPE_MCPA),
 191
 192         /* 0x18 */
 193         TYPE(PERIPHC_NDFLASH,   CLOCK_TYPE_PCMT),
 194         TYPE(PERIPHC_SDMMC4,    CLOCK_TYPE_PCMT),
 195         TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
 196         TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
 197         TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
 198         TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),
 199         TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
 200         TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),
 201
 202         /* 0x20 */
 203         TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
 204         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 205         TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
 206         TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PDCT),
 207         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 208         TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
 209         TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
 210         TYPE(PERIPHC_EMC,       CLOCK_TYPE_MCPT),
 211
 212         /* 0x28 */
 213         TYPE(PERIPHC_UART3,     CLOCK_TYPE_PCMT),
 214         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 215         TYPE(PERIPHC_VI,        CLOCK_TYPE_MCPA),
 216         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 217         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 218         TYPE(PERIPHC_SPI4,      CLOCK_TYPE_PCMT),
 219         TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
 220         TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),
 221
 222         /* 0x30 */
 223         TYPE(PERIPHC_UART4,     CLOCK_TYPE_PCMT),
 224         TYPE(PERIPHC_UART5,     CLOCK_TYPE_PCMT),
 225         TYPE(PERIPHC_VDE,       CLOCK_TYPE_PCMT),
 226         TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
 227         TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
 228         TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
 229 };
 230
 231 /*
 232  * This array translates a periph_id to a periphc_internal_id
 233  *
 234  * Not present/matched up:
 235  *      uint vi_sensor;  _VI_SENSOR_0,          0x1A8
 236  *      SPDIF - which is both 0x08 and 0x0c
 237  *
 238  */
 239 #define NONE(name) (-1)
 240 #define OFFSET(name, value) PERIPHC_ ## name
 241 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 242         /* Low word: 31:0 */
 243         NONE(CPU),
 244         NONE(RESERVED1),
 245         NONE(RESERVED2),
 246         NONE(AC97),
 247         NONE(RTC),
 248         NONE(TMR),
 249         PERIPHC_UART1,
 250         PERIPHC_UART2,  /* and vfir 0x68 */
 251
 252         /* 0x08 */
 253         NONE(GPIO),
 254         PERIPHC_SDMMC2,
 255         NONE(SPDIF),            /* 0x08 and 0x0c, unclear which to use */
 256         PERIPHC_I2S1,
 257         PERIPHC_I2C1,
 258         PERIPHC_NDFLASH,
 259         PERIPHC_SDMMC1,
 260         PERIPHC_SDMMC4,
 261
 262         /* 0x10 */
 263         PERIPHC_TWC,
 264         PERIPHC_PWM,
 265         PERIPHC_I2S2,
 266         PERIPHC_EPP,
 267         PERIPHC_VI,
 268         PERIPHC_G2D,
 269         NONE(USBD),
 270         NONE(ISP),
 271
 272         /* 0x18 */
 273         PERIPHC_G3D,
 274         PERIPHC_IDE0,
 275         PERIPHC_DISP2,
 276         PERIPHC_DISP1,
 277         PERIPHC_HOST1X,
 278         NONE(VCP),
 279         NONE(RESERVED30),
 280         NONE(CACHE2),
 281
 282         /* Middle word: 63:32 */
 283         NONE(MEM),
 284         NONE(AHBDMA),
 285         NONE(APBDMA),
 286         NONE(RESERVED35),
 287         NONE(KBC),
 288         NONE(STAT_MON),
 289         NONE(PMC),
 290         NONE(FUSE),
 291
 292         /* 0x28 */
 293         NONE(KFUSE),
 294         NONE(SBC1),     /* SBC1, 0x34, is this SPI1? */
 295         PERIPHC_NOR,
 296         PERIPHC_SPI1,
 297         PERIPHC_SPI2,
 298         PERIPHC_XIO,
 299         PERIPHC_SPI3,
 300         PERIPHC_DVC_I2C,
 301
 302         /* 0x30 */
 303         NONE(DSI),
 304         PERIPHC_TVO,    /* also CVE 0x40 */
 305         PERIPHC_MIPI,
 306         PERIPHC_HDMI,
 307         PERIPHC_CSITE,
 308         PERIPHC_TVDAC,
 309         PERIPHC_I2C2,
 310         PERIPHC_UART3,
 311
 312         /* 0x38 */
 313         NONE(RESERVED56),
 314         PERIPHC_EMC,
 315         NONE(USB2),
 316         NONE(USB3),
 317         PERIPHC_MPE,
 318         PERIPHC_VDE,
 319         NONE(BSEA),
 320         NONE(BSEV),
 321
 322         /* Upper word 95:64 */
 323         NONE(SPEEDO),
 324         PERIPHC_UART4,
 325         PERIPHC_UART5,
 326         PERIPHC_I2C3,
 327         PERIPHC_SPI4,
 328         PERIPHC_SDMMC3,
 329         NONE(PCIE),
 330         PERIPHC_OWR,
 331
 332         /* 0x48 */
 333         NONE(AFI),
 334         NONE(CORESIGHT),
 335         NONE(RESERVED74),
 336         NONE(AVPUCQ),
 337         NONE(RESERVED76),
 338         NONE(RESERVED77),
 339         NONE(RESERVED78),
 340         NONE(RESERVED79),
 341
 342         /* 0x50 */
 343         NONE(RESERVED80),
 344         NONE(RESERVED81),
 345         NONE(RESERVED82),
 346         NONE(RESERVED83),
 347         NONE(IRAMA),
 348         NONE(IRAMB),
 349         NONE(IRAMC),
 350         NONE(IRAMD),
 351
 352         /* 0x58 */
 353         NONE(CRAM2),
 354 };
 355
 356 /*
 357  * Get the oscillator frequency, from the corresponding hardware configuration
 358  * field. T20 has 4 frequencies that it supports.
 359  */
 360 enum clock_osc_freq clock_get_osc_freq(void)
 361 {
 362         struct clk_rst_ctlr *clkrst =
 363                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 364         u32 reg;
 365
 366         reg = readl(&clkrst->crc_osc_ctrl);
 367         return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 368 }
 369
 370 /* Returns a pointer to the clock source register for a peripheral */
 371 u32 *get_periph_source_reg(enum periph_id periph_id)
 372 {
 373         struct clk_rst_ctlr *clkrst =
 374                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 375         enum periphc_internal_id internal_id;
 376
 377         assert(clock_periph_id_isvalid(periph_id));
 378         internal_id = periph_id_to_internal_id[periph_id];
 379         assert(internal_id != -1);
 380         return &clkrst->crc_clk_src[internal_id];
 381 }
 382
 383 /**
 384  * Given a peripheral ID and the required source clock, this returns which
 385  * value should be programmed into the source mux for that peripheral.
 386  *
 387  * There is special code here to handle the one source type with 5 sources.
 388  *
 389  * @param periph_id     peripheral to start
 390  * @param source        PLL id of required parent clock
 391  * @param mux_bits      Set to number of bits in mux register: 2 or 4
 392  * @param divider_bits  Set to number of divider bits (8 or 16)
 393  * @return mux value (0-4, or -1 if not found)
 394  */
 395 int get_periph_clock_source(enum periph_id periph_id,
 396                 enum clock_id parent, int *mux_bits, int *divider_bits)
 397 {
 398         enum clock_type_id type;
 399         enum periphc_internal_id internal_id;
 400         int mux;
 401
 402         assert(clock_periph_id_isvalid(periph_id));
 403
 404         internal_id = periph_id_to_internal_id[periph_id];
 405         assert(periphc_internal_id_isvalid(internal_id));
 406
 407         type = clock_periph_type[internal_id];
 408         assert(clock_type_id_isvalid(type));
 409
 410         /*
 411          * Special cases here for the clock with a 4-bit source mux and I2C
 412          * with its 16-bit divisor
 413          */
 414         if (type == CLOCK_TYPE_PCXTS)
 415                 *mux_bits = 4;
 416         else
 417                 *mux_bits = 2;
 418         if (type == CLOCK_TYPE_PCMT16)
 419                 *divider_bits = 16;
 420         else
 421                 *divider_bits = 8;
 422
 423         for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
 424                 if (clock_source[type][mux] == parent)
 425                         return mux;
 426
 427         /*
 428          * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
 429          * which is not in our table. If not, then they are asking for a
 430          * source which this peripheral can't access through its mux.
 431          */
 432         assert(type == CLOCK_TYPE_PCXTS);
 433         assert(parent == CLOCK_ID_SFROM32KHZ);
 434         if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
 435                 return 4;       /* mux value for this clock */
 436
 437         /* if we get here, either us or the caller has made a mistake */
 438         printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
 439                 parent);
 440         return -1;
 441 }
 442
 443 void clock_set_enable(enum periph_id periph_id, int enable)
 444 {
 445         struct clk_rst_ctlr *clkrst =
 446                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 447         u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
 448         u32 reg;
 449
 450         /* Enable/disable the clock to this peripheral */
 451         assert(clock_periph_id_isvalid(periph_id));
 452         reg = readl(clk);
 453         if (enable)
 454                 reg |= PERIPH_MASK(periph_id);
 455         else
 456                 reg &= ~PERIPH_MASK(periph_id);
 457         writel(reg, clk);
 458 }
 459
 460 void reset_set_enable(enum periph_id periph_id, int enable)
 461 {
 462         struct clk_rst_ctlr *clkrst =
 463                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 464         u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
 465         u32 reg;
 466
 467         /* Enable/disable reset to the peripheral */
 468         assert(clock_periph_id_isvalid(periph_id));
 469         reg = readl(reset);
 470         if (enable)
 471                 reg |= PERIPH_MASK(periph_id);
 472         else
 473                 reg &= ~PERIPH_MASK(periph_id);
 474         writel(reg, reset);
 475 }
 476
 477 #ifdef CONFIG_OF_CONTROL
 478 /*
 479  * Convert a device tree clock ID to our peripheral ID. They are mostly
 480  * the same but we are very cautious so we check that a valid clock ID is
 481  * provided.
 482  *
 483  * @param clk_id        Clock ID according to tegra20 device tree binding
 484  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
 485  */
 486 enum periph_id clk_id_to_periph_id(int clk_id)
 487 {
 488         if (clk_id > PERIPH_ID_COUNT)
 489                 return PERIPH_ID_NONE;
 490
 491         switch (clk_id) {
 492         case PERIPH_ID_RESERVED1:
 493         case PERIPH_ID_RESERVED2:
 494         case PERIPH_ID_RESERVED30:
 495         case PERIPH_ID_RESERVED35:
 496         case PERIPH_ID_RESERVED56:
 497         case PERIPH_ID_RESERVED74:
 498         case PERIPH_ID_RESERVED76:
 499         case PERIPH_ID_RESERVED77:
 500         case PERIPH_ID_RESERVED78:
 501         case PERIPH_ID_RESERVED79:
 502         case PERIPH_ID_RESERVED80:
 503         case PERIPH_ID_RESERVED81:
 504         case PERIPH_ID_RESERVED82:
 505         case PERIPH_ID_RESERVED83:
 506         case PERIPH_ID_RESERVED91:
 507                 return PERIPH_ID_NONE;
 508         default:
 509                 return clk_id;
 510         }
 511 }
 512 #endif /* CONFIG_OF_CONTROL */
 513
 514 void clock_early_init(void)
 515 {
 516         /*
 517          * PLLP output frequency set to 216MHz
 518          * PLLC output frequency set to 600Mhz
 519          *
 520          * TODO: Can we calculate these values instead of hard-coding?
 521          */
 522         switch (clock_get_osc_freq()) {
 523         case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
 524                 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
 525                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
 526                 break;
 527
 528         case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
 529                 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
 530                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
 531                 break;
 532
 533         case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
 534                 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
 535                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
 536                 break;
 537         case CLOCK_OSC_FREQ_19_2:
 538         default:
 539                 /*
 540                  * These are not supported. It is too early to print a
 541                  * message and the UART likely won't work anyway due to the
 542                  * oscillator being wrong.
 543                  */
 544                 break;
 545         }
 546 }
 547
 548 void arch_timer_init(void)
 549 {
 550 }