2 * (C) Copyright 2010 - 2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch/sdram_param.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/fuse.h>
21 #include <asm/arch-tegra/warmboot.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #ifndef CONFIG_TEGRA_CLOCK_SCALING
26 #error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
30 * This is the place in SRAM where the SDRAM parameters are stored. There
31 * are 4 blocks, one for each RAM code
33 #define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
35 /* TODO: If we later add support for the Misc GP controller, refactor this */
73 * TODO: This register is not documented in the TRM yet. We could move this
74 * into the EMC and give it a proper interface, but not while it is
77 union fbio_spare_reg
{
85 /* We pack the resume information into these unions for later */
89 u32 pllm_base_divn
:10;
91 u32 pllm_misc_lfcon
:4;
92 u32 pllm_misc_cpcon
:4;
93 u32 gp_xm2cfga_padctrl_preemp
:1;
94 u32 gp_xm2cfgd_padctrl_schmt
:1;
103 u32 emc_clock_divider
:8;
104 u32 pllm_stable_time
:8;
105 u32 pllx_stable_time
:8;
106 u32 emc_fbio_spare_cfg_wb0
:8;
111 union scratch24_reg
{
113 u32 emc_auto_cal_wait
:8;
114 u32 emc_pin_program_wait
:8;
121 int warmboot_save_sdram_params(void)
124 struct sdram_params sdram
;
125 struct pmux_tri_ctlr
*pmt
= (struct pmux_tri_ctlr
*)NV_PA_APB_MISC_BASE
;
126 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
127 struct apb_misc_gp_ctlr
*gp
=
128 (struct apb_misc_gp_ctlr
*)NV_PA_APB_MISC_GP_BASE
;
129 struct emc_ctlr
*emc
= emc_get_controller(gd
->fdt_blob
);
130 union scratch2_reg scratch2
;
131 union scratch4_reg scratch4
;
132 union scratch24_reg scratch24
;
133 union xm2cfga_reg xm2cfga
;
134 union xm2cfgd_reg xm2cfgd
;
135 union fbio_spare_reg fbio_spare
;
137 /* get ram code that is used as index to array sdram_params in BCT */
138 ram_code
= (readl(&pmt
->pmt_strap_opt_a
) >>
139 STRAP_OPT_A_RAM_CODE_SHIFT
) & 3;
141 (char *)((struct sdram_params
*)SDRAM_PARAMS_BASE
+ ram_code
),
144 xm2cfga
.word
= readl(&gp
->xm2cfga
);
145 xm2cfgd
.word
= readl(&gp
->xm2cfgd
);
148 scratch2
.osc_ctrl_xobp
= clock_get_osc_bypass();
150 /* Get the memory PLL settings */
152 u32 divm
, divn
, divp
, cpcon
, lfcon
;
154 if (clock_ll_read_pll(CLOCK_ID_MEMORY
, &divm
, &divn
, &divp
,
157 scratch2
.pllm_base_divm
= divm
;
158 scratch2
.pllm_base_divn
= divn
;
159 scratch2
.pllm_base_divp
= divp
;
160 scratch2
.pllm_misc_cpcon
= cpcon
;
161 scratch2
.pllm_misc_lfcon
= lfcon
;
164 scratch2
.gp_xm2cfga_padctrl_preemp
= xm2cfga
.preemp_en
;
165 scratch2
.gp_xm2cfgd_padctrl_schmt
= xm2cfgd
.schmt_en
;
166 scratch2
.memory_type
= sdram
.memory_type
;
167 writel(scratch2
.word
, &pmc
->pmc_scratch2
);
169 /* collect data from various sources for pmc_scratch4 */
170 fbio_spare
.word
= readl(&emc
->fbio_spare
);
172 scratch4
.emc_fbio_spare_cfg_wb0
= fbio_spare
.cfg_wb0
;
173 scratch4
.emc_clock_divider
= sdram
.emc_clock_divider
;
174 scratch4
.pllm_stable_time
= -1;
175 scratch4
.pllx_stable_time
= -1;
176 writel(scratch4
.word
, &pmc
->pmc_scratch4
);
178 /* collect various data from sdram for pmc_scratch24 */
180 scratch24
.emc_pin_program_wait
= sdram
.emc_pin_program_wait
;
181 scratch24
.emc_auto_cal_wait
= sdram
.emc_auto_cal_wait
;
182 scratch24
.warmboot_wait
= sdram
.warm_boot_wait
;
183 writel(scratch24
.word
, &pmc
->pmc_scratch24
);
188 static u32
get_major_version(void)
191 struct apb_misc_gp_ctlr
*gp
=
192 (struct apb_misc_gp_ctlr
*)NV_PA_APB_MISC_GP_BASE
;
194 major_id
= (readl(&gp
->hidrev
) & HIDREV_MAJORPREV_MASK
) >>
195 HIDREV_MAJORPREV_SHIFT
;
199 static int is_production_mode_fuse_set(struct fuse_regs
*fuse
)
201 return readl(&fuse
->production_mode
);
204 static int is_odm_production_mode_fuse_set(struct fuse_regs
*fuse
)
206 return readl(&fuse
->security_mode
);
209 static int is_failure_analysis_mode(struct fuse_regs
*fuse
)
211 return readl(&fuse
->fa
);
214 static int ap20_is_odm_production_mode(void)
216 struct fuse_regs
*fuse
= (struct fuse_regs
*)NV_PA_FUSE_BASE
;
218 if (!is_failure_analysis_mode(fuse
) &&
219 is_odm_production_mode_fuse_set(fuse
))
225 static int ap20_is_production_mode(void)
227 struct fuse_regs
*fuse
= (struct fuse_regs
*)NV_PA_FUSE_BASE
;
229 if (get_major_version() == 0)
232 if (!is_failure_analysis_mode(fuse
) &&
233 is_production_mode_fuse_set(fuse
) &&
234 !is_odm_production_mode_fuse_set(fuse
))
240 static enum fuse_operating_mode
fuse_get_operation_mode(void)
243 struct apb_misc_gp_ctlr
*gp
=
244 (struct apb_misc_gp_ctlr
*)NV_PA_APB_MISC_GP_BASE
;
246 chip_id
= (readl(&gp
->hidrev
) & HIDREV_CHIPID_MASK
) >>
248 if (chip_id
== CHIPID_TEGRA20
) {
249 if (ap20_is_odm_production_mode()) {
250 printf("!! odm_production_mode is not supported !!\n");
251 return MODE_UNDEFINED
;
253 if (ap20_is_production_mode())
254 return MODE_PRODUCTION
;
256 return MODE_UNDEFINED
;
258 return MODE_UNDEFINED
;
261 static void determine_crypto_options(int *is_encrypted
, int *is_signed
,
264 switch (fuse_get_operation_mode()) {
265 case MODE_PRODUCTION
:
279 static int sign_wb_code(u32 start
, u32 length
, int use_zero_key
)
282 u8
*source
; /* Pointer to source */
285 /* Calculate AES block parameters. */
286 source
= (u8
*)(start
+ offsetof(struct wb_header
, random_aes_block
));
287 length
-= offsetof(struct wb_header
, random_aes_block
);
288 hash
= (u8
*)(start
+ offsetof(struct wb_header
, hash
));
289 err
= sign_data_block(source
, length
, hash
);
294 int warmboot_prepare_code(u32 seg_address
, u32 seg_length
)
297 u32 length
; /* length of the signed/encrypt code */
298 struct wb_header
*dst_header
; /* Pointer to dest WB header */
299 int is_encrypted
; /* Segment is encrypted */
300 int is_signed
; /* Segment is signed */
301 int use_zero_key
; /* Use key of all zeros */
303 /* Determine crypto options. */
304 determine_crypto_options(&is_encrypted
, &is_signed
, &use_zero_key
);
306 /* Get the actual code limits. */
307 length
= roundup(((u32
)wb_end
- (u32
)wb_start
), 16);
310 * The region specified by seg_address must be in SDRAM and must be
313 if (seg_length
== 0 || seg_address
< NV_PA_SDRAM_BASE
||
314 seg_address
+ seg_length
>= NV_PA_SDRAM_BASE
+ gd
->ram_size
) {
319 /* Things must be 16-byte aligned. */
320 if ((seg_length
& 0xF) || (seg_address
& 0xF)) {
325 /* Will the code fit? (destination includes wb_header + wb code) */
326 if (seg_length
< (length
+ sizeof(struct wb_header
))) {
331 dst_header
= (struct wb_header
*)seg_address
;
332 memset((char *)dst_header
, 0, sizeof(struct wb_header
));
334 /* Populate the random_aes_block as requested. */
336 u32
*aes_block
= (u32
*)&(dst_header
->random_aes_block
);
337 u32
*end
= (u32
*)(((u32
)aes_block
) +
338 sizeof(dst_header
->random_aes_block
));
342 } while (aes_block
< end
);
345 /* Populate the header. */
346 dst_header
->length_insecure
= length
+ sizeof(struct wb_header
);
347 dst_header
->length_secure
= length
+ sizeof(struct wb_header
);
348 dst_header
->destination
= NV_WB_RUN_ADDRESS
;
349 dst_header
->entry_point
= NV_WB_RUN_ADDRESS
;
350 dst_header
->code_length
= length
;
353 printf("!!!! Encryption is not supported !!!!\n");
354 dst_header
->length_insecure
= 0;
358 /* copy the wb code directly following dst_header. */
359 memcpy((char *)(dst_header
+1), (char *)wb_start
, length
);
362 err
= sign_wb_code(seg_address
, dst_header
->length_insecure
,
367 printf("Warning: warmboot code copy failed (error=%d)\n", err
);