arch/arm/dts/dra74x.dtsi

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include "dra7.dtsi"
  11
  12 / {
  13         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
  14
  15         cpus {
  16                 cpu@1 {
  17                         device_type = "cpu";
  18                         compatible = "arm,cortex-a15";
  19                         reg = <1>;
  20                         operating-points-v2 = <&cpu0_opp_table>;
  21                 };
  22         };
  23
  24         pmu {
  25                 compatible = "arm,cortex-a15-pmu";
  26                 interrupt-parent = <&wakeupgen>;
  27                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  28                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  29         };
  30
  31         ocp {
  32                 dsp2_system: dsp_system@41500000 {
  33                         compatible = "syscon";
  34                         reg = <0x41500000 0x100>;
  35                 };
  36
  37                 omap_dwc3_4: omap_dwc3_4@48940000 {
  38                         compatible = "ti,dwc3";
  39                         ti,hwmods = "usb_otg_ss4";
  40                         reg = <0x48940000 0x10000>;
  41                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  42                         #address-cells = <1>;
  43                         #size-cells = <1>;
  44                         utmi-mode = <2>;
  45                         ranges;
  46                         status = "disabled";
  47                         usb4: usb@48950000 {
  48                                 compatible = "snps,dwc3";
  49                                 reg = <0x48950000 0x17000>;
  50                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  51                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  52                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  53                                 interrupt-names = "peripheral",
  54                                                   "host",
  55                                                   "otg";
  56                                 maximum-speed = "high-speed";
  57                                 dr_mode = "otg";
  58                         };
  59                 };
  60
  61                 mmu0_dsp2: mmu@41501000 {
  62                         compatible = "ti,dra7-dsp-iommu";
  63                         reg = <0x41501000 0x100>;
  64                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  65                         ti,hwmods = "mmu0_dsp2";
  66                         #iommu-cells = <0>;
  67                         ti,syscon-mmuconfig = <&dsp2_system 0x0>;
  68                         status = "disabled";
  69                 };
  70
  71                 mmu1_dsp2: mmu@41502000 {
  72                         compatible = "ti,dra7-dsp-iommu";
  73                         reg = <0x41502000 0x100>;
  74                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  75                         ti,hwmods = "mmu1_dsp2";
  76                         #iommu-cells = <0>;
  77                         ti,syscon-mmuconfig = <&dsp2_system 0x1>;
  78                         status = "disabled";
  79                 };
  80         };
  81 };
  82
  83 &cpu0_opp_table {
  84         opp-shared;
  85 };
  86
  87 &dss {
  88         reg = <0x58000000 0x80>,
  89               <0x58004054 0x4>,
  90               <0x58004300 0x20>,
  91               <0x58009054 0x4>,
  92               <0x58009300 0x20>;
  93         reg-names = "dss", "pll1_clkctrl", "pll1",
  94                     "pll2_clkctrl", "pll2";
  95
  96         clocks = <&dss_dss_clk>,
  97                  <&dss_video1_clk>,
  98                  <&dss_video2_clk>;
  99         clock-names = "fck", "video1_clk", "video2_clk";
 100 };
 101
 102 &mailbox5 {
 103         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 104                 ti,mbox-tx = <6 2 2>;
 105                 ti,mbox-rx = <4 2 2>;
 106                 status = "disabled";
 107         };
 108         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 109                 ti,mbox-tx = <5 2 2>;
 110                 ti,mbox-rx = <1 2 2>;
 111                 status = "disabled";
 112         };
 113 };
 114
 115 &mailbox6 {
 116         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 117                 ti,mbox-tx = <6 2 2>;
 118                 ti,mbox-rx = <4 2 2>;
 119                 status = "disabled";
 120         };
 121         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 122                 ti,mbox-tx = <5 2 2>;
 123                 ti,mbox-rx = <1 2 2>;
 124                 status = "disabled";
 125         };
 126 };