arch/arm/dts/dra7xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for DRA7xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         atl_clkin0_ck: atl_clkin0_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,dra7-atl-clock";
  14                 clocks = <&atl_gfclk_mux>;
  15         };
  16
  17         atl_clkin1_ck: atl_clkin1_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,dra7-atl-clock";
  20                 clocks = <&atl_gfclk_mux>;
  21         };
  22
  23         atl_clkin2_ck: atl_clkin2_ck {
  24                 #clock-cells = <0>;
  25                 compatible = "ti,dra7-atl-clock";
  26                 clocks = <&atl_gfclk_mux>;
  27         };
  28
  29         atl_clkin3_ck: atl_clkin3_ck {
  30                 #clock-cells = <0>;
  31                 compatible = "ti,dra7-atl-clock";
  32                 clocks = <&atl_gfclk_mux>;
  33         };
  34
  35         hdmi_clkin_ck: hdmi_clkin_ck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <0>;
  39         };
  40
  41         mlb_clkin_ck: mlb_clkin_ck {
  42                 #clock-cells = <0>;
  43                 compatible = "fixed-clock";
  44                 clock-frequency = <0>;
  45         };
  46
  47         mlbp_clkin_ck: mlbp_clkin_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-clock";
  50                 clock-frequency = <0>;
  51         };
  52
  53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <100000000>;
  57         };
  58
  59         ref_clkin0_ck: ref_clkin0_ck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <0>;
  63         };
  64
  65         ref_clkin1_ck: ref_clkin1_ck {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <0>;
  69         };
  70
  71         ref_clkin2_ck: ref_clkin2_ck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <0>;
  75         };
  76
  77         ref_clkin3_ck: ref_clkin3_ck {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         rmii_clk_ck: rmii_clk_ck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <0>;
  87         };
  88
  89         sdvenc_clkin_ck: sdvenc_clkin_ck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <0>;
  93         };
  94
  95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99         };
 100
 101         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-clock";
 104                 clock-frequency = <32768>;
 105         };
 106
 107         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-factor-clock";
 110                 clocks = <&sys_clkin1>;
 111                 clock-mult = <1>;
 112                 clock-div = <610>;
 113         };
 114
 115         virt_12000000_ck: virt_12000000_ck {
 116                 #clock-cells = <0>;
 117                 compatible = "fixed-clock";
 118                 clock-frequency = <12000000>;
 119         };
 120
 121         virt_13000000_ck: virt_13000000_ck {
 122                 #clock-cells = <0>;
 123                 compatible = "fixed-clock";
 124                 clock-frequency = <13000000>;
 125         };
 126
 127         virt_16800000_ck: virt_16800000_ck {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-clock";
 130                 clock-frequency = <16800000>;
 131         };
 132
 133         virt_19200000_ck: virt_19200000_ck {
 134                 #clock-cells = <0>;
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <19200000>;
 137         };
 138
 139         virt_20000000_ck: virt_20000000_ck {
 140                 #clock-cells = <0>;
 141                 compatible = "fixed-clock";
 142                 clock-frequency = <20000000>;
 143         };
 144
 145         virt_26000000_ck: virt_26000000_ck {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-clock";
 148                 clock-frequency = <26000000>;
 149         };
 150
 151         virt_27000000_ck: virt_27000000_ck {
 152                 #clock-cells = <0>;
 153                 compatible = "fixed-clock";
 154                 clock-frequency = <27000000>;
 155         };
 156
 157         virt_38400000_ck: virt_38400000_ck {
 158                 #clock-cells = <0>;
 159                 compatible = "fixed-clock";
 160                 clock-frequency = <38400000>;
 161         };
 162
 163         sys_clkin2: sys_clkin2 {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-clock";
 166                 clock-frequency = <22579200>;
 167         };
 168
 169         usb_otg_clkin_ck: usb_otg_clkin_ck {
 170                 #clock-cells = <0>;
 171                 compatible = "fixed-clock";
 172                 clock-frequency = <0>;
 173         };
 174
 175         video1_clkin_ck: video1_clkin_ck {
 176                 #clock-cells = <0>;
 177                 compatible = "fixed-clock";
 178                 clock-frequency = <0>;
 179         };
 180
 181         video1_m2_clkin_ck: video1_m2_clkin_ck {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-clock";
 184                 clock-frequency = <0>;
 185         };
 186
 187         video2_clkin_ck: video2_clkin_ck {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-frequency = <0>;
 191         };
 192
 193         video2_m2_clkin_ck: video2_m2_clkin_ck {
 194                 #clock-cells = <0>;
 195                 compatible = "fixed-clock";
 196                 clock-frequency = <0>;
 197         };
 198
 199         dpll_abe_ck: dpll_abe_ck@1e0 {
 200                 #clock-cells = <0>;
 201                 compatible = "ti,omap4-dpll-m4xen-clock";
 202                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 203                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 204         };
 205
 206         dpll_abe_x2_ck: dpll_abe_x2_ck {
 207                 #clock-cells = <0>;
 208                 compatible = "ti,omap4-dpll-x2-clock";
 209                 clocks = <&dpll_abe_ck>;
 210         };
 211
 212         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 213                 #clock-cells = <0>;
 214                 compatible = "ti,divider-clock";
 215                 clocks = <&dpll_abe_x2_ck>;
 216                 ti,max-div = <31>;
 217                 ti,autoidle-shift = <8>;
 218                 reg = <0x01f0>;
 219                 ti,index-starts-at-one;
 220                 ti,invert-autoidle-bit;
 221         };
 222
 223         abe_clk: abe_clk@108 {
 224                 #clock-cells = <0>;
 225                 compatible = "ti,divider-clock";
 226                 clocks = <&dpll_abe_m2x2_ck>;
 227                 ti,max-div = <4>;
 228                 reg = <0x0108>;
 229                 ti,index-power-of-two;
 230         };
 231
 232         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 233                 #clock-cells = <0>;
 234                 compatible = "ti,divider-clock";
 235                 clocks = <&dpll_abe_ck>;
 236                 ti,max-div = <31>;
 237                 ti,autoidle-shift = <8>;
 238                 reg = <0x01f0>;
 239                 ti,index-starts-at-one;
 240                 ti,invert-autoidle-bit;
 241         };
 242
 243         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,divider-clock";
 246                 clocks = <&dpll_abe_x2_ck>;
 247                 ti,max-div = <31>;
 248                 ti,autoidle-shift = <8>;
 249                 reg = <0x01f4>;
 250                 ti,index-starts-at-one;
 251                 ti,invert-autoidle-bit;
 252         };
 253
 254         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 255                 #clock-cells = <0>;
 256                 compatible = "ti,mux-clock";
 257                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 258                 ti,bit-shift = <23>;
 259                 reg = <0x012c>;
 260         };
 261
 262         dpll_core_ck: dpll_core_ck@120 {
 263                 #clock-cells = <0>;
 264                 compatible = "ti,omap4-dpll-core-clock";
 265                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 266                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 267         };
 268
 269         dpll_core_x2_ck: dpll_core_x2_ck {
 270                 #clock-cells = <0>;
 271                 compatible = "ti,omap4-dpll-x2-clock";
 272                 clocks = <&dpll_core_ck>;
 273         };
 274
 275         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 276                 #clock-cells = <0>;
 277                 compatible = "ti,divider-clock";
 278                 clocks = <&dpll_core_x2_ck>;
 279                 ti,max-div = <63>;
 280                 ti,autoidle-shift = <8>;
 281                 reg = <0x013c>;
 282                 ti,index-starts-at-one;
 283                 ti,invert-autoidle-bit;
 284         };
 285
 286         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 287                 #clock-cells = <0>;
 288                 compatible = "fixed-factor-clock";
 289                 clocks = <&dpll_core_h12x2_ck>;
 290                 clock-mult = <1>;
 291                 clock-div = <1>;
 292         };
 293
 294         dpll_mpu_ck: dpll_mpu_ck@160 {
 295                 #clock-cells = <0>;
 296                 compatible = "ti,omap5-mpu-dpll-clock";
 297                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 298                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 299         };
 300
 301         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 302                 #clock-cells = <0>;
 303                 compatible = "ti,divider-clock";
 304                 clocks = <&dpll_mpu_ck>;
 305                 ti,max-div = <31>;
 306                 ti,autoidle-shift = <8>;
 307                 reg = <0x0170>;
 308                 ti,index-starts-at-one;
 309                 ti,invert-autoidle-bit;
 310         };
 311
 312         mpu_dclk_div: mpu_dclk_div {
 313                 #clock-cells = <0>;
 314                 compatible = "fixed-factor-clock";
 315                 clocks = <&dpll_mpu_m2_ck>;
 316                 clock-mult = <1>;
 317                 clock-div = <1>;
 318         };
 319
 320         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 321                 #clock-cells = <0>;
 322                 compatible = "fixed-factor-clock";
 323                 clocks = <&dpll_core_h12x2_ck>;
 324                 clock-mult = <1>;
 325                 clock-div = <1>;
 326         };
 327
 328         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 329                 #clock-cells = <0>;
 330                 compatible = "ti,mux-clock";
 331                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 332                 ti,bit-shift = <23>;
 333                 reg = <0x0240>;
 334         };
 335
 336         dpll_dsp_ck: dpll_dsp_ck@234 {
 337                 #clock-cells = <0>;
 338                 compatible = "ti,omap4-dpll-clock";
 339                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 340                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 341                 assigned-clocks = <&dpll_dsp_ck>;
 342                 assigned-clock-rates = <600000000>;
 343         };
 344
 345         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 346                 #clock-cells = <0>;
 347                 compatible = "ti,divider-clock";
 348                 clocks = <&dpll_dsp_ck>;
 349                 ti,max-div = <31>;
 350                 ti,autoidle-shift = <8>;
 351                 reg = <0x0244>;
 352                 ti,index-starts-at-one;
 353                 ti,invert-autoidle-bit;
 354                 assigned-clocks = <&dpll_dsp_m2_ck>;
 355                 assigned-clock-rates = <600000000>;
 356         };
 357
 358         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 359                 #clock-cells = <0>;
 360                 compatible = "fixed-factor-clock";
 361                 clocks = <&dpll_core_h12x2_ck>;
 362                 clock-mult = <1>;
 363                 clock-div = <1>;
 364         };
 365
 366         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 367                 #clock-cells = <0>;
 368                 compatible = "ti,mux-clock";
 369                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 370                 ti,bit-shift = <23>;
 371                 reg = <0x01ac>;
 372         };
 373
 374         dpll_iva_ck: dpll_iva_ck@1a0 {
 375                 #clock-cells = <0>;
 376                 compatible = "ti,omap4-dpll-clock";
 377                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 378                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 379                 assigned-clocks = <&dpll_iva_ck>;
 380                 assigned-clock-rates = <1165000000>;
 381         };
 382
 383         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 384                 #clock-cells = <0>;
 385                 compatible = "ti,divider-clock";
 386                 clocks = <&dpll_iva_ck>;
 387                 ti,max-div = <31>;
 388                 ti,autoidle-shift = <8>;
 389                 reg = <0x01b0>;
 390                 ti,index-starts-at-one;
 391                 ti,invert-autoidle-bit;
 392                 assigned-clocks = <&dpll_iva_m2_ck>;
 393                 assigned-clock-rates = <388333334>;
 394         };
 395
 396         iva_dclk: iva_dclk {
 397                 #clock-cells = <0>;
 398                 compatible = "fixed-factor-clock";
 399                 clocks = <&dpll_iva_m2_ck>;
 400                 clock-mult = <1>;
 401                 clock-div = <1>;
 402         };
 403
 404         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 405                 #clock-cells = <0>;
 406                 compatible = "ti,mux-clock";
 407                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 408                 ti,bit-shift = <23>;
 409                 reg = <0x02e4>;
 410         };
 411
 412         dpll_gpu_ck: dpll_gpu_ck@2d8 {
 413                 #clock-cells = <0>;
 414                 compatible = "ti,omap4-dpll-clock";
 415                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 416                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 417                 assigned-clocks = <&dpll_gpu_ck>;
 418                 assigned-clock-rates = <1277000000>;
 419         };
 420
 421         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 422                 #clock-cells = <0>;
 423                 compatible = "ti,divider-clock";
 424                 clocks = <&dpll_gpu_ck>;
 425                 ti,max-div = <31>;
 426                 ti,autoidle-shift = <8>;
 427                 reg = <0x02e8>;
 428                 ti,index-starts-at-one;
 429                 ti,invert-autoidle-bit;
 430                 assigned-clocks = <&dpll_gpu_m2_ck>;
 431                 assigned-clock-rates = <425666667>;
 432         };
 433
 434         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 435                 #clock-cells = <0>;
 436                 compatible = "ti,divider-clock";
 437                 clocks = <&dpll_core_ck>;
 438                 ti,max-div = <31>;
 439                 ti,autoidle-shift = <8>;
 440                 reg = <0x0130>;
 441                 ti,index-starts-at-one;
 442                 ti,invert-autoidle-bit;
 443         };
 444
 445         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 446                 #clock-cells = <0>;
 447                 compatible = "fixed-factor-clock";
 448                 clocks = <&dpll_core_m2_ck>;
 449                 clock-mult = <1>;
 450                 clock-div = <1>;
 451         };
 452
 453         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 454                 #clock-cells = <0>;
 455                 compatible = "ti,mux-clock";
 456                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 457                 ti,bit-shift = <23>;
 458                 reg = <0x021c>;
 459         };
 460
 461         dpll_ddr_ck: dpll_ddr_ck@210 {
 462                 #clock-cells = <0>;
 463                 compatible = "ti,omap4-dpll-clock";
 464                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 465                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 466         };
 467
 468         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 469                 #clock-cells = <0>;
 470                 compatible = "ti,divider-clock";
 471                 clocks = <&dpll_ddr_ck>;
 472                 ti,max-div = <31>;
 473                 ti,autoidle-shift = <8>;
 474                 reg = <0x0220>;
 475                 ti,index-starts-at-one;
 476                 ti,invert-autoidle-bit;
 477         };
 478
 479         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 480                 #clock-cells = <0>;
 481                 compatible = "ti,mux-clock";
 482                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 483                 ti,bit-shift = <23>;
 484                 reg = <0x02b4>;
 485         };
 486
 487         dpll_gmac_ck: dpll_gmac_ck@2a8 {
 488                 #clock-cells = <0>;
 489                 compatible = "ti,omap4-dpll-clock";
 490                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 491                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 492         };
 493
 494         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 495                 #clock-cells = <0>;
 496                 compatible = "ti,divider-clock";
 497                 clocks = <&dpll_gmac_ck>;
 498                 ti,max-div = <31>;
 499                 ti,autoidle-shift = <8>;
 500                 reg = <0x02b8>;
 501                 ti,index-starts-at-one;
 502                 ti,invert-autoidle-bit;
 503         };
 504
 505         video2_dclk_div: video2_dclk_div {
 506                 #clock-cells = <0>;
 507                 compatible = "fixed-factor-clock";
 508                 clocks = <&video2_m2_clkin_ck>;
 509                 clock-mult = <1>;
 510                 clock-div = <1>;
 511         };
 512
 513         video1_dclk_div: video1_dclk_div {
 514                 #clock-cells = <0>;
 515                 compatible = "fixed-factor-clock";
 516                 clocks = <&video1_m2_clkin_ck>;
 517                 clock-mult = <1>;
 518                 clock-div = <1>;
 519         };
 520
 521         hdmi_dclk_div: hdmi_dclk_div {
 522                 #clock-cells = <0>;
 523                 compatible = "fixed-factor-clock";
 524                 clocks = <&hdmi_clkin_ck>;
 525                 clock-mult = <1>;
 526                 clock-div = <1>;
 527         };
 528
 529         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 530                 #clock-cells = <0>;
 531                 compatible = "fixed-factor-clock";
 532                 clocks = <&dpll_abe_m3x2_ck>;
 533                 clock-mult = <1>;
 534                 clock-div = <2>;
 535         };
 536
 537         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 538                 #clock-cells = <0>;
 539                 compatible = "fixed-factor-clock";
 540                 clocks = <&dpll_abe_m3x2_ck>;
 541                 clock-mult = <1>;
 542                 clock-div = <3>;
 543         };
 544
 545         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 546                 #clock-cells = <0>;
 547                 compatible = "fixed-factor-clock";
 548                 clocks = <&dpll_core_h12x2_ck>;
 549                 clock-mult = <1>;
 550                 clock-div = <1>;
 551         };
 552
 553         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 554                 #clock-cells = <0>;
 555                 compatible = "ti,mux-clock";
 556                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 557                 ti,bit-shift = <23>;
 558                 reg = <0x0290>;
 559         };
 560
 561         dpll_eve_ck: dpll_eve_ck@284 {
 562                 #clock-cells = <0>;
 563                 compatible = "ti,omap4-dpll-clock";
 564                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 565                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 566         };
 567
 568         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 569                 #clock-cells = <0>;
 570                 compatible = "ti,divider-clock";
 571                 clocks = <&dpll_eve_ck>;
 572                 ti,max-div = <31>;
 573                 ti,autoidle-shift = <8>;
 574                 reg = <0x0294>;
 575                 ti,index-starts-at-one;
 576                 ti,invert-autoidle-bit;
 577         };
 578
 579         eve_dclk_div: eve_dclk_div {
 580                 #clock-cells = <0>;
 581                 compatible = "fixed-factor-clock";
 582                 clocks = <&dpll_eve_m2_ck>;
 583                 clock-mult = <1>;
 584                 clock-div = <1>;
 585         };
 586
 587         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 588                 #clock-cells = <0>;
 589                 compatible = "ti,divider-clock";
 590                 clocks = <&dpll_core_x2_ck>;
 591                 ti,max-div = <63>;
 592                 ti,autoidle-shift = <8>;
 593                 reg = <0x0140>;
 594                 ti,index-starts-at-one;
 595                 ti,invert-autoidle-bit;
 596         };
 597
 598         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 599                 #clock-cells = <0>;
 600                 compatible = "ti,divider-clock";
 601                 clocks = <&dpll_core_x2_ck>;
 602                 ti,max-div = <63>;
 603                 ti,autoidle-shift = <8>;
 604                 reg = <0x0144>;
 605                 ti,index-starts-at-one;
 606                 ti,invert-autoidle-bit;
 607         };
 608
 609         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 610                 #clock-cells = <0>;
 611                 compatible = "ti,divider-clock";
 612                 clocks = <&dpll_core_x2_ck>;
 613                 ti,max-div = <63>;
 614                 ti,autoidle-shift = <8>;
 615                 reg = <0x0154>;
 616                 ti,index-starts-at-one;
 617                 ti,invert-autoidle-bit;
 618         };
 619
 620         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 621                 #clock-cells = <0>;
 622                 compatible = "ti,divider-clock";
 623                 clocks = <&dpll_core_x2_ck>;
 624                 ti,max-div = <63>;
 625                 ti,autoidle-shift = <8>;
 626                 reg = <0x0158>;
 627                 ti,index-starts-at-one;
 628                 ti,invert-autoidle-bit;
 629         };
 630
 631         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 632                 #clock-cells = <0>;
 633                 compatible = "ti,divider-clock";
 634                 clocks = <&dpll_core_x2_ck>;
 635                 ti,max-div = <63>;
 636                 ti,autoidle-shift = <8>;
 637                 reg = <0x015c>;
 638                 ti,index-starts-at-one;
 639                 ti,invert-autoidle-bit;
 640         };
 641
 642         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 643                 #clock-cells = <0>;
 644                 compatible = "ti,omap4-dpll-x2-clock";
 645                 clocks = <&dpll_ddr_ck>;
 646         };
 647
 648         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 649                 #clock-cells = <0>;
 650                 compatible = "ti,divider-clock";
 651                 clocks = <&dpll_ddr_x2_ck>;
 652                 ti,max-div = <63>;
 653                 ti,autoidle-shift = <8>;
 654                 reg = <0x0228>;
 655                 ti,index-starts-at-one;
 656                 ti,invert-autoidle-bit;
 657         };
 658
 659         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 660                 #clock-cells = <0>;
 661                 compatible = "ti,omap4-dpll-x2-clock";
 662                 clocks = <&dpll_dsp_ck>;
 663         };
 664
 665         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 666                 #clock-cells = <0>;
 667                 compatible = "ti,divider-clock";
 668                 clocks = <&dpll_dsp_x2_ck>;
 669                 ti,max-div = <31>;
 670                 ti,autoidle-shift = <8>;
 671                 reg = <0x0248>;
 672                 ti,index-starts-at-one;
 673                 ti,invert-autoidle-bit;
 674                 assigned-clocks = <&dpll_dsp_m3x2_ck>;
 675                 assigned-clock-rates = <400000000>;
 676         };
 677
 678         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 679                 #clock-cells = <0>;
 680                 compatible = "ti,omap4-dpll-x2-clock";
 681                 clocks = <&dpll_gmac_ck>;
 682         };
 683
 684         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 685                 #clock-cells = <0>;
 686                 compatible = "ti,divider-clock";
 687                 clocks = <&dpll_gmac_x2_ck>;
 688                 ti,max-div = <63>;
 689                 ti,autoidle-shift = <8>;
 690                 reg = <0x02c0>;
 691                 ti,index-starts-at-one;
 692                 ti,invert-autoidle-bit;
 693         };
 694
 695         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 696                 #clock-cells = <0>;
 697                 compatible = "ti,divider-clock";
 698                 clocks = <&dpll_gmac_x2_ck>;
 699                 ti,max-div = <63>;
 700                 ti,autoidle-shift = <8>;
 701                 reg = <0x02c4>;
 702                 ti,index-starts-at-one;
 703                 ti,invert-autoidle-bit;
 704         };
 705
 706         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 707                 #clock-cells = <0>;
 708                 compatible = "ti,divider-clock";
 709                 clocks = <&dpll_gmac_x2_ck>;
 710                 ti,max-div = <63>;
 711                 ti,autoidle-shift = <8>;
 712                 reg = <0x02c8>;
 713                 ti,index-starts-at-one;
 714                 ti,invert-autoidle-bit;
 715         };
 716
 717         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 718                 #clock-cells = <0>;
 719                 compatible = "ti,divider-clock";
 720                 clocks = <&dpll_gmac_x2_ck>;
 721                 ti,max-div = <31>;
 722                 ti,autoidle-shift = <8>;
 723                 reg = <0x02bc>;
 724                 ti,index-starts-at-one;
 725                 ti,invert-autoidle-bit;
 726         };
 727
 728         gmii_m_clk_div: gmii_m_clk_div {
 729                 #clock-cells = <0>;
 730                 compatible = "fixed-factor-clock";
 731                 clocks = <&dpll_gmac_h11x2_ck>;
 732                 clock-mult = <1>;
 733                 clock-div = <2>;
 734         };
 735
 736         hdmi_clk2_div: hdmi_clk2_div {
 737                 #clock-cells = <0>;
 738                 compatible = "fixed-factor-clock";
 739                 clocks = <&hdmi_clkin_ck>;
 740                 clock-mult = <1>;
 741                 clock-div = <1>;
 742         };
 743
 744         hdmi_div_clk: hdmi_div_clk {
 745                 #clock-cells = <0>;
 746                 compatible = "fixed-factor-clock";
 747                 clocks = <&hdmi_clkin_ck>;
 748                 clock-mult = <1>;
 749                 clock-div = <1>;
 750         };
 751
 752         l3_iclk_div: l3_iclk_div@100 {
 753                 #clock-cells = <0>;
 754                 compatible = "ti,divider-clock";
 755                 ti,max-div = <2>;
 756                 ti,bit-shift = <4>;
 757                 reg = <0x0100>;
 758                 clocks = <&dpll_core_h12x2_ck>;
 759                 ti,index-power-of-two;
 760         };
 761
 762         l4_root_clk_div: l4_root_clk_div {
 763                 #clock-cells = <0>;
 764                 compatible = "fixed-factor-clock";
 765                 clocks = <&l3_iclk_div>;
 766                 clock-mult = <1>;
 767                 clock-div = <2>;
 768         };
 769
 770         video1_clk2_div: video1_clk2_div {
 771                 #clock-cells = <0>;
 772                 compatible = "fixed-factor-clock";
 773                 clocks = <&video1_clkin_ck>;
 774                 clock-mult = <1>;
 775                 clock-div = <1>;
 776         };
 777
 778         video1_div_clk: video1_div_clk {
 779                 #clock-cells = <0>;
 780                 compatible = "fixed-factor-clock";
 781                 clocks = <&video1_clkin_ck>;
 782                 clock-mult = <1>;
 783                 clock-div = <1>;
 784         };
 785
 786         video2_clk2_div: video2_clk2_div {
 787                 #clock-cells = <0>;
 788                 compatible = "fixed-factor-clock";
 789                 clocks = <&video2_clkin_ck>;
 790                 clock-mult = <1>;
 791                 clock-div = <1>;
 792         };
 793
 794         video2_div_clk: video2_div_clk {
 795                 #clock-cells = <0>;
 796                 compatible = "fixed-factor-clock";
 797                 clocks = <&video2_clkin_ck>;
 798                 clock-mult = <1>;
 799                 clock-div = <1>;
 800         };
 801
 802         ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 803                 #clock-cells = <0>;
 804                 compatible = "ti,mux-clock";
 805                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 806                 ti,bit-shift = <24>;
 807                 reg = <0x0520>;
 808                 assigned-clocks = <&ipu1_gfclk_mux>;
 809                 assigned-clock-parents = <&dpll_core_h22x2_ck>;
 810         };
 811
 812         mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
 813                 #clock-cells = <0>;
 814                 compatible = "ti,mux-clock";
 815                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 816                 ti,bit-shift = <28>;
 817                 reg = <0x0550>;
 818         };
 819
 820         mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
 821                 #clock-cells = <0>;
 822                 compatible = "ti,mux-clock";
 823                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 824                 ti,bit-shift = <24>;
 825                 reg = <0x0550>;
 826         };
 827
 828         mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
 829                 #clock-cells = <0>;
 830                 compatible = "ti,mux-clock";
 831                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
 832                 ti,bit-shift = <22>;
 833                 reg = <0x0550>;
 834         };
 835
 836         timer5_gfclk_mux: timer5_gfclk_mux@558 {
 837                 #clock-cells = <0>;
 838                 compatible = "ti,mux-clock";
 839                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 840                 ti,bit-shift = <24>;
 841                 reg = <0x0558>;
 842         };
 843
 844         timer6_gfclk_mux: timer6_gfclk_mux@560 {
 845                 #clock-cells = <0>;
 846                 compatible = "ti,mux-clock";
 847                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 848                 ti,bit-shift = <24>;
 849                 reg = <0x0560>;
 850         };
 851
 852         timer7_gfclk_mux: timer7_gfclk_mux@568 {
 853                 #clock-cells = <0>;
 854                 compatible = "ti,mux-clock";
 855                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 856                 ti,bit-shift = <24>;
 857                 reg = <0x0568>;
 858         };
 859
 860         timer8_gfclk_mux: timer8_gfclk_mux@570 {
 861                 #clock-cells = <0>;
 862                 compatible = "ti,mux-clock";
 863                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 864                 ti,bit-shift = <24>;
 865                 reg = <0x0570>;
 866         };
 867
 868         uart6_gfclk_mux: uart6_gfclk_mux@580 {
 869                 #clock-cells = <0>;
 870                 compatible = "ti,mux-clock";
 871                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
 872                 ti,bit-shift = <24>;
 873                 reg = <0x0580>;
 874         };
 875
 876         dummy_ck: dummy_ck {
 877                 #clock-cells = <0>;
 878                 compatible = "fixed-clock";
 879                 clock-frequency = <0>;
 880         };
 881 };
 882 &prm_clocks {
 883         sys_clkin1: sys_clkin1@110 {
 884                 #clock-cells = <0>;
 885                 compatible = "ti,mux-clock";
 886                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 887                 reg = <0x0110>;
 888                 ti,index-starts-at-one;
 889         };
 890
 891         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 892                 #clock-cells = <0>;
 893                 compatible = "ti,mux-clock";
 894                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 895                 reg = <0x0118>;
 896         };
 897
 898         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 899                 #clock-cells = <0>;
 900                 compatible = "ti,mux-clock";
 901                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 902                 reg = <0x0114>;
 903         };
 904
 905         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 906                 #clock-cells = <0>;
 907                 compatible = "ti,mux-clock";
 908                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 909                 reg = <0x010c>;
 910         };
 911
 912         abe_24m_fclk: abe_24m_fclk@11c {
 913                 #clock-cells = <0>;
 914                 compatible = "ti,divider-clock";
 915                 clocks = <&dpll_abe_m2x2_ck>;
 916                 reg = <0x011c>;
 917                 ti,dividers = <8>, <16>;
 918         };
 919
 920         aess_fclk: aess_fclk@178 {
 921                 #clock-cells = <0>;
 922                 compatible = "ti,divider-clock";
 923                 clocks = <&abe_clk>;
 924                 reg = <0x0178>;
 925                 ti,max-div = <2>;
 926         };
 927
 928         abe_giclk_div: abe_giclk_div@174 {
 929                 #clock-cells = <0>;
 930                 compatible = "ti,divider-clock";
 931                 clocks = <&aess_fclk>;
 932                 reg = <0x0174>;
 933                 ti,max-div = <2>;
 934         };
 935
 936         abe_lp_clk_div: abe_lp_clk_div@1d8 {
 937                 #clock-cells = <0>;
 938                 compatible = "ti,divider-clock";
 939                 clocks = <&dpll_abe_m2x2_ck>;
 940                 reg = <0x01d8>;
 941                 ti,dividers = <16>, <32>;
 942         };
 943
 944         abe_sys_clk_div: abe_sys_clk_div@120 {
 945                 #clock-cells = <0>;
 946                 compatible = "ti,divider-clock";
 947                 clocks = <&sys_clkin1>;
 948                 reg = <0x0120>;
 949                 ti,max-div = <2>;
 950         };
 951
 952         adc_gfclk_mux: adc_gfclk_mux@1dc {
 953                 #clock-cells = <0>;
 954                 compatible = "ti,mux-clock";
 955                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 956                 reg = <0x01dc>;
 957         };
 958
 959         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 960                 #clock-cells = <0>;
 961                 compatible = "ti,divider-clock";
 962                 clocks = <&sys_clkin1>;
 963                 ti,max-div = <64>;
 964                 reg = <0x01c8>;
 965                 ti,index-power-of-two;
 966         };
 967
 968         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 969                 #clock-cells = <0>;
 970                 compatible = "ti,divider-clock";
 971                 clocks = <&sys_clkin2>;
 972                 ti,max-div = <64>;
 973                 reg = <0x01cc>;
 974                 ti,index-power-of-two;
 975         };
 976
 977         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 978                 #clock-cells = <0>;
 979                 compatible = "ti,divider-clock";
 980                 clocks = <&dpll_abe_m2_ck>;
 981                 ti,max-div = <64>;
 982                 reg = <0x01bc>;
 983                 ti,index-power-of-two;
 984         };
 985
 986         dsp_gclk_div: dsp_gclk_div@18c {
 987                 #clock-cells = <0>;
 988                 compatible = "ti,divider-clock";
 989                 clocks = <&dpll_dsp_m2_ck>;
 990                 ti,max-div = <64>;
 991                 reg = <0x018c>;
 992                 ti,index-power-of-two;
 993         };
 994
 995         gpu_dclk: gpu_dclk@1a0 {
 996                 #clock-cells = <0>;
 997                 compatible = "ti,divider-clock";
 998                 clocks = <&dpll_gpu_m2_ck>;
 999                 ti,max-div = <64>;
1000                 reg = <0x01a0>;
1001                 ti,index-power-of-two;
1002         };
1003
1004         emif_phy_dclk_div: emif_phy_dclk_div@190 {
1005                 #clock-cells = <0>;
1006                 compatible = "ti,divider-clock";
1007                 clocks = <&dpll_ddr_m2_ck>;
1008                 ti,max-div = <64>;
1009                 reg = <0x0190>;
1010                 ti,index-power-of-two;
1011         };
1012
1013         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
1014                 #clock-cells = <0>;
1015                 compatible = "ti,divider-clock";
1016                 clocks = <&dpll_gmac_m2_ck>;
1017                 ti,max-div = <64>;
1018                 reg = <0x019c>;
1019                 ti,index-power-of-two;
1020         };
1021
1022         gmac_main_clk: gmac_main_clk {
1023                 #clock-cells = <0>;
1024                 compatible = "fixed-factor-clock";
1025                 clocks = <&gmac_250m_dclk_div>;
1026                 clock-mult = <1>;
1027                 clock-div = <2>;
1028         };
1029
1030         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1031                 #clock-cells = <0>;
1032                 compatible = "ti,divider-clock";
1033                 clocks = <&dpll_usb_m2_ck>;
1034                 ti,max-div = <64>;
1035                 reg = <0x01ac>;
1036                 ti,index-power-of-two;
1037         };
1038
1039         usb_otg_dclk_div: usb_otg_dclk_div@184 {
1040                 #clock-cells = <0>;
1041                 compatible = "ti,divider-clock";
1042                 clocks = <&usb_otg_clkin_ck>;
1043                 ti,max-div = <64>;
1044                 reg = <0x0184>;
1045                 ti,index-power-of-two;
1046         };
1047
1048         sata_dclk_div: sata_dclk_div@1c0 {
1049                 #clock-cells = <0>;
1050                 compatible = "ti,divider-clock";
1051                 clocks = <&sys_clkin1>;
1052                 ti,max-div = <64>;
1053                 reg = <0x01c0>;
1054                 ti,index-power-of-two;
1055         };
1056
1057         pcie2_dclk_div: pcie2_dclk_div@1b8 {
1058                 #clock-cells = <0>;
1059                 compatible = "ti,divider-clock";
1060                 clocks = <&dpll_pcie_ref_m2_ck>;
1061                 ti,max-div = <64>;
1062                 reg = <0x01b8>;
1063                 ti,index-power-of-two;
1064         };
1065
1066         pcie_dclk_div: pcie_dclk_div@1b4 {
1067                 #clock-cells = <0>;
1068                 compatible = "ti,divider-clock";
1069                 clocks = <&apll_pcie_m2_ck>;
1070                 ti,max-div = <64>;
1071                 reg = <0x01b4>;
1072                 ti,index-power-of-two;
1073         };
1074
1075         emu_dclk_div: emu_dclk_div@194 {
1076                 #clock-cells = <0>;
1077                 compatible = "ti,divider-clock";
1078                 clocks = <&sys_clkin1>;
1079                 ti,max-div = <64>;
1080                 reg = <0x0194>;
1081                 ti,index-power-of-two;
1082         };
1083
1084         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1085                 #clock-cells = <0>;
1086                 compatible = "ti,divider-clock";
1087                 clocks = <&secure_32k_clk_src_ck>;
1088                 ti,max-div = <64>;
1089                 reg = <0x01c4>;
1090                 ti,index-power-of-two;
1091         };
1092
1093         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1094                 #clock-cells = <0>;
1095                 compatible = "ti,mux-clock";
1096                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1097                 reg = <0x0158>;
1098         };
1099
1100         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1101                 #clock-cells = <0>;
1102                 compatible = "ti,mux-clock";
1103                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1104                 reg = <0x015c>;
1105         };
1106
1107         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1108                 #clock-cells = <0>;
1109                 compatible = "ti,mux-clock";
1110                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1111                 reg = <0x0160>;
1112         };
1113
1114         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1115                 #clock-cells = <0>;
1116                 compatible = "fixed-factor-clock";
1117                 clocks = <&sys_clkin1>;
1118                 clock-mult = <1>;
1119                 clock-div = <2>;
1120         };
1121
1122         eve_clk: eve_clk@180 {
1123                 #clock-cells = <0>;
1124                 compatible = "ti,mux-clock";
1125                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1126                 reg = <0x0180>;
1127         };
1128
1129         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1130                 #clock-cells = <0>;
1131                 compatible = "ti,mux-clock";
1132                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1133                 reg = <0x0164>;
1134         };
1135
1136         mlb_clk: mlb_clk@134 {
1137                 #clock-cells = <0>;
1138                 compatible = "ti,divider-clock";
1139                 clocks = <&mlb_clkin_ck>;
1140                 ti,max-div = <64>;
1141                 reg = <0x0134>;
1142                 ti,index-power-of-two;
1143         };
1144
1145         mlbp_clk: mlbp_clk@130 {
1146                 #clock-cells = <0>;
1147                 compatible = "ti,divider-clock";
1148                 clocks = <&mlbp_clkin_ck>;
1149                 ti,max-div = <64>;
1150                 reg = <0x0130>;
1151                 ti,index-power-of-two;
1152         };
1153
1154         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1155                 #clock-cells = <0>;
1156                 compatible = "ti,divider-clock";
1157                 clocks = <&dpll_abe_m2_ck>;
1158                 ti,max-div = <64>;
1159                 reg = <0x0138>;
1160                 ti,index-power-of-two;
1161         };
1162
1163         timer_sys_clk_div: timer_sys_clk_div@144 {
1164                 #clock-cells = <0>;
1165                 compatible = "ti,divider-clock";
1166                 clocks = <&sys_clkin1>;
1167                 reg = <0x0144>;
1168                 ti,max-div = <2>;
1169         };
1170
1171         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1172                 #clock-cells = <0>;
1173                 compatible = "ti,mux-clock";
1174                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1175                 reg = <0x0168>;
1176         };
1177
1178         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1179                 #clock-cells = <0>;
1180                 compatible = "ti,mux-clock";
1181                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1182                 reg = <0x016c>;
1183         };
1184
1185         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1186                 #clock-cells = <0>;
1187                 compatible = "ti,mux-clock";
1188                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1189                 reg = <0x0108>;
1190         };
1191
1192         gpio1_dbclk: gpio1_dbclk@1838 {
1193                 #clock-cells = <0>;
1194                 compatible = "ti,gate-clock";
1195                 clocks = <&sys_32k_ck>;
1196                 ti,bit-shift = <8>;
1197                 reg = <0x1838>;
1198         };
1199
1200         dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1201                 #clock-cells = <0>;
1202                 compatible = "ti,mux-clock";
1203                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1204                 ti,bit-shift = <24>;
1205                 reg = <0x1888>;
1206         };
1207
1208         timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1209                 #clock-cells = <0>;
1210                 compatible = "ti,mux-clock";
1211                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1212                 ti,bit-shift = <24>;
1213                 reg = <0x1840>;
1214         };
1215
1216         uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1217                 #clock-cells = <0>;
1218                 compatible = "ti,mux-clock";
1219                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1220                 ti,bit-shift = <24>;
1221                 reg = <0x1880>;
1222         };
1223 };
1224 &cm_core_clocks {
1225         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1226                 #clock-cells = <0>;
1227                 compatible = "ti,omap4-dpll-clock";
1228                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1229                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1230         };
1231
1232         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1233                 #clock-cells = <0>;
1234                 compatible = "ti,divider-clock";
1235                 clocks = <&dpll_pcie_ref_ck>;
1236                 ti,max-div = <31>;
1237                 ti,autoidle-shift = <8>;
1238                 reg = <0x0210>;
1239                 ti,index-starts-at-one;
1240                 ti,invert-autoidle-bit;
1241         };
1242
1243         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1244                 compatible = "ti,mux-clock";
1245                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1246                 #clock-cells = <0>;
1247                 reg = <0x021c 0x4>;
1248                 ti,bit-shift = <7>;
1249         };
1250
1251         apll_pcie_ck: apll_pcie_ck@21c {
1252                 #clock-cells = <0>;
1253                 compatible = "ti,dra7-apll-clock";
1254                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1255                 reg = <0x021c>, <0x0220>;
1256         };
1257
1258         optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1259                 compatible = "ti,gate-clock";
1260                 clocks = <&sys_32k_ck>;
1261                 #clock-cells = <0>;
1262                 reg = <0x13b0>;
1263                 ti,bit-shift = <8>;
1264         };
1265
1266         optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1267                 compatible = "ti,gate-clock";
1268                 clocks = <&sys_32k_ck>;
1269                 #clock-cells = <0>;
1270                 reg = <0x13b8>;
1271                 ti,bit-shift = <8>;
1272         };
1273
1274         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1275                 compatible = "ti,divider-clock";
1276                 clocks = <&apll_pcie_ck>;
1277                 #clock-cells = <0>;
1278                 reg = <0x021c>;
1279                 ti,dividers = <2>, <1>;
1280                 ti,bit-shift = <8>;
1281                 ti,max-div = <2>;
1282         };
1283
1284         optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1285                 compatible = "ti,gate-clock";
1286                 clocks = <&apll_pcie_ck>;
1287                 #clock-cells = <0>;
1288                 reg = <0x13b0>;
1289                 ti,bit-shift = <9>;
1290         };
1291
1292         optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1293                 compatible = "ti,gate-clock";
1294                 clocks = <&apll_pcie_ck>;
1295                 #clock-cells = <0>;
1296                 reg = <0x13b8>;
1297                 ti,bit-shift = <9>;
1298         };
1299
1300         optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1301                 compatible = "ti,gate-clock";
1302                 clocks = <&optfclk_pciephy_div>;
1303                 #clock-cells = <0>;
1304                 reg = <0x13b0>;
1305                 ti,bit-shift = <10>;
1306         };
1307
1308         optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1309                 compatible = "ti,gate-clock";
1310                 clocks = <&optfclk_pciephy_div>;
1311                 #clock-cells = <0>;
1312                 reg = <0x13b8>;
1313                 ti,bit-shift = <10>;
1314         };
1315
1316         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1317                 #clock-cells = <0>;
1318                 compatible = "fixed-factor-clock";
1319                 clocks = <&apll_pcie_ck>;
1320                 clock-mult = <1>;
1321                 clock-div = <1>;
1322         };
1323
1324         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1325                 #clock-cells = <0>;
1326                 compatible = "fixed-factor-clock";
1327                 clocks = <&apll_pcie_ck>;
1328                 clock-mult = <1>;
1329                 clock-div = <1>;
1330         };
1331
1332         apll_pcie_m2_ck: apll_pcie_m2_ck {
1333                 #clock-cells = <0>;
1334                 compatible = "fixed-factor-clock";
1335                 clocks = <&apll_pcie_ck>;
1336                 clock-mult = <1>;
1337                 clock-div = <1>;
1338         };
1339
1340         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1341                 #clock-cells = <0>;
1342                 compatible = "ti,mux-clock";
1343                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1344                 ti,bit-shift = <23>;
1345                 reg = <0x014c>;
1346         };
1347
1348         dpll_per_ck: dpll_per_ck@140 {
1349                 #clock-cells = <0>;
1350                 compatible = "ti,omap4-dpll-clock";
1351                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1352                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1353         };
1354
1355         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1356                 #clock-cells = <0>;
1357                 compatible = "ti,divider-clock";
1358                 clocks = <&dpll_per_ck>;
1359                 ti,max-div = <31>;
1360                 ti,autoidle-shift = <8>;
1361                 reg = <0x0150>;
1362                 ti,index-starts-at-one;
1363                 ti,invert-autoidle-bit;
1364         };
1365
1366         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1367                 #clock-cells = <0>;
1368                 compatible = "fixed-factor-clock";
1369                 clocks = <&dpll_per_m2_ck>;
1370                 clock-mult = <1>;
1371                 clock-div = <1>;
1372         };
1373
1374         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1375                 #clock-cells = <0>;
1376                 compatible = "ti,mux-clock";
1377                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1378                 ti,bit-shift = <23>;
1379                 reg = <0x018c>;
1380         };
1381
1382         dpll_usb_ck: dpll_usb_ck@180 {
1383                 #clock-cells = <0>;
1384                 compatible = "ti,omap4-dpll-j-type-clock";
1385                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1386                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1387         };
1388
1389         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1390                 #clock-cells = <0>;
1391                 compatible = "ti,divider-clock";
1392                 clocks = <&dpll_usb_ck>;
1393                 ti,max-div = <127>;
1394                 ti,autoidle-shift = <8>;
1395                 reg = <0x0190>;
1396                 ti,index-starts-at-one;
1397                 ti,invert-autoidle-bit;
1398         };
1399
1400         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1401                 #clock-cells = <0>;
1402                 compatible = "ti,divider-clock";
1403                 clocks = <&dpll_pcie_ref_ck>;
1404                 ti,max-div = <127>;
1405                 ti,autoidle-shift = <8>;
1406                 reg = <0x0210>;
1407                 ti,index-starts-at-one;
1408                 ti,invert-autoidle-bit;
1409         };
1410
1411         dpll_per_x2_ck: dpll_per_x2_ck {
1412                 #clock-cells = <0>;
1413                 compatible = "ti,omap4-dpll-x2-clock";
1414                 clocks = <&dpll_per_ck>;
1415         };
1416
1417         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1418                 #clock-cells = <0>;
1419                 compatible = "ti,divider-clock";
1420                 clocks = <&dpll_per_x2_ck>;
1421                 ti,max-div = <63>;
1422                 ti,autoidle-shift = <8>;
1423                 reg = <0x0158>;
1424                 ti,index-starts-at-one;
1425                 ti,invert-autoidle-bit;
1426         };
1427
1428         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1429                 #clock-cells = <0>;
1430                 compatible = "ti,divider-clock";
1431                 clocks = <&dpll_per_x2_ck>;
1432                 ti,max-div = <63>;
1433                 ti,autoidle-shift = <8>;
1434                 reg = <0x015c>;
1435                 ti,index-starts-at-one;
1436                 ti,invert-autoidle-bit;
1437         };
1438
1439         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1440                 #clock-cells = <0>;
1441                 compatible = "ti,divider-clock";
1442                 clocks = <&dpll_per_x2_ck>;
1443                 ti,max-div = <63>;
1444                 ti,autoidle-shift = <8>;
1445                 reg = <0x0160>;
1446                 ti,index-starts-at-one;
1447                 ti,invert-autoidle-bit;
1448         };
1449
1450         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1451                 #clock-cells = <0>;
1452                 compatible = "ti,divider-clock";
1453                 clocks = <&dpll_per_x2_ck>;
1454                 ti,max-div = <63>;
1455                 ti,autoidle-shift = <8>;
1456                 reg = <0x0164>;
1457                 ti,index-starts-at-one;
1458                 ti,invert-autoidle-bit;
1459         };
1460
1461         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1462                 #clock-cells = <0>;
1463                 compatible = "ti,divider-clock";
1464                 clocks = <&dpll_per_x2_ck>;
1465                 ti,max-div = <31>;
1466                 ti,autoidle-shift = <8>;
1467                 reg = <0x0150>;
1468                 ti,index-starts-at-one;
1469                 ti,invert-autoidle-bit;
1470         };
1471
1472         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1473                 #clock-cells = <0>;
1474                 compatible = "fixed-factor-clock";
1475                 clocks = <&dpll_usb_ck>;
1476                 clock-mult = <1>;
1477                 clock-div = <1>;
1478         };
1479
1480         func_128m_clk: func_128m_clk {
1481                 #clock-cells = <0>;
1482                 compatible = "fixed-factor-clock";
1483                 clocks = <&dpll_per_h11x2_ck>;
1484                 clock-mult = <1>;
1485                 clock-div = <2>;
1486         };
1487
1488         func_12m_fclk: func_12m_fclk {
1489                 #clock-cells = <0>;
1490                 compatible = "fixed-factor-clock";
1491                 clocks = <&dpll_per_m2x2_ck>;
1492                 clock-mult = <1>;
1493                 clock-div = <16>;
1494         };
1495
1496         func_24m_clk: func_24m_clk {
1497                 #clock-cells = <0>;
1498                 compatible = "fixed-factor-clock";
1499                 clocks = <&dpll_per_m2_ck>;
1500                 clock-mult = <1>;
1501                 clock-div = <4>;
1502         };
1503
1504         func_48m_fclk: func_48m_fclk {
1505                 #clock-cells = <0>;
1506                 compatible = "fixed-factor-clock";
1507                 clocks = <&dpll_per_m2x2_ck>;
1508                 clock-mult = <1>;
1509                 clock-div = <4>;
1510         };
1511
1512         func_96m_fclk: func_96m_fclk {
1513                 #clock-cells = <0>;
1514                 compatible = "fixed-factor-clock";
1515                 clocks = <&dpll_per_m2x2_ck>;
1516                 clock-mult = <1>;
1517                 clock-div = <2>;
1518         };
1519
1520         l3init_60m_fclk: l3init_60m_fclk@104 {
1521                 #clock-cells = <0>;
1522                 compatible = "ti,divider-clock";
1523                 clocks = <&dpll_usb_m2_ck>;
1524                 reg = <0x0104>;
1525                 ti,dividers = <1>, <8>;
1526         };
1527
1528         clkout2_clk: clkout2_clk@6b0 {
1529                 #clock-cells = <0>;
1530                 compatible = "ti,gate-clock";
1531                 clocks = <&clkoutmux2_clk_mux>;
1532                 ti,bit-shift = <8>;
1533                 reg = <0x06b0>;
1534         };
1535
1536         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1537                 #clock-cells = <0>;
1538                 compatible = "ti,gate-clock";
1539                 clocks = <&dpll_usb_clkdcoldo>;
1540                 ti,bit-shift = <8>;
1541                 reg = <0x06c0>;
1542         };
1543
1544         dss_32khz_clk: dss_32khz_clk@1120 {
1545                 #clock-cells = <0>;
1546                 compatible = "ti,gate-clock";
1547                 clocks = <&sys_32k_ck>;
1548                 ti,bit-shift = <11>;
1549                 reg = <0x1120>;
1550         };
1551
1552         dss_48mhz_clk: dss_48mhz_clk@1120 {
1553                 #clock-cells = <0>;
1554                 compatible = "ti,gate-clock";
1555                 clocks = <&func_48m_fclk>;
1556                 ti,bit-shift = <9>;
1557                 reg = <0x1120>;
1558         };
1559
1560         dss_dss_clk: dss_dss_clk@1120 {
1561                 #clock-cells = <0>;
1562                 compatible = "ti,gate-clock";
1563                 clocks = <&dpll_per_h12x2_ck>;
1564                 ti,bit-shift = <8>;
1565                 reg = <0x1120>;
1566                 ti,set-rate-parent;
1567         };
1568
1569         dss_hdmi_clk: dss_hdmi_clk@1120 {
1570                 #clock-cells = <0>;
1571                 compatible = "ti,gate-clock";
1572                 clocks = <&hdmi_dpll_clk_mux>;
1573                 ti,bit-shift = <10>;
1574                 reg = <0x1120>;
1575         };
1576
1577         dss_video1_clk: dss_video1_clk@1120 {
1578                 #clock-cells = <0>;
1579                 compatible = "ti,gate-clock";
1580                 clocks = <&video1_dpll_clk_mux>;
1581                 ti,bit-shift = <12>;
1582                 reg = <0x1120>;
1583         };
1584
1585         dss_video2_clk: dss_video2_clk@1120 {
1586                 #clock-cells = <0>;
1587                 compatible = "ti,gate-clock";
1588                 clocks = <&video2_dpll_clk_mux>;
1589                 ti,bit-shift = <13>;
1590                 reg = <0x1120>;
1591         };
1592
1593         gpio2_dbclk: gpio2_dbclk@1760 {
1594                 #clock-cells = <0>;
1595                 compatible = "ti,gate-clock";
1596                 clocks = <&sys_32k_ck>;
1597                 ti,bit-shift = <8>;
1598                 reg = <0x1760>;
1599         };
1600
1601         gpio3_dbclk: gpio3_dbclk@1768 {
1602                 #clock-cells = <0>;
1603                 compatible = "ti,gate-clock";
1604                 clocks = <&sys_32k_ck>;
1605                 ti,bit-shift = <8>;
1606                 reg = <0x1768>;
1607         };
1608
1609         gpio4_dbclk: gpio4_dbclk@1770 {
1610                 #clock-cells = <0>;
1611                 compatible = "ti,gate-clock";
1612                 clocks = <&sys_32k_ck>;
1613                 ti,bit-shift = <8>;
1614                 reg = <0x1770>;
1615         };
1616
1617         gpio5_dbclk: gpio5_dbclk@1778 {
1618                 #clock-cells = <0>;
1619                 compatible = "ti,gate-clock";
1620                 clocks = <&sys_32k_ck>;
1621                 ti,bit-shift = <8>;
1622                 reg = <0x1778>;
1623         };
1624
1625         gpio6_dbclk: gpio6_dbclk@1780 {
1626                 #clock-cells = <0>;
1627                 compatible = "ti,gate-clock";
1628                 clocks = <&sys_32k_ck>;
1629                 ti,bit-shift = <8>;
1630                 reg = <0x1780>;
1631         };
1632
1633         gpio7_dbclk: gpio7_dbclk@1810 {
1634                 #clock-cells = <0>;
1635                 compatible = "ti,gate-clock";
1636                 clocks = <&sys_32k_ck>;
1637                 ti,bit-shift = <8>;
1638                 reg = <0x1810>;
1639         };
1640
1641         gpio8_dbclk: gpio8_dbclk@1818 {
1642                 #clock-cells = <0>;
1643                 compatible = "ti,gate-clock";
1644                 clocks = <&sys_32k_ck>;
1645                 ti,bit-shift = <8>;
1646                 reg = <0x1818>;
1647         };
1648
1649         mmc1_clk32k: mmc1_clk32k@1328 {
1650                 #clock-cells = <0>;
1651                 compatible = "ti,gate-clock";
1652                 clocks = <&sys_32k_ck>;
1653                 ti,bit-shift = <8>;
1654                 reg = <0x1328>;
1655         };
1656
1657         mmc2_clk32k: mmc2_clk32k@1330 {
1658                 #clock-cells = <0>;
1659                 compatible = "ti,gate-clock";
1660                 clocks = <&sys_32k_ck>;
1661                 ti,bit-shift = <8>;
1662                 reg = <0x1330>;
1663         };
1664
1665         mmc3_clk32k: mmc3_clk32k@1820 {
1666                 #clock-cells = <0>;
1667                 compatible = "ti,gate-clock";
1668                 clocks = <&sys_32k_ck>;
1669                 ti,bit-shift = <8>;
1670                 reg = <0x1820>;
1671         };
1672
1673         mmc4_clk32k: mmc4_clk32k@1828 {
1674                 #clock-cells = <0>;
1675                 compatible = "ti,gate-clock";
1676                 clocks = <&sys_32k_ck>;
1677                 ti,bit-shift = <8>;
1678                 reg = <0x1828>;
1679         };
1680
1681         sata_ref_clk: sata_ref_clk@1388 {
1682                 #clock-cells = <0>;
1683                 compatible = "ti,gate-clock";
1684                 clocks = <&sys_clkin1>;
1685                 ti,bit-shift = <8>;
1686                 reg = <0x1388>;
1687         };
1688
1689         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1690                 #clock-cells = <0>;
1691                 compatible = "ti,gate-clock";
1692                 clocks = <&l3init_960m_gfclk>;
1693                 ti,bit-shift = <8>;
1694                 reg = <0x13f0>;
1695         };
1696
1697         usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1698                 #clock-cells = <0>;
1699                 compatible = "ti,gate-clock";
1700                 clocks = <&l3init_960m_gfclk>;
1701                 ti,bit-shift = <8>;
1702                 reg = <0x1340>;
1703         };
1704
1705         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1706                 #clock-cells = <0>;
1707                 compatible = "ti,gate-clock";
1708                 clocks = <&sys_32k_ck>;
1709                 ti,bit-shift = <8>;
1710                 reg = <0x0640>;
1711         };
1712
1713         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1714                 #clock-cells = <0>;
1715                 compatible = "ti,gate-clock";
1716                 clocks = <&sys_32k_ck>;
1717                 ti,bit-shift = <8>;
1718                 reg = <0x0688>;
1719         };
1720
1721         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1722                 #clock-cells = <0>;
1723                 compatible = "ti,gate-clock";
1724                 clocks = <&sys_32k_ck>;
1725                 ti,bit-shift = <8>;
1726                 reg = <0x0698>;
1727         };
1728
1729         atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1730                 #clock-cells = <0>;
1731                 compatible = "ti,mux-clock";
1732                 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1733                 ti,bit-shift = <24>;
1734                 reg = <0x0c00>;
1735         };
1736
1737         atl_gfclk_mux: atl_gfclk_mux@c00 {
1738                 #clock-cells = <0>;
1739                 compatible = "ti,mux-clock";
1740                 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1741                 ti,bit-shift = <26>;
1742                 reg = <0x0c00>;
1743         };
1744
1745         rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
1746                 #clock-cells = <0>;
1747                 compatible = "ti,mux-clock";
1748                 clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
1749                 ti,bit-shift = <24>;
1750                 reg = <0x13d0>;
1751         };
1752
1753         gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1754                 #clock-cells = <0>;
1755                 compatible = "ti,mux-clock";
1756                 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1757                 ti,bit-shift = <25>;
1758                 reg = <0x13d0>;
1759         };
1760
1761         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1762                 #clock-cells = <0>;
1763                 compatible = "ti,mux-clock";
1764                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1765                 ti,bit-shift = <24>;
1766                 reg = <0x1220>;
1767                 assigned-clocks = <&gpu_core_gclk_mux>;
1768                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1769         };
1770
1771         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1772                 #clock-cells = <0>;
1773                 compatible = "ti,mux-clock";
1774                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1775                 ti,bit-shift = <26>;
1776                 reg = <0x1220>;
1777                 assigned-clocks = <&gpu_hyd_gclk_mux>;
1778                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1779         };
1780
1781         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1782                 #clock-cells = <0>;
1783                 compatible = "ti,divider-clock";
1784                 clocks = <&wkupaon_iclk_mux>;
1785                 ti,bit-shift = <24>;
1786                 reg = <0x0e50>;
1787                 ti,dividers = <8>, <16>, <32>;
1788         };
1789
1790         mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1791                 #clock-cells = <0>;
1792                 compatible = "ti,mux-clock";
1793                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1794                 ti,bit-shift = <28>;
1795                 reg = <0x1860>;
1796         };
1797
1798         mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1799                 #clock-cells = <0>;
1800                 compatible = "ti,mux-clock";
1801                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1802                 ti,bit-shift = <24>;
1803                 reg = <0x1860>;
1804         };
1805
1806         mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1807                 #clock-cells = <0>;
1808                 compatible = "ti,mux-clock";
1809                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1810                 ti,bit-shift = <22>;
1811                 reg = <0x1860>;
1812         };
1813
1814         mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1815                 #clock-cells = <0>;
1816                 compatible = "ti,mux-clock";
1817                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1818                 ti,bit-shift = <24>;
1819                 reg = <0x1868>;
1820         };
1821
1822         mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1823                 #clock-cells = <0>;
1824                 compatible = "ti,mux-clock";
1825                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1826                 ti,bit-shift = <22>;
1827                 reg = <0x1868>;
1828         };
1829
1830         mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1831                 #clock-cells = <0>;
1832                 compatible = "ti,mux-clock";
1833                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1834                 ti,bit-shift = <24>;
1835                 reg = <0x1898>;
1836         };
1837
1838         mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1839                 #clock-cells = <0>;
1840                 compatible = "ti,mux-clock";
1841                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1842                 ti,bit-shift = <22>;
1843                 reg = <0x1898>;
1844         };
1845
1846         mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1847                 #clock-cells = <0>;
1848                 compatible = "ti,mux-clock";
1849                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1850                 ti,bit-shift = <24>;
1851                 reg = <0x1878>;
1852         };
1853
1854         mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1855                 #clock-cells = <0>;
1856                 compatible = "ti,mux-clock";
1857                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1858                 ti,bit-shift = <22>;
1859                 reg = <0x1878>;
1860         };
1861
1862         mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1863                 #clock-cells = <0>;
1864                 compatible = "ti,mux-clock";
1865                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1866                 ti,bit-shift = <24>;
1867                 reg = <0x1904>;
1868         };
1869
1870         mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1871                 #clock-cells = <0>;
1872                 compatible = "ti,mux-clock";
1873                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1874                 ti,bit-shift = <22>;
1875                 reg = <0x1904>;
1876         };
1877
1878         mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1879                 #clock-cells = <0>;
1880                 compatible = "ti,mux-clock";
1881                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1882                 ti,bit-shift = <24>;
1883                 reg = <0x1908>;
1884         };
1885
1886         mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1887                 #clock-cells = <0>;
1888                 compatible = "ti,mux-clock";
1889                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1890                 ti,bit-shift = <22>;
1891                 reg = <0x1908>;
1892         };
1893
1894         mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1895                 #clock-cells = <0>;
1896                 compatible = "ti,mux-clock";
1897                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1898                 ti,bit-shift = <22>;
1899                 reg = <0x1890>;
1900         };
1901
1902         mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1903                 #clock-cells = <0>;
1904                 compatible = "ti,mux-clock";
1905                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1906                 ti,bit-shift = <24>;
1907                 reg = <0x1890>;
1908         };
1909
1910         mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1911                 #clock-cells = <0>;
1912                 compatible = "ti,mux-clock";
1913                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1914                 ti,bit-shift = <24>;
1915                 reg = <0x1328>;
1916         };
1917
1918         mmc1_fclk_div: mmc1_fclk_div@1328 {
1919                 #clock-cells = <0>;
1920                 compatible = "ti,divider-clock";
1921                 clocks = <&mmc1_fclk_mux>;
1922                 ti,bit-shift = <25>;
1923                 ti,max-div = <4>;
1924                 reg = <0x1328>;
1925                 ti,index-power-of-two;
1926         };
1927
1928         mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1929                 #clock-cells = <0>;
1930                 compatible = "ti,mux-clock";
1931                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1932                 ti,bit-shift = <24>;
1933                 reg = <0x1330>;
1934         };
1935
1936         mmc2_fclk_div: mmc2_fclk_div@1330 {
1937                 #clock-cells = <0>;
1938                 compatible = "ti,divider-clock";
1939                 clocks = <&mmc2_fclk_mux>;
1940                 ti,bit-shift = <25>;
1941                 ti,max-div = <4>;
1942                 reg = <0x1330>;
1943                 ti,index-power-of-two;
1944         };
1945
1946         mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1947                 #clock-cells = <0>;
1948                 compatible = "ti,mux-clock";
1949                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1950                 ti,bit-shift = <24>;
1951                 reg = <0x1820>;
1952         };
1953
1954         mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1955                 #clock-cells = <0>;
1956                 compatible = "ti,divider-clock";
1957                 clocks = <&mmc3_gfclk_mux>;
1958                 ti,bit-shift = <25>;
1959                 ti,max-div = <4>;
1960                 reg = <0x1820>;
1961                 ti,index-power-of-two;
1962         };
1963
1964         mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1965                 #clock-cells = <0>;
1966                 compatible = "ti,mux-clock";
1967                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1968                 ti,bit-shift = <24>;
1969                 reg = <0x1828>;
1970         };
1971
1972         mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1973                 #clock-cells = <0>;
1974                 compatible = "ti,divider-clock";
1975                 clocks = <&mmc4_gfclk_mux>;
1976                 ti,bit-shift = <25>;
1977                 ti,max-div = <4>;
1978                 reg = <0x1828>;
1979                 ti,index-power-of-two;
1980         };
1981
1982         qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1983                 #clock-cells = <0>;
1984                 compatible = "ti,mux-clock";
1985                 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1986                 ti,bit-shift = <24>;
1987                 reg = <0x1838>;
1988         };
1989
1990         qspi_gfclk_div: qspi_gfclk_div@1838 {
1991                 #clock-cells = <0>;
1992                 compatible = "ti,divider-clock";
1993                 clocks = <&qspi_gfclk_mux>;
1994                 ti,bit-shift = <25>;
1995                 ti,max-div = <4>;
1996                 reg = <0x1838>;
1997                 ti,index-power-of-two;
1998         };
1999
2000         timer10_gfclk_mux: timer10_gfclk_mux@1728 {
2001                 #clock-cells = <0>;
2002                 compatible = "ti,mux-clock";
2003                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2004                 ti,bit-shift = <24>;
2005                 reg = <0x1728>;
2006         };
2007
2008         timer11_gfclk_mux: timer11_gfclk_mux@1730 {
2009                 #clock-cells = <0>;
2010                 compatible = "ti,mux-clock";
2011                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2012                 ti,bit-shift = <24>;
2013                 reg = <0x1730>;
2014         };
2015
2016         timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
2017                 #clock-cells = <0>;
2018                 compatible = "ti,mux-clock";
2019                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2020                 ti,bit-shift = <24>;
2021                 reg = <0x17c8>;
2022         };
2023
2024         timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
2025                 #clock-cells = <0>;
2026                 compatible = "ti,mux-clock";
2027                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2028                 ti,bit-shift = <24>;
2029                 reg = <0x17d0>;
2030         };
2031
2032         timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2033                 #clock-cells = <0>;
2034                 compatible = "ti,mux-clock";
2035                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2036                 ti,bit-shift = <24>;
2037                 reg = <0x17d8>;
2038         };
2039
2040         timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2041                 #clock-cells = <0>;
2042                 compatible = "ti,mux-clock";
2043                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2044                 ti,bit-shift = <24>;
2045                 reg = <0x1830>;
2046         };
2047
2048         timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2049                 #clock-cells = <0>;
2050                 compatible = "ti,mux-clock";
2051                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2052                 ti,bit-shift = <24>;
2053                 reg = <0x1738>;
2054         };
2055
2056         timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2057                 #clock-cells = <0>;
2058                 compatible = "ti,mux-clock";
2059                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2060                 ti,bit-shift = <24>;
2061                 reg = <0x1740>;
2062         };
2063
2064         timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2065                 #clock-cells = <0>;
2066                 compatible = "ti,mux-clock";
2067                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2068                 ti,bit-shift = <24>;
2069                 reg = <0x1748>;
2070         };
2071
2072         timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2073                 #clock-cells = <0>;
2074                 compatible = "ti,mux-clock";
2075                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2076                 ti,bit-shift = <24>;
2077                 reg = <0x1750>;
2078         };
2079
2080         uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2081                 #clock-cells = <0>;
2082                 compatible = "ti,mux-clock";
2083                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2084                 ti,bit-shift = <24>;
2085                 reg = <0x1840>;
2086         };
2087
2088         uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2089                 #clock-cells = <0>;
2090                 compatible = "ti,mux-clock";
2091                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2092                 ti,bit-shift = <24>;
2093                 reg = <0x1848>;
2094         };
2095
2096         uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2097                 #clock-cells = <0>;
2098                 compatible = "ti,mux-clock";
2099                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2100                 ti,bit-shift = <24>;
2101                 reg = <0x1850>;
2102         };
2103
2104         uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2105                 #clock-cells = <0>;
2106                 compatible = "ti,mux-clock";
2107                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2108                 ti,bit-shift = <24>;
2109                 reg = <0x1858>;
2110         };
2111
2112         uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2113                 #clock-cells = <0>;
2114                 compatible = "ti,mux-clock";
2115                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2116                 ti,bit-shift = <24>;
2117                 reg = <0x1870>;
2118         };
2119
2120         uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2121                 #clock-cells = <0>;
2122                 compatible = "ti,mux-clock";
2123                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2124                 ti,bit-shift = <24>;
2125                 reg = <0x18d0>;
2126         };
2127
2128         uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2129                 #clock-cells = <0>;
2130                 compatible = "ti,mux-clock";
2131                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2132                 ti,bit-shift = <24>;
2133                 reg = <0x18e0>;
2134         };
2135
2136         uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2137                 #clock-cells = <0>;
2138                 compatible = "ti,mux-clock";
2139                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2140                 ti,bit-shift = <24>;
2141                 reg = <0x18e8>;
2142         };
2143
2144         vip1_gclk_mux: vip1_gclk_mux@1020 {
2145                 #clock-cells = <0>;
2146                 compatible = "ti,mux-clock";
2147                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2148                 ti,bit-shift = <24>;
2149                 reg = <0x1020>;
2150         };
2151
2152         vip2_gclk_mux: vip2_gclk_mux@1028 {
2153                 #clock-cells = <0>;
2154                 compatible = "ti,mux-clock";
2155                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2156                 ti,bit-shift = <24>;
2157                 reg = <0x1028>;
2158         };
2159
2160         vip3_gclk_mux: vip3_gclk_mux@1030 {
2161                 #clock-cells = <0>;
2162                 compatible = "ti,mux-clock";
2163                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2164                 ti,bit-shift = <24>;
2165                 reg = <0x1030>;
2166         };
2167 };
2168
2169 &cm_core_clockdomains {
2170         coreaon_clkdm: coreaon_clkdm {
2171                 compatible = "ti,clockdomain";
2172                 clocks = <&dpll_usb_ck>;
2173         };
2174 };
2175
2176 &scm_conf_clocks {
2177         dss_deshdcp_clk: dss_deshdcp_clk@558 {
2178                 #clock-cells = <0>;
2179                 compatible = "ti,gate-clock";
2180                 clocks = <&l3_iclk_div>;
2181                 ti,bit-shift = <0>;
2182                 reg = <0x558>;
2183         };
2184
2185        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2186                 #clock-cells = <0>;
2187                 compatible = "ti,gate-clock";
2188                 clocks = <&l4_root_clk_div>;
2189                 ti,bit-shift = <20>;
2190                 reg = <0x0558>;
2191         };
2192
2193         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2194                 #clock-cells = <0>;
2195                 compatible = "ti,gate-clock";
2196                 clocks = <&l4_root_clk_div>;
2197                 ti,bit-shift = <21>;
2198                 reg = <0x0558>;
2199         };
2200
2201         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2202                 #clock-cells = <0>;
2203                 compatible = "ti,gate-clock";
2204                 clocks = <&l4_root_clk_div>;
2205                 ti,bit-shift = <22>;
2206                 reg = <0x0558>;
2207         };
2208
2209         sys_32k_ck: sys_32k_ck {
2210                 #clock-cells = <0>;
2211                 compatible = "ti,mux-clock";
2212                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
2213                 ti,bit-shift = <8>;
2214                 reg = <0x6c4>;
2215         };
2216 };