arch/arm/dts/imx6qdl-icore-rqs.dtsi

   1 /*
   2  * Copyright (C) 2015 Amarula Solutions B.V.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/clock/imx6qdl-clock.h>
  44
  45 / {
  46         memory {
  47                 reg = <0x10000000 0x80000000>;
  48         };
  49 };
  50
  51 &fec {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_enet>;
  54         phy-handle = <&eth_phy>;
  55         phy-mode = "rgmii";
  56         status = "okay";
  57
  58         mdio {
  59                 eth_phy: ethernet-phy {
  60                         rxc-skew-ps = <1140>;
  61                         txc-skew-ps = <1140>;
  62                         txen-skew-ps = <600>;
  63                         rxdv-skew-ps = <240>;
  64                         rxd0-skew-ps = <420>;
  65                         rxd1-skew-ps = <600>;
  66                         rxd2-skew-ps = <420>;
  67                         rxd3-skew-ps = <240>;
  68                         txd0-skew-ps = <60>;
  69                         txd1-skew-ps = <60>;
  70                         txd2-skew-ps = <60>;
  71                         txd3-skew-ps = <240>;
  72                 };
  73         };
  74 };
  75
  76 &i2c1 {
  77         clock-frequency = <100000>;
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_i2c1>;
  80         status = "okay";
  81 };
  82
  83 &i2c2 {
  84         clock-frequency = <100000>;
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_i2c2>;
  87         status = "okay";
  88 };
  89
  90 &i2c3 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_i2c3>;
  93         status = "okay";
  94 };
  95
  96 &uart4 {
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&pinctrl_uart4>;
  99         status = "okay";
 100 };
 101
 102 &usdhc3 {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_usdhc3>;
 105         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 106         no-1-8-v;
 107         status = "okay";
 108 };
 109
 110 &iomuxc {
 111         pinctrl_enet: enetgrp {
 112                 fsl,pins = <
 113                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 114                         MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 115                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
 116                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
 117                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
 118                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
 119                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
 120                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 121                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 122                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
 123                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
 124                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
 125                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
 126                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
 127                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 128                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 129                 >;
 130         };
 131
 132         pinctrl_i2c1: i2c1grp {
 133                 fsl,pins = <
 134                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 135                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 136                 >;
 137         };
 138
 139         pinctrl_i2c2: i2c2grp {
 140                 fsl,pins = <
 141                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 142                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 143                 >;
 144         };
 145
 146         pinctrl_i2c3: i2c3grp {
 147                 fsl,pins = <
 148                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 149                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 150                 >;
 151         };
 152
 153         pinctrl_uart4: uart4grp {
 154                 fsl,pins = <
 155                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 156                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 157                 >;
 158         };
 159
 160         pinctrl_usdhc3: usdhc3grp {
 161                 fsl,pins = <
 162                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 163                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
 164                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
 165                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
 166                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
 167                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
 168                 >;
 169         };
 170 };