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[people/ms/u-boot.git] / arch / arm / dts / imx6ull.dtsi
1 /*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6ull-pinfunc.h"
13 #include "imx6ull-pinfunc-snvs.h"
14 #include "skeleton.dtsi"
15
16 / {
17 aliases {
18 can0 = &flexcan1;
19 can1 = &flexcan2;
20 ethernet0 = &fec1;
21 ethernet1 = &fec2;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 i2c0 = &i2c1;
28 i2c1 = &i2c2;
29 i2c2 = &i2c3;
30 i2c3 = &i2c4;
31 mmc0 = &usdhc1;
32 mmc1 = &usdhc2;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 serial5 = &uart6;
39 serial6 = &uart7;
40 serial7 = &uart8;
41 spi0 = &qspi;
42 spi1 = &ecspi1;
43 spi2 = &ecspi2;
44 spi3 = &ecspi3;
45 spi4 = &ecspi4;
46 usbphy0 = &usbphy1;
47 usbphy1 = &usbphy2;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 compatible = "arm,cortex-a7";
56 device_type = "cpu";
57 reg = <0>;
58 clock-latency = <61036>; /* two CLK32 periods */
59 operating-points = <
60 /* kHz uV */
61 528000 1175000
62 99000 950000
63 >;
64 fsl,soc-operating-points = <
65 /* KHz uV */
66 528000 1175000
67 99000 1175000
68 >;
69 clocks = <&clks IMX6UL_CLK_ARM>,
70 <&clks IMX6UL_CLK_PLL2_BUS>,
71 <&clks IMX6UL_CLK_PLL2_PFD2>,
72 <&clks IMX6UL_CA7_SECONDARY_SEL>,
73 <&clks IMX6UL_CLK_STEP>,
74 <&clks IMX6UL_CLK_PLL1_SW>,
75 <&clks IMX6UL_CLK_PLL1_SYS>,
76 <&clks IMX6UL_PLL1_BYPASS>,
77 <&clks IMX6UL_CLK_PLL1>,
78 <&clks IMX6UL_PLL1_BYPASS_SRC>,
79 <&clks IMX6UL_CLK_OSC>;
80 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step",
81 "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
82 };
83 };
84
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a7-gic";
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 reg = <0x00a01000 0x1000>,
90 <0x00a02000 0x100>;
91 };
92
93 clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 ckil: clock@0 {
98 compatible = "fixed-clock";
99 reg = <0>;
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 #clock-cells = <0>;
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
111 };
112
113 ipp_di0: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
119 };
120
121 ipp_di1: clock@3 {
122 compatible = "fixed-clock";
123 reg = <3>;
124 #clock-cells = <0>;
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
127 };
128 };
129
130 soc {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&gpc>;
135 ranges;
136
137 busfreq {
138 compatible = "fsl,imx_busfreq";
139 clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
140 <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
141 <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
142 <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
143 <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
144 <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
145 <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
146 <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
147 <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
148 <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
149 <&clks IMX6UL_CLK_PLL1>;
150 clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
151 "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
152 "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
153 "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
154 fsl,max_ddr_freq = <400000000>;
155 };
156
157 pmu {
158 compatible = "arm,cortex-a7-pmu";
159 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
160 status = "disabled";
161 };
162
163 ocrams: sram@00900000 {
164 compatible = "fsl,lpm-sram";
165 reg = <0x00900000 0x4000>;
166 };
167
168 ocrams_ddr: sram@00904000 {
169 compatible = "fsl,ddr-lpm-sram";
170 reg = <0x00904000 0x1000>;
171 };
172
173 ocram: sram@00905000 {
174 compatible = "mmio-sram";
175 reg = <0x00905000 0x1B000>;
176 };
177
178 dma_apbh: dma-apbh@01804000 {
179 compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
180 reg = <0x01804000 0x2000>;
181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
186 #dma-cells = <1>;
187 dma-channels = <4>;
188 clocks = <&clks IMX6UL_CLK_APBHDMA>;
189 };
190
191 gpmi: gpmi-nand@01806000{
192 compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
196 reg-names = "gpmi-nand", "bch";
197 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-names = "bch";
199 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
200 <&clks IMX6UL_CLK_GPMI_APB>,
201 <&clks IMX6UL_CLK_GPMI_BCH>,
202 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
203 <&clks IMX6UL_CLK_PER_BCH>;
204 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
205 "gpmi_bch_apb", "per1_bch";
206 dmas = <&dma_apbh 0>;
207 dma-names = "rx-tx";
208 status = "disabled";
209 };
210
211 aips1: aips-bus@02000000 {
212 compatible = "fsl,aips-bus", "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 reg = <0x02000000 0x100000>;
216 ranges;
217
218 spba-bus@02000000 {
219 compatible = "fsl,spba-bus", "simple-bus";
220 #address-cells = <1>;
221 #size-cells = <1>;
222 reg = <0x02000000 0x40000>;
223 ranges;
224
225 spdif: spdif@02004000 {
226 compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
227 reg = <0x02004000 0x4000>;
228 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
229 dmas = <&sdma 41 18 0>,
230 <&sdma 42 18 0>;
231 dma-names = "rx", "tx";
232 clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
233 <&clks IMX6UL_CLK_OSC>,
234 <&clks IMX6UL_CLK_SPDIF>,
235 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
236 <&clks IMX6UL_CLK_IPG>,
237 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
238 <&clks IMX6UL_CLK_SPBA>;
239 clock-names = "core", "rxtx0",
240 "rxtx1", "rxtx2",
241 "rxtx3", "rxtx4",
242 "rxtx5", "rxtx6",
243 "rxtx7", "dma";
244 status = "disabled";
245 };
246
247 ecspi1: ecspi@02008000 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
251 reg = <0x02008000 0x4000>;
252 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clks IMX6UL_CLK_ECSPI1>,
254 <&clks IMX6UL_CLK_ECSPI1>;
255 clock-names = "ipg", "per";
256 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
257 dma-names = "rx", "tx";
258 status = "disabled";
259 };
260
261 ecspi2: ecspi@0200c000 {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
265 reg = <0x0200c000 0x4000>;
266 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX6UL_CLK_ECSPI2>,
268 <&clks IMX6UL_CLK_ECSPI2>;
269 clock-names = "ipg", "per";
270 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
271 dma-names = "rx", "tx";
272 status = "disabled";
273 };
274
275 ecspi3: ecspi@02010000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
279 reg = <0x02010000 0x4000>;
280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6UL_CLK_ECSPI3>,
282 <&clks IMX6UL_CLK_ECSPI3>;
283 clock-names = "ipg", "per";
284 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
285 dma-names = "rx", "tx";
286 status = "disabled";
287 };
288
289 ecspi4: ecspi@02014000 {
290 #address-cells = <1>;
291 #size-cells = <0>;
292 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
293 reg = <0x02014000 0x4000>;
294 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6UL_CLK_ECSPI4>,
296 <&clks IMX6UL_CLK_ECSPI4>;
297 clock-names = "ipg", "per";
298 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
299 dma-names = "rx", "tx";
300 status = "disabled";
301 };
302
303 uart7: serial@02018000 {
304 compatible = "fsl,imx6ul-uart",
305 "fsl,imx6q-uart", "fsl,imx21-uart";
306 reg = <0x02018000 0x4000>;
307 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
309 <&clks IMX6UL_CLK_UART7_SERIAL>;
310 clock-names = "ipg", "per";
311 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
312 dma-names = "rx", "tx";
313 status = "disabled";
314 };
315
316 uart1: serial@02020000 {
317 compatible = "fsl,imx6ul-uart",
318 "fsl,imx6q-uart", "fsl,imx21-uart";
319 reg = <0x02020000 0x4000>;
320 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
322 <&clks IMX6UL_CLK_UART1_SERIAL>;
323 clock-names = "ipg", "per";
324 status = "disabled";
325 };
326
327 esai: esai@02024000 {
328 compatible = "fsl,imx6ull-esai";
329 reg = <0x02024000 0x4000>;
330 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6UL_CLK_ESAI_IPG>,
332 <&clks IMX6UL_CLK_ESAI_MEM>,
333 <&clks IMX6UL_CLK_ESAI_EXTAL>,
334 <&clks IMX6UL_CLK_ESAI_IPG>,
335 <&clks IMX6UL_CLK_SPBA>;
336 clock-names = "core", "mem", "extal",
337 "fsys", "dma";
338 dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
339 dma-names = "rx", "tx";
340 dma-source = <&gpr 0 14 0 15>;
341 status = "disabled";
342 };
343
344 sai1: sai@02028000 {
345 compatible = "fsl,imx6ul-sai",
346 "fsl,imx6sx-sai";
347 reg = <0x02028000 0x4000>;
348 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
350 <&clks IMX6UL_CLK_DUMMY>,
351 <&clks IMX6UL_CLK_SAI1>,
352 <&clks 0>, <&clks 0>;
353 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
355 dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
356 status = "disabled";
357 };
358
359 sai2: sai@0202c000 {
360 compatible = "fsl,imx6ul-sai",
361 "fsl,imx6sx-sai";
362 reg = <0x0202c000 0x4000>;
363 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
365 <&clks IMX6UL_CLK_DUMMY>,
366 <&clks IMX6UL_CLK_SAI2>,
367 <&clks 0>, <&clks 0>;
368 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
369 dma-names = "rx", "tx";
370 dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
371 status = "disabled";
372 };
373
374 sai3: sai@02030000 {
375 compatible = "fsl,imx6ul-sai",
376 "fsl,imx6sx-sai";
377 reg = <0x02030000 0x4000>;
378 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
380 <&clks IMX6UL_CLK_DUMMY>,
381 <&clks IMX6UL_CLK_SAI3>,
382 <&clks 0>, <&clks 0>;
383 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
384 dma-names = "rx", "tx";
385 dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
386 status = "disabled";
387 };
388
389 asrc: asrc@02034000 {
390 compatible = "fsl,imx53-asrc";
391 reg = <0x02034000 0x4000>;
392 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
394 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
395 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
398 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
399 <&clks IMX6UL_CLK_SPBA>;
400 clock-names = "mem", "ipg", "asrck_0",
401 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
402 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
403 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
404 "asrck_d", "asrck_e", "asrck_f", "dma";
405 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
406 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
407 dma-names = "rxa", "rxb", "rxc",
408 "txa", "txb", "txc";
409 fsl,asrc-rate = <48000>;
410 fsl,asrc-width = <16>;
411 status = "okay";
412 };
413 };
414
415 tsc: tsc@02040000 {
416 compatible = "fsl,imx6ul-tsc";
417 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
418 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6UL_CLK_IPG>,
421 <&clks IMX6UL_CLK_ADC2>;
422 clock-names = "tsc", "adc";
423 status = "disabled";
424 };
425
426 pwm1: pwm@02080000 {
427 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
428 reg = <0x02080000 0x4000>;
429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6UL_CLK_PWM1>,
431 <&clks IMX6UL_CLK_PWM1>;
432 clock-names = "ipg", "per";
433 #pwm-cells = <2>;
434 };
435
436 pwm2: pwm@02084000 {
437 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
438 reg = <0x02084000 0x4000>;
439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6UL_CLK_DUMMY>,
441 <&clks IMX6UL_CLK_DUMMY>;
442 clock-names = "ipg", "per";
443 #pwm-cells = <2>;
444 };
445
446 pwm3: pwm@02088000 {
447 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
448 reg = <0x02088000 0x4000>;
449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6UL_CLK_PWM3>,
451 <&clks IMX6UL_CLK_PWM3>;
452 clock-names = "ipg", "per";
453 #pwm-cells = <2>;
454 };
455
456 pwm4: pwm@0208c000 {
457 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
458 reg = <0x0208c000 0x4000>;
459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clks IMX6UL_CLK_DUMMY>,
461 <&clks IMX6UL_CLK_DUMMY>;
462 clock-names = "ipg", "per";
463 #pwm-cells = <2>;
464 };
465
466 flexcan1: can@02090000 {
467 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
468 reg = <0x02090000 0x4000>;
469 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
471 <&clks IMX6UL_CLK_CAN1_SERIAL>;
472 clock-names = "ipg", "per";
473 stop-mode = <&gpr 0x10 1 0x10 17>;
474 status = "disabled";
475 };
476
477 flexcan2: can@02094000 {
478 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
479 reg = <0x02094000 0x4000>;
480 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
482 <&clks IMX6UL_CLK_CAN2_SERIAL>;
483 clock-names = "ipg", "per";
484 stop-mode = <&gpr 0x10 2 0x10 18>;
485 status = "disabled";
486 };
487
488 gpt1: gpt@02098000 {
489 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
490 reg = <0x02098000 0x4000>;
491 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
493 <&clks IMX6UL_CLK_GPT1_SERIAL>;
494 clock-names = "ipg", "per";
495 };
496
497 gpio1: gpio@0209c000 {
498 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
499 reg = <0x0209c000 0x4000>;
500 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 };
507
508 gpio2: gpio@020a0000 {
509 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
510 reg = <0x020a0000 0x4000>;
511 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 };
518
519 gpio3: gpio@020a4000 {
520 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
521 reg = <0x020a4000 0x4000>;
522 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 };
529
530 gpio4: gpio@020a8000 {
531 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
532 reg = <0x020a8000 0x4000>;
533 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
540
541 gpio5: gpio@020ac000 {
542 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
543 reg = <0x020ac000 0x4000>;
544 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 };
551
552 snvslp: snvs@020b0000 {
553 compatible = "fsl,imx6ul-snvs";
554 reg = <0x020b0000 0x4000>;
555 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
556 };
557
558 fec2: ethernet@020b4000 {
559 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
560 reg = <0x020b4000 0x4000>;
561 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&clks IMX6UL_CLK_ENET>,
564 <&clks IMX6UL_CLK_ENET_AHB>,
565 <&clks IMX6UL_CLK_ENET_PTP>,
566 <&clks IMX6UL_CLK_ENET2_REF_125M>,
567 <&clks IMX6UL_CLK_ENET2_REF_125M>;
568 clock-names = "ipg", "ahb", "ptp",
569 "enet_clk_ref", "enet_out";
570 stop-mode = <&gpr 0x10 4>;
571 fsl,num-tx-queues=<1>;
572 fsl,num-rx-queues=<1>;
573 fsl,magic-packet;
574 fsl,wakeup_irq = <0>;
575 status = "disabled";
576 };
577
578 kpp: kpp@020b8000 {
579 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
580 reg = <0x020b8000 0x4000>;
581 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clks IMX6UL_CLK_DUMMY>;
583 status = "disabled";
584 };
585
586 wdog1: wdog@020bc000 {
587 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
588 reg = <0x020bc000 0x4000>;
589 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clks IMX6UL_CLK_WDOG1>;
591 };
592
593 wdog2: wdog@020c0000 {
594 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
595 reg = <0x020c0000 0x4000>;
596 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&clks IMX6UL_CLK_WDOG2>;
598 status = "disabled";
599 };
600
601 clks: ccm@020c4000 {
602 compatible = "fsl,imx6ul-ccm";
603 reg = <0x020c4000 0x4000>;
604 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
606 #clock-cells = <1>;
607 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
608 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
609 };
610
611 anatop: anatop@020c8000 {
612 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
613 "syscon", "simple-bus";
614 reg = <0x020c8000 0x1000>;
615 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
618
619 reg_3p0: regulator-3p0@120 {
620 compatible = "fsl,anatop-regulator";
621 regulator-name = "vdd3p0";
622 regulator-min-microvolt = <2625000>;
623 regulator-max-microvolt = <3400000>;
624 anatop-reg-offset = <0x120>;
625 anatop-vol-bit-shift = <8>;
626 anatop-vol-bit-width = <5>;
627 anatop-min-bit-val = <0>;
628 anatop-min-voltage = <2625000>;
629 anatop-max-voltage = <3400000>;
630 anatop-enable-bit = <0>;
631 };
632
633 reg_arm: regulator-vddcore@140 {
634 compatible = "fsl,anatop-regulator";
635 regulator-name = "cpu";
636 regulator-min-microvolt = <725000>;
637 regulator-max-microvolt = <1450000>;
638 regulator-always-on;
639 anatop-reg-offset = <0x140>;
640 anatop-vol-bit-shift = <0>;
641 anatop-vol-bit-width = <5>;
642 anatop-delay-reg-offset = <0x170>;
643 anatop-delay-bit-shift = <24>;
644 anatop-delay-bit-width = <2>;
645 anatop-min-bit-val = <1>;
646 anatop-min-voltage = <725000>;
647 anatop-max-voltage = <1450000>;
648 };
649
650 reg_soc: regulator-vddsoc@140 {
651 compatible = "fsl,anatop-regulator";
652 regulator-name = "vddsoc";
653 regulator-min-microvolt = <725000>;
654 regulator-max-microvolt = <1450000>;
655 regulator-always-on;
656 anatop-reg-offset = <0x140>;
657 anatop-vol-bit-shift = <18>;
658 anatop-vol-bit-width = <5>;
659 anatop-delay-reg-offset = <0x170>;
660 anatop-delay-bit-shift = <28>;
661 anatop-delay-bit-width = <2>;
662 anatop-min-bit-val = <1>;
663 anatop-min-voltage = <725000>;
664 anatop-max-voltage = <1450000>;
665 };
666 };
667
668 usbphy1: usbphy@020c9000 {
669 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
670 reg = <0x020c9000 0x1000>;
671 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6UL_CLK_USBPHY1>;
673 phy-3p0-supply = <&reg_3p0>;
674 fsl,anatop = <&anatop>;
675 };
676
677 usbphy2: usbphy@020ca000 {
678 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
679 reg = <0x020ca000 0x1000>;
680 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX6UL_CLK_USBPHY2>;
682 phy-3p0-supply = <&reg_3p0>;
683 fsl,anatop = <&anatop>;
684 };
685
686 tempmon: tempmon {
687 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
688 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
689 fsl,tempmon = <&anatop>;
690 fsl,tempmon-data = <&ocotp>;
691 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
692 };
693
694 snvs: snvs@020cc000 {
695 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
696 reg = <0x020cc000 0x4000>;
697
698 snvs_rtc: snvs-rtc-lp {
699 compatible = "fsl,sec-v4.0-mon-rtc-lp";
700 regmap = <&snvs>;
701 offset = <0x34>;
702 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
703 };
704
705 snvs_poweroff: snvs-poweroff {
706 compatible = "syscon-poweroff";
707 regmap = <&snvs>;
708 offset = <0x38>;
709 mask = <0x61>;
710 };
711
712 snvs_pwrkey: snvs-powerkey {
713 compatible = "fsl,sec-v4.0-pwrkey";
714 regmap = <&snvs>;
715 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
716 linux,keycode = <KEY_POWER>;
717 wakeup;
718 };
719 };
720
721 epit1: epit@020d0000 {
722 reg = <0x020d0000 0x4000>;
723 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
724 };
725
726 epit2: epit@020d4000 {
727 reg = <0x020d4000 0x4000>;
728 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
729 };
730
731 src: src@020d8000 {
732 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
733 reg = <0x020d8000 0x4000>;
734 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
736 #reset-cells = <1>;
737 };
738
739 gpc: gpc@020dc000 {
740 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
741 reg = <0x020dc000 0x4000>;
742 interrupt-controller;
743 #interrupt-cells = <3>;
744 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-parent = <&intc>;
746 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
747 };
748
749 iomuxc: iomuxc@020e0000 {
750 compatible = "fsl,imx6ul-iomuxc";
751 reg = <0x020e0000 0x4000>;
752 };
753
754 gpr: iomuxc-gpr@020e4000 {
755 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
756 reg = <0x020e4000 0x4000>;
757 };
758
759 mqs: mqs {
760 compatible = "fsl,imx6sx-mqs";
761 gpr = <&gpr>;
762 status = "disabled";
763 };
764
765 gpt2: gpt@020e8000 {
766 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
767 reg = <0x020e8000 0x4000>;
768 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clks IMX6UL_CLK_DUMMY>,
770 <&clks IMX6UL_CLK_DUMMY>;
771 clock-names = "ipg", "per";
772 };
773
774 sdma: sdma@020ec000 {
775 compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
776 reg = <0x020ec000 0x4000>;
777 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clks IMX6UL_CLK_SDMA>,
779 <&clks IMX6UL_CLK_SDMA>;
780 clock-names = "ipg", "ahb";
781 #dma-cells = <3>;
782 iram = <&ocram>;
783 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
784 };
785
786 pwm5: pwm@020f0000 {
787 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
788 reg = <0x020f0000 0x4000>;
789 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clks IMX6UL_CLK_DUMMY>,
791 <&clks IMX6UL_CLK_DUMMY>;
792 clock-names = "ipg", "per";
793 #pwm-cells = <2>;
794 };
795
796 pwm6: pwm@020f4000 {
797 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
798 reg = <0x020f4000 0x4000>;
799 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clks IMX6UL_CLK_DUMMY>,
801 <&clks IMX6UL_CLK_DUMMY>;
802 clock-names = "ipg", "per";
803 #pwm-cells = <2>;
804 };
805
806 pwm7: pwm@020f8000 {
807 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
808 reg = <0x020f8000 0x4000>;
809 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clks IMX6UL_CLK_DUMMY>,
811 <&clks IMX6UL_CLK_DUMMY>;
812 clock-names = "ipg", "per";
813 #pwm-cells = <2>;
814 };
815
816 pwm8: pwm@020fc000 {
817 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
818 reg = <0x020fc000 0x4000>;
819 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&clks IMX6UL_CLK_DUMMY>,
821 <&clks IMX6UL_CLK_DUMMY>;
822 clock-names = "ipg", "per";
823 #pwm-cells = <2>;
824 };
825 };
826
827 aips2: aips-bus@02100000 {
828 compatible = "fsl,aips-bus", "simple-bus";
829 #address-cells = <1>;
830 #size-cells = <1>;
831 reg = <0x02100000 0x100000>;
832 ranges;
833
834 usbotg1: usb@02184000 {
835 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
836 reg = <0x02184000 0x200>;
837 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clks IMX6UL_CLK_USBOH3>;
839 fsl,usbphy = <&usbphy1>;
840 fsl,usbmisc = <&usbmisc 0>;
841 fsl,anatop = <&anatop>;
842 ahb-burst-config = <0x0>;
843 tx-burst-size-dword = <0x10>;
844 rx-burst-size-dword = <0x10>;
845 status = "disabled";
846 };
847
848 usbotg2: usb@02184200 {
849 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
850 reg = <0x02184200 0x200>;
851 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6UL_CLK_USBOH3>;
853 fsl,usbphy = <&usbphy2>;
854 fsl,usbmisc = <&usbmisc 1>;
855 ahb-burst-config = <0x0>;
856 tx-burst-size-dword = <0x10>;
857 rx-burst-size-dword = <0x10>;
858 status = "disabled";
859 };
860
861 usbmisc: usbmisc@02184800 {
862 #index-cells = <1>;
863 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
864 reg = <0x02184800 0x200>;
865 };
866
867 fec1: ethernet@02188000 {
868 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
869 reg = <0x02188000 0x4000>;
870 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks IMX6UL_CLK_ENET>,
873 <&clks IMX6UL_CLK_ENET_AHB>,
874 <&clks IMX6UL_CLK_ENET_PTP>,
875 <&clks IMX6UL_CLK_ENET_REF>,
876 <&clks IMX6UL_CLK_ENET_REF>;
877 clock-names = "ipg", "ahb", "ptp",
878 "enet_clk_ref", "enet_out";
879 stop-mode = <&gpr 0x10 3>;
880 fsl,num-tx-queues=<1>;
881 fsl,num-rx-queues=<1>;
882 fsl,magic-packet;
883 fsl,wakeup_irq = <0>;
884 status = "disabled";
885 };
886
887 usdhc1: usdhc@02190000 {
888 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
889 reg = <0x02190000 0x4000>;
890 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&clks IMX6UL_CLK_USDHC1>,
892 <&clks IMX6UL_CLK_USDHC1>,
893 <&clks IMX6UL_CLK_USDHC1>;
894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
896 fsl,tuning-step= <2>;
897 status = "disabled";
898 };
899
900 usdhc2: usdhc@02194000 {
901 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
902 reg = <0x02194000 0x4000>;
903 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&clks IMX6UL_CLK_USDHC2>,
905 <&clks IMX6UL_CLK_USDHC2>,
906 <&clks IMX6UL_CLK_USDHC2>;
907 clock-names = "ipg", "ahb", "per";
908 bus-width = <4>;
909 fsl,tuning-step= <2>;
910 status = "disabled";
911 };
912
913 adc1: adc@02198000 {
914 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
915 reg = <0x02198000 0x4000>;
916 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clks IMX6UL_CLK_ADC1>;
918 num-channels = <2>;
919 clock-names = "adc";
920 status = "disabled";
921 };
922
923 i2c1: i2c@021a0000 {
924 #address-cells = <1>;
925 #size-cells = <0>;
926 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
927 reg = <0x021a0000 0x4000>;
928 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6UL_CLK_I2C1>;
930 status = "disabled";
931 };
932
933 i2c2: i2c@021a4000 {
934 #address-cells = <1>;
935 #size-cells = <0>;
936 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
937 reg = <0x021a4000 0x4000>;
938 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&clks IMX6UL_CLK_I2C2>;
940 status = "disabled";
941 };
942
943 i2c3: i2c@021a8000 {
944 #address-cells = <1>;
945 #size-cells = <0>;
946 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
947 reg = <0x021a8000 0x4000>;
948 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clks IMX6UL_CLK_I2C3>;
950 status = "disabled";
951 };
952
953 romcp@021ac000 {
954 compatible = "fsl,imx6ul-romcp", "syscon";
955 reg = <0x021ac000 0x4000>;
956 };
957
958 mmdc: mmdc@021b0000 {
959 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
960 reg = <0x021b0000 0x4000>;
961 };
962
963 weim: weim@021b8000 {
964 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
965 reg = <0x021b8000 0x4000>;
966 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&clks IMX6UL_CLK_DUMMY>;
968 };
969
970 ocotp: ocotp-ctrl@021bc000 {
971 compatible = "fsl,imx6ull-ocotp", "syscon";
972 reg = <0x021bc000 0x4000>;
973 clocks = <&clks IMX6UL_CLK_OCOTP>;
974 };
975
976 csu: csu@021c0000 {
977 compatible = "fsl,imx6ul-csu";
978 reg = <0x021c0000 0x4000>;
979 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
980 status = "disabled";
981 };
982
983 csi: csi@021c4000 {
984 compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
985 reg = <0x021c4000 0x4000>;
986 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&clks IMX6UL_CLK_DUMMY>,
988 <&clks IMX6UL_CLK_CSI>,
989 <&clks IMX6UL_CLK_DUMMY>;
990 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
991 status = "disabled";
992 };
993
994 lcdif: lcdif@021c8000 {
995 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
996 reg = <0x021c8000 0x4000>;
997 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
999 <&clks IMX6UL_CLK_LCDIF_APB>,
1000 <&clks IMX6UL_CLK_DUMMY>;
1001 clock-names = "pix", "axi", "disp_axi";
1002 status = "disabled";
1003 };
1004
1005 pxp: pxp@021cc000 {
1006 compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
1007 reg = <0x021cc000 0x4000>;
1008 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
1011 clock-names = "pxp_ipg", "pxp_axi";
1012 status = "disabled";
1013 };
1014
1015 qspi: qspi@021e0000 {
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi";
1019 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1020 reg-names = "QuadSPI", "QuadSPI-memory";
1021 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&clks IMX6UL_CLK_QSPI>,
1023 <&clks IMX6UL_CLK_QSPI>;
1024 clock-names = "qspi_en", "qspi";
1025 status = "disabled";
1026 };
1027
1028 uart2: serial@021e8000 {
1029 compatible = "fsl,imx6ul-uart",
1030 "fsl,imx6q-uart", "fsl,imx21-uart";
1031 reg = <0x021e8000 0x4000>;
1032 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1034 <&clks IMX6UL_CLK_UART2_SERIAL>;
1035 clock-names = "ipg", "per";
1036 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1037 dma-names = "rx", "tx";
1038 status = "disabled";
1039 };
1040
1041 uart3: serial@021ec000 {
1042 compatible = "fsl,imx6ul-uart",
1043 "fsl,imx6q-uart", "fsl,imx21-uart";
1044 reg = <0x021ec000 0x4000>;
1045 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1047 <&clks IMX6UL_CLK_UART3_SERIAL>;
1048 clock-names = "ipg", "per";
1049 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1050 dma-names = "rx", "tx";
1051 status = "disabled";
1052 };
1053
1054 uart4: serial@021f0000 {
1055 compatible = "fsl,imx6ul-uart",
1056 "fsl,imx6q-uart", "fsl,imx21-uart";
1057 reg = <0x021f0000 0x4000>;
1058 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1060 <&clks IMX6UL_CLK_UART4_SERIAL>;
1061 clock-names = "ipg", "per";
1062 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1063 dma-names = "rx", "tx";
1064 status = "disabled";
1065 };
1066
1067 uart5: serial@021f4000 {
1068 compatible = "fsl,imx6ul-uart",
1069 "fsl,imx6q-uart", "fsl,imx21-uart";
1070 reg = <0x021f4000 0x4000>;
1071 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1073 <&clks IMX6UL_CLK_UART5_SERIAL>;
1074 clock-names = "ipg", "per";
1075 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1076 dma-names = "rx", "tx";
1077 status = "disabled";
1078 };
1079
1080 i2c4: i2c@021f8000 {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1084 reg = <0x021f8000 0x4000>;
1085 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&clks IMX6UL_CLK_I2C4>;
1087 status = "disabled";
1088 };
1089
1090 uart6: serial@021fc000 {
1091 compatible = "fsl,imx6ul-uart",
1092 "fsl,imx6q-uart", "fsl,imx21-uart";
1093 reg = <0x021fc000 0x4000>;
1094 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1096 <&clks IMX6UL_CLK_UART6_SERIAL>;
1097 clock-names = "ipg", "per";
1098 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1099 dma-names = "rx", "tx";
1100 status = "disabled";
1101 };
1102 };
1103
1104 aips3: aips-bus@02200000 {
1105 compatible = "fsl,aips-bus", "simple-bus";
1106 #address-cells = <1>;
1107 #size-cells = <1>;
1108 reg = <0x02200000 0x100000>;
1109 ranges;
1110
1111 dcp: dcp@02280000 {
1112 reg = <0x02280000 0x4000>;
1113 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1115 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1116 /*clocks = <&clks IMX6UL_CLK_DCP>;*/
1117 clock-names = "dcp";
1118 status = "disabled";
1119 };
1120
1121 rngb: rngb@02284000 {
1122 reg = <0x02284000 0x4000>;
1123 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1124 };
1125
1126 uart8: serial@02288000 {
1127 compatible = "fsl,imx6ul-uart",
1128 "fsl,imx6q-uart", "fsl,imx21-uart";
1129 reg = <0x02288000 0x4000>;
1130 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
1132 <&clks IMX6UL_CLK_UART8_SERIAL>;
1133 clock-names = "ipg", "per";
1134 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
1135 dma-names = "rx", "tx";
1136 status = "disabled";
1137 };
1138
1139 epdc: epdc@0228c000 {
1140 compatible = "fsl,imx7d-epdc";
1141 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1142 reg = <0x0228c000 0x4000>;
1143 clocks = <&clks IMX6UL_CLK_EPDC_ACLK>,
1144 <&clks IMX6UL_CLK_EPDC_PIX>;
1145 clock-names = "epdc_axi", "epdc_pix";
1146 /* Need to fix epdc-ram */
1147 /* epdc-ram = <&gpr 0x4 30>; */
1148 status = "disabled";
1149 };
1150
1151 iomuxc_snvs: iomuxc-snvs@02290000 {
1152 compatible = "fsl,imx6ull-iomuxc-snvs";
1153 reg = <0x02290000 0x10000>;
1154 };
1155
1156 snvs_gpr: snvs-gpr@0x02294000 {
1157 compatible = "fsl, imx6ull-snvs-gpr";
1158 reg = <0x02294000 0x10000>;
1159 };
1160 };
1161 };
1162 };
"Das U-Boot" Source Tree