]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/dts/r8a7795.dtsi
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mtd/spi: fix block count for is25lq040b
[people/ms/u-boot.git] / arch / arm / dts / r8a7795.dtsi
1 /*
2 * Device Tree Source for the r8a7795 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a7795-sysc.h>
14
15 / {
16 compatible = "renesas,r8a7795";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
29 };
30
31 psci {
32 compatible = "arm,psci-1.0", "arm,psci-0.2";
33 method = "smc";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 a57_0: cpu@0 {
41 compatible = "arm,cortex-a57", "arm,armv8";
42 reg = <0x0>;
43 device_type = "cpu";
44 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
45 next-level-cache = <&L2_CA57>;
46 enable-method = "psci";
47 };
48
49 a57_1: cpu@1 {
50 compatible = "arm,cortex-a57","arm,armv8";
51 reg = <0x1>;
52 device_type = "cpu";
53 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
54 next-level-cache = <&L2_CA57>;
55 enable-method = "psci";
56 };
57
58 a57_2: cpu@2 {
59 compatible = "arm,cortex-a57","arm,armv8";
60 reg = <0x2>;
61 device_type = "cpu";
62 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
63 next-level-cache = <&L2_CA57>;
64 enable-method = "psci";
65 };
66
67 a57_3: cpu@3 {
68 compatible = "arm,cortex-a57","arm,armv8";
69 reg = <0x3>;
70 device_type = "cpu";
71 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
72 next-level-cache = <&L2_CA57>;
73 enable-method = "psci";
74 };
75
76 a53_0: cpu@100 {
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0x100>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
81 next-level-cache = <&L2_CA53>;
82 enable-method = "psci";
83 };
84
85 a53_1: cpu@101 {
86 compatible = "arm,cortex-a53","arm,armv8";
87 reg = <0x101>;
88 device_type = "cpu";
89 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
92 };
93
94 a53_2: cpu@102 {
95 compatible = "arm,cortex-a53","arm,armv8";
96 reg = <0x102>;
97 device_type = "cpu";
98 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
99 next-level-cache = <&L2_CA53>;
100 enable-method = "psci";
101 };
102
103 a53_3: cpu@103 {
104 compatible = "arm,cortex-a53","arm,armv8";
105 reg = <0x103>;
106 device_type = "cpu";
107 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
108 next-level-cache = <&L2_CA53>;
109 enable-method = "psci";
110 };
111
112 L2_CA57: cache-controller-0 {
113 compatible = "cache";
114 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
115 cache-unified;
116 cache-level = <2>;
117 };
118
119 L2_CA53: cache-controller-1 {
120 compatible = "cache";
121 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
122 cache-unified;
123 cache-level = <2>;
124 };
125 };
126
127 extal_clk: extal {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 /* This value must be overridden by the board */
131 clock-frequency = <0>;
132 u-boot,dm-pre-reloc;
133 };
134
135 extalr_clk: extalr {
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 /* This value must be overridden by the board */
139 clock-frequency = <0>;
140 u-boot,dm-pre-reloc;
141 };
142
143 /*
144 * The external audio clocks are configured as 0 Hz fixed frequency
145 * clocks by default.
146 * Boards that provide audio clocks should override them.
147 */
148 audio_clk_a: audio_clk_a {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <0>;
152 };
153
154 audio_clk_b: audio_clk_b {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <0>;
158 };
159
160 audio_clk_c: audio_clk_c {
161 compatible = "fixed-clock";
162 #clock-cells = <0>;
163 clock-frequency = <0>;
164 };
165
166 /* External CAN clock - to be overridden by boards that provide it */
167 can_clk: can {
168 compatible = "fixed-clock";
169 #clock-cells = <0>;
170 clock-frequency = <0>;
171 };
172
173 /* External SCIF clock - to be overridden by boards that provide it */
174 scif_clk: scif {
175 compatible = "fixed-clock";
176 #clock-cells = <0>;
177 clock-frequency = <0>;
178 };
179
180 /* External PCIe clock - can be overridden by the board */
181 pcie_bus_clk: pcie_bus {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <0>;
185 };
186
187 soc: soc {
188 compatible = "simple-bus";
189 interrupt-parent = <&gic>;
190
191 #address-cells = <2>;
192 #size-cells = <2>;
193 ranges;
194 u-boot,dm-pre-reloc;
195
196 gic: interrupt-controller@f1010000 {
197 compatible = "arm,gic-400";
198 #interrupt-cells = <3>;
199 #address-cells = <0>;
200 interrupt-controller;
201 reg = <0x0 0xf1010000 0 0x1000>,
202 <0x0 0xf1020000 0 0x20000>,
203 <0x0 0xf1040000 0 0x20000>,
204 <0x0 0xf1060000 0 0x20000>;
205 interrupts = <GIC_PPI 9
206 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
207 clocks = <&cpg CPG_MOD 408>;
208 clock-names = "clk";
209 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
210 resets = <&cpg 408>;
211 };
212
213 wdt0: watchdog@e6020000 {
214 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
215 reg = <0 0xe6020000 0 0x0c>;
216 clocks = <&cpg CPG_MOD 402>;
217 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
218 resets = <&cpg 402>;
219 status = "disabled";
220 };
221
222 gpio0: gpio@e6050000 {
223 compatible = "renesas,gpio-r8a7795",
224 "renesas,gpio-rcar";
225 reg = <0 0xe6050000 0 0x50>;
226 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
227 #gpio-cells = <2>;
228 gpio-controller;
229 gpio-ranges = <&pfc 0 0 16>;
230 #interrupt-cells = <2>;
231 interrupt-controller;
232 clocks = <&cpg CPG_MOD 912>;
233 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
234 resets = <&cpg 912>;
235 };
236
237 gpio1: gpio@e6051000 {
238 compatible = "renesas,gpio-r8a7795",
239 "renesas,gpio-rcar";
240 reg = <0 0xe6051000 0 0x50>;
241 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
242 #gpio-cells = <2>;
243 gpio-controller;
244 gpio-ranges = <&pfc 0 32 28>;
245 #interrupt-cells = <2>;
246 interrupt-controller;
247 clocks = <&cpg CPG_MOD 911>;
248 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
249 resets = <&cpg 911>;
250 };
251
252 gpio2: gpio@e6052000 {
253 compatible = "renesas,gpio-r8a7795",
254 "renesas,gpio-rcar";
255 reg = <0 0xe6052000 0 0x50>;
256 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 gpio-ranges = <&pfc 0 64 15>;
260 #interrupt-cells = <2>;
261 interrupt-controller;
262 clocks = <&cpg CPG_MOD 910>;
263 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
264 resets = <&cpg 910>;
265 };
266
267 gpio3: gpio@e6053000 {
268 compatible = "renesas,gpio-r8a7795",
269 "renesas,gpio-rcar";
270 reg = <0 0xe6053000 0 0x50>;
271 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
272 #gpio-cells = <2>;
273 gpio-controller;
274 gpio-ranges = <&pfc 0 96 16>;
275 #interrupt-cells = <2>;
276 interrupt-controller;
277 clocks = <&cpg CPG_MOD 909>;
278 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
279 resets = <&cpg 909>;
280 };
281
282 gpio4: gpio@e6054000 {
283 compatible = "renesas,gpio-r8a7795",
284 "renesas,gpio-rcar";
285 reg = <0 0xe6054000 0 0x50>;
286 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
287 #gpio-cells = <2>;
288 gpio-controller;
289 gpio-ranges = <&pfc 0 128 18>;
290 #interrupt-cells = <2>;
291 interrupt-controller;
292 clocks = <&cpg CPG_MOD 908>;
293 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
294 resets = <&cpg 908>;
295 };
296
297 gpio5: gpio@e6055000 {
298 compatible = "renesas,gpio-r8a7795",
299 "renesas,gpio-rcar";
300 reg = <0 0xe6055000 0 0x50>;
301 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
302 #gpio-cells = <2>;
303 gpio-controller;
304 gpio-ranges = <&pfc 0 160 26>;
305 #interrupt-cells = <2>;
306 interrupt-controller;
307 clocks = <&cpg CPG_MOD 907>;
308 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
309 resets = <&cpg 907>;
310 };
311
312 gpio6: gpio@e6055400 {
313 compatible = "renesas,gpio-r8a7795",
314 "renesas,gpio-rcar";
315 reg = <0 0xe6055400 0 0x50>;
316 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
317 #gpio-cells = <2>;
318 gpio-controller;
319 gpio-ranges = <&pfc 0 192 32>;
320 #interrupt-cells = <2>;
321 interrupt-controller;
322 clocks = <&cpg CPG_MOD 906>;
323 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
324 resets = <&cpg 906>;
325 };
326
327 gpio7: gpio@e6055800 {
328 compatible = "renesas,gpio-r8a7795",
329 "renesas,gpio-rcar";
330 reg = <0 0xe6055800 0 0x50>;
331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
332 #gpio-cells = <2>;
333 gpio-controller;
334 gpio-ranges = <&pfc 0 224 4>;
335 #interrupt-cells = <2>;
336 interrupt-controller;
337 clocks = <&cpg CPG_MOD 905>;
338 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
339 resets = <&cpg 905>;
340 };
341
342 pmu_a57 {
343 compatible = "arm,cortex-a57-pmu";
344 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-affinity = <&a57_0>,
349 <&a57_1>,
350 <&a57_2>,
351 <&a57_3>;
352 };
353
354 pmu_a53 {
355 compatible = "arm,cortex-a53-pmu";
356 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-affinity = <&a53_0>,
361 <&a53_1>,
362 <&a53_2>,
363 <&a53_3>;
364 };
365
366 timer {
367 compatible = "arm,armv8-timer";
368 interrupts = <GIC_PPI 13
369 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
370 <GIC_PPI 14
371 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
372 <GIC_PPI 11
373 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
374 <GIC_PPI 10
375 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
376 };
377
378 cpg: clock-controller@e6150000 {
379 compatible = "renesas,r8a7795-cpg-mssr";
380 reg = <0 0xe6150000 0 0x1000>;
381 clocks = <&extal_clk>, <&extalr_clk>;
382 clock-names = "extal", "extalr";
383 #clock-cells = <2>;
384 #power-domain-cells = <0>;
385 #reset-cells = <1>;
386 u-boot,dm-pre-reloc;
387 };
388
389 rst: reset-controller@e6160000 {
390 compatible = "renesas,r8a7795-rst";
391 reg = <0 0xe6160000 0 0x0200>;
392 };
393
394 prr: chipid@fff00044 {
395 compatible = "renesas,prr";
396 reg = <0 0xfff00044 0 4>;
397 };
398
399 sysc: system-controller@e6180000 {
400 compatible = "renesas,r8a7795-sysc";
401 reg = <0 0xe6180000 0 0x0400>;
402 #power-domain-cells = <1>;
403 };
404
405 pfc: pin-controller@e6060000 {
406 compatible = "renesas,pfc-r8a7795";
407 reg = <0 0xe6060000 0 0x50c>;
408 };
409
410 intc_ex: interrupt-controller@e61c0000 {
411 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
412 #interrupt-cells = <2>;
413 interrupt-controller;
414 reg = <0 0xe61c0000 0 0x200>;
415 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 407>;
422 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
423 resets = <&cpg 407>;
424 };
425
426 dmac0: dma-controller@e6700000 {
427 compatible = "renesas,dmac-r8a7795",
428 "renesas,rcar-dmac";
429 reg = <0 0xe6700000 0 0x10000>;
430 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
433 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
436 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
437 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
444 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "error",
448 "ch0", "ch1", "ch2", "ch3",
449 "ch4", "ch5", "ch6", "ch7",
450 "ch8", "ch9", "ch10", "ch11",
451 "ch12", "ch13", "ch14", "ch15";
452 clocks = <&cpg CPG_MOD 219>;
453 clock-names = "fck";
454 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
455 resets = <&cpg 219>;
456 #dma-cells = <1>;
457 dma-channels = <16>;
458 };
459
460 dmac1: dma-controller@e7300000 {
461 compatible = "renesas,dmac-r8a7795",
462 "renesas,rcar-dmac";
463 reg = <0 0xe7300000 0 0x10000>;
464 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
465 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
466 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
467 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
468 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
469 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
470 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
471 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
473 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
474 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
477 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
478 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
479 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
480 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-names = "error",
482 "ch0", "ch1", "ch2", "ch3",
483 "ch4", "ch5", "ch6", "ch7",
484 "ch8", "ch9", "ch10", "ch11",
485 "ch12", "ch13", "ch14", "ch15";
486 clocks = <&cpg CPG_MOD 218>;
487 clock-names = "fck";
488 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
489 resets = <&cpg 218>;
490 #dma-cells = <1>;
491 dma-channels = <16>;
492 };
493
494 dmac2: dma-controller@e7310000 {
495 compatible = "renesas,dmac-r8a7795",
496 "renesas,rcar-dmac";
497 reg = <0 0xe7310000 0 0x10000>;
498 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
499 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
500 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
501 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
502 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
503 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
504 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
505 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
506 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
507 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
508 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
509 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
510 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
511 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
512 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
513 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
514 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
515 interrupt-names = "error",
516 "ch0", "ch1", "ch2", "ch3",
517 "ch4", "ch5", "ch6", "ch7",
518 "ch8", "ch9", "ch10", "ch11",
519 "ch12", "ch13", "ch14", "ch15";
520 clocks = <&cpg CPG_MOD 217>;
521 clock-names = "fck";
522 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
523 resets = <&cpg 217>;
524 #dma-cells = <1>;
525 dma-channels = <16>;
526 };
527
528 audma0: dma-controller@ec700000 {
529 compatible = "renesas,dmac-r8a7795",
530 "renesas,rcar-dmac";
531 reg = <0 0xec700000 0 0x10000>;
532 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
533 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
534 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
535 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
536 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
537 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
538 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
539 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
540 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
541 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
542 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
543 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
544 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
545 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
546 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
547 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
548 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "error",
550 "ch0", "ch1", "ch2", "ch3",
551 "ch4", "ch5", "ch6", "ch7",
552 "ch8", "ch9", "ch10", "ch11",
553 "ch12", "ch13", "ch14", "ch15";
554 clocks = <&cpg CPG_MOD 502>;
555 clock-names = "fck";
556 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
557 resets = <&cpg 502>;
558 #dma-cells = <1>;
559 dma-channels = <16>;
560 };
561
562 audma1: dma-controller@ec720000 {
563 compatible = "renesas,dmac-r8a7795",
564 "renesas,rcar-dmac";
565 reg = <0 0xec720000 0 0x10000>;
566 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
567 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
568 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
569 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
570 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
571 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
572 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
573 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
574 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
575 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
576 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
577 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
578 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
579 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
580 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
581 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
582 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "error",
584 "ch0", "ch1", "ch2", "ch3",
585 "ch4", "ch5", "ch6", "ch7",
586 "ch8", "ch9", "ch10", "ch11",
587 "ch12", "ch13", "ch14", "ch15";
588 clocks = <&cpg CPG_MOD 501>;
589 clock-names = "fck";
590 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
591 resets = <&cpg 501>;
592 #dma-cells = <1>;
593 dma-channels = <16>;
594 };
595
596 avb: ethernet@e6800000 {
597 compatible = "renesas,etheravb-r8a7795",
598 "renesas,etheravb-rcar-gen3";
599 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
600 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "ch0", "ch1", "ch2", "ch3",
626 "ch4", "ch5", "ch6", "ch7",
627 "ch8", "ch9", "ch10", "ch11",
628 "ch12", "ch13", "ch14", "ch15",
629 "ch16", "ch17", "ch18", "ch19",
630 "ch20", "ch21", "ch22", "ch23",
631 "ch24";
632 clocks = <&cpg CPG_MOD 812>;
633 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
634 resets = <&cpg 812>;
635 phy-mode = "rgmii-txid";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 status = "disabled";
639 };
640
641 can0: can@e6c30000 {
642 compatible = "renesas,can-r8a7795",
643 "renesas,rcar-gen3-can";
644 reg = <0 0xe6c30000 0 0x1000>;
645 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cpg CPG_MOD 916>,
647 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
648 <&can_clk>;
649 clock-names = "clkp1", "clkp2", "can_clk";
650 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
651 assigned-clock-rates = <40000000>;
652 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
653 resets = <&cpg 916>;
654 status = "disabled";
655 };
656
657 can1: can@e6c38000 {
658 compatible = "renesas,can-r8a7795",
659 "renesas,rcar-gen3-can";
660 reg = <0 0xe6c38000 0 0x1000>;
661 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 915>,
663 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
664 <&can_clk>;
665 clock-names = "clkp1", "clkp2", "can_clk";
666 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
667 assigned-clock-rates = <40000000>;
668 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
669 resets = <&cpg 915>;
670 status = "disabled";
671 };
672
673 canfd: can@e66c0000 {
674 compatible = "renesas,r8a7795-canfd",
675 "renesas,rcar-gen3-canfd";
676 reg = <0 0xe66c0000 0 0x8000>;
677 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&cpg CPG_MOD 914>,
680 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
681 <&can_clk>;
682 clock-names = "fck", "canfd", "can_clk";
683 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
684 assigned-clock-rates = <40000000>;
685 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
686 resets = <&cpg 914>;
687 status = "disabled";
688
689 channel0 {
690 status = "disabled";
691 };
692
693 channel1 {
694 status = "disabled";
695 };
696 };
697
698 hscif0: serial@e6540000 {
699 compatible = "renesas,hscif-r8a7795",
700 "renesas,rcar-gen3-hscif",
701 "renesas,hscif";
702 reg = <0 0xe6540000 0 96>;
703 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&cpg CPG_MOD 520>,
705 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
706 <&scif_clk>;
707 clock-names = "fck", "brg_int", "scif_clk";
708 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
709 dma-names = "tx", "rx";
710 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
711 resets = <&cpg 520>;
712 status = "disabled";
713 };
714
715 hscif1: serial@e6550000 {
716 compatible = "renesas,hscif-r8a7795",
717 "renesas,rcar-gen3-hscif",
718 "renesas,hscif";
719 reg = <0 0xe6550000 0 96>;
720 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 519>,
722 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
723 <&scif_clk>;
724 clock-names = "fck", "brg_int", "scif_clk";
725 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
726 dma-names = "tx", "rx";
727 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
728 resets = <&cpg 519>;
729 status = "disabled";
730 };
731
732 hscif2: serial@e6560000 {
733 compatible = "renesas,hscif-r8a7795",
734 "renesas,rcar-gen3-hscif",
735 "renesas,hscif";
736 reg = <0 0xe6560000 0 96>;
737 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&cpg CPG_MOD 518>,
739 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
740 <&scif_clk>;
741 clock-names = "fck", "brg_int", "scif_clk";
742 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
743 dma-names = "tx", "rx";
744 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
745 resets = <&cpg 518>;
746 status = "disabled";
747 };
748
749 hscif3: serial@e66a0000 {
750 compatible = "renesas,hscif-r8a7795",
751 "renesas,rcar-gen3-hscif",
752 "renesas,hscif";
753 reg = <0 0xe66a0000 0 96>;
754 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&cpg CPG_MOD 517>,
756 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
757 <&scif_clk>;
758 clock-names = "fck", "brg_int", "scif_clk";
759 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
760 dma-names = "tx", "rx";
761 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
762 resets = <&cpg 517>;
763 status = "disabled";
764 };
765
766 hscif4: serial@e66b0000 {
767 compatible = "renesas,hscif-r8a7795",
768 "renesas,rcar-gen3-hscif",
769 "renesas,hscif";
770 reg = <0 0xe66b0000 0 96>;
771 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&cpg CPG_MOD 516>,
773 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
776 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
777 dma-names = "tx", "rx";
778 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
779 resets = <&cpg 516>;
780 status = "disabled";
781 };
782
783 scif0: serial@e6e60000 {
784 compatible = "renesas,scif-r8a7795",
785 "renesas,rcar-gen3-scif", "renesas,scif";
786 reg = <0 0xe6e60000 0 64>;
787 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cpg CPG_MOD 207>,
789 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
790 <&scif_clk>;
791 clock-names = "fck", "brg_int", "scif_clk";
792 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
793 dma-names = "tx", "rx";
794 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
795 resets = <&cpg 207>;
796 status = "disabled";
797 };
798
799 scif1: serial@e6e68000 {
800 compatible = "renesas,scif-r8a7795",
801 "renesas,rcar-gen3-scif", "renesas,scif";
802 reg = <0 0xe6e68000 0 64>;
803 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&cpg CPG_MOD 206>,
805 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
806 <&scif_clk>;
807 clock-names = "fck", "brg_int", "scif_clk";
808 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
809 dma-names = "tx", "rx";
810 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
811 resets = <&cpg 206>;
812 status = "disabled";
813 };
814
815 scif2: serial@e6e88000 {
816 compatible = "renesas,scif-r8a7795",
817 "renesas,rcar-gen3-scif", "renesas,scif";
818 reg = <0 0xe6e88000 0 64>;
819 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 310>,
821 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
822 <&scif_clk>;
823 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
825 dma-names = "tx", "rx";
826 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
827 resets = <&cpg 310>;
828 status = "disabled";
829 };
830
831 scif3: serial@e6c50000 {
832 compatible = "renesas,scif-r8a7795",
833 "renesas,rcar-gen3-scif", "renesas,scif";
834 reg = <0 0xe6c50000 0 64>;
835 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&cpg CPG_MOD 204>,
837 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
838 <&scif_clk>;
839 clock-names = "fck", "brg_int", "scif_clk";
840 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
841 dma-names = "tx", "rx";
842 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
843 resets = <&cpg 204>;
844 status = "disabled";
845 };
846
847 scif4: serial@e6c40000 {
848 compatible = "renesas,scif-r8a7795",
849 "renesas,rcar-gen3-scif", "renesas,scif";
850 reg = <0 0xe6c40000 0 64>;
851 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&cpg CPG_MOD 203>,
853 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
854 <&scif_clk>;
855 clock-names = "fck", "brg_int", "scif_clk";
856 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
857 dma-names = "tx", "rx";
858 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
859 resets = <&cpg 203>;
860 status = "disabled";
861 };
862
863 scif5: serial@e6f30000 {
864 compatible = "renesas,scif-r8a7795",
865 "renesas,rcar-gen3-scif", "renesas,scif";
866 reg = <0 0xe6f30000 0 64>;
867 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&cpg CPG_MOD 202>,
869 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
870 <&scif_clk>;
871 clock-names = "fck", "brg_int", "scif_clk";
872 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
873 dma-names = "tx", "rx";
874 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
875 resets = <&cpg 202>;
876 status = "disabled";
877 };
878
879 i2c_dvfs: i2c@e60b0000 {
880 #address-cells = <1>;
881 #size-cells = <0>;
882 compatible = "renesas,iic-r8a7795",
883 "renesas,rcar-gen3-iic",
884 "renesas,rmobile-iic";
885 reg = <0 0xe60b0000 0 0x425>;
886 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&cpg CPG_MOD 926>;
888 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
889 resets = <&cpg 926>;
890 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
891 dma-names = "tx", "rx";
892 status = "disabled";
893 };
894
895 i2c0: i2c@e6500000 {
896 #address-cells = <1>;
897 #size-cells = <0>;
898 compatible = "renesas,i2c-r8a7795",
899 "renesas,rcar-gen3-i2c";
900 reg = <0 0xe6500000 0 0x40>;
901 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&cpg CPG_MOD 931>;
903 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
904 resets = <&cpg 931>;
905 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
906 dma-names = "tx", "rx";
907 i2c-scl-internal-delay-ns = <110>;
908 status = "disabled";
909 };
910
911 i2c1: i2c@e6508000 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 compatible = "renesas,i2c-r8a7795",
915 "renesas,rcar-gen3-i2c";
916 reg = <0 0xe6508000 0 0x40>;
917 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&cpg CPG_MOD 930>;
919 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
920 resets = <&cpg 930>;
921 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
922 dma-names = "tx", "rx";
923 i2c-scl-internal-delay-ns = <6>;
924 status = "disabled";
925 };
926
927 i2c2: i2c@e6510000 {
928 #address-cells = <1>;
929 #size-cells = <0>;
930 compatible = "renesas,i2c-r8a7795",
931 "renesas,rcar-gen3-i2c";
932 reg = <0 0xe6510000 0 0x40>;
933 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&cpg CPG_MOD 929>;
935 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
936 resets = <&cpg 929>;
937 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
938 dma-names = "tx", "rx";
939 i2c-scl-internal-delay-ns = <6>;
940 status = "disabled";
941 };
942
943 i2c3: i2c@e66d0000 {
944 #address-cells = <1>;
945 #size-cells = <0>;
946 compatible = "renesas,i2c-r8a7795",
947 "renesas,rcar-gen3-i2c";
948 reg = <0 0xe66d0000 0 0x40>;
949 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cpg CPG_MOD 928>;
951 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
952 resets = <&cpg 928>;
953 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
954 dma-names = "tx", "rx";
955 i2c-scl-internal-delay-ns = <110>;
956 status = "disabled";
957 };
958
959 i2c4: i2c@e66d8000 {
960 #address-cells = <1>;
961 #size-cells = <0>;
962 compatible = "renesas,i2c-r8a7795",
963 "renesas,rcar-gen3-i2c";
964 reg = <0 0xe66d8000 0 0x40>;
965 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&cpg CPG_MOD 927>;
967 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
968 resets = <&cpg 927>;
969 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
970 dma-names = "tx", "rx";
971 i2c-scl-internal-delay-ns = <110>;
972 status = "disabled";
973 };
974
975 i2c5: i2c@e66e0000 {
976 #address-cells = <1>;
977 #size-cells = <0>;
978 compatible = "renesas,i2c-r8a7795",
979 "renesas,rcar-gen3-i2c";
980 reg = <0 0xe66e0000 0 0x40>;
981 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cpg CPG_MOD 919>;
983 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
984 resets = <&cpg 919>;
985 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
986 dma-names = "tx", "rx";
987 i2c-scl-internal-delay-ns = <110>;
988 status = "disabled";
989 };
990
991 i2c6: i2c@e66e8000 {
992 #address-cells = <1>;
993 #size-cells = <0>;
994 compatible = "renesas,i2c-r8a7795",
995 "renesas,rcar-gen3-i2c";
996 reg = <0 0xe66e8000 0 0x40>;
997 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&cpg CPG_MOD 918>;
999 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1000 resets = <&cpg 918>;
1001 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
1002 dma-names = "tx", "rx";
1003 i2c-scl-internal-delay-ns = <6>;
1004 status = "disabled";
1005 };
1006
1007 pwm0: pwm@e6e30000 {
1008 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1009 reg = <0 0xe6e30000 0 0x8>;
1010 clocks = <&cpg CPG_MOD 523>;
1011 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1012 resets = <&cpg 523>;
1013 #pwm-cells = <2>;
1014 status = "disabled";
1015 };
1016
1017 pwm1: pwm@e6e31000 {
1018 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1019 reg = <0 0xe6e31000 0 0x8>;
1020 clocks = <&cpg CPG_MOD 523>;
1021 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1022 resets = <&cpg 523>;
1023 #pwm-cells = <2>;
1024 status = "disabled";
1025 };
1026
1027 pwm2: pwm@e6e32000 {
1028 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1029 reg = <0 0xe6e32000 0 0x8>;
1030 clocks = <&cpg CPG_MOD 523>;
1031 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1032 resets = <&cpg 523>;
1033 #pwm-cells = <2>;
1034 status = "disabled";
1035 };
1036
1037 pwm3: pwm@e6e33000 {
1038 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1039 reg = <0 0xe6e33000 0 0x8>;
1040 clocks = <&cpg CPG_MOD 523>;
1041 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1042 resets = <&cpg 523>;
1043 #pwm-cells = <2>;
1044 status = "disabled";
1045 };
1046
1047 pwm4: pwm@e6e34000 {
1048 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1049 reg = <0 0xe6e34000 0 0x8>;
1050 clocks = <&cpg CPG_MOD 523>;
1051 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1052 resets = <&cpg 523>;
1053 #pwm-cells = <2>;
1054 status = "disabled";
1055 };
1056
1057 pwm5: pwm@e6e35000 {
1058 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1059 reg = <0 0xe6e35000 0 0x8>;
1060 clocks = <&cpg CPG_MOD 523>;
1061 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1062 resets = <&cpg 523>;
1063 #pwm-cells = <2>;
1064 status = "disabled";
1065 };
1066
1067 pwm6: pwm@e6e36000 {
1068 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1069 reg = <0 0xe6e36000 0 0x8>;
1070 clocks = <&cpg CPG_MOD 523>;
1071 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1072 resets = <&cpg 523>;
1073 #pwm-cells = <2>;
1074 status = "disabled";
1075 };
1076
1077 rcar_sound: sound@ec500000 {
1078 /*
1079 * #sound-dai-cells is required
1080 *
1081 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1082 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1083 */
1084 /*
1085 * #clock-cells is required for audio_clkout0/1/2/3
1086 *
1087 * clkout : #clock-cells = <0>; <&rcar_sound>;
1088 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1089 */
1090 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
1091 reg = <0 0xec500000 0 0x1000>, /* SCU */
1092 <0 0xec5a0000 0 0x100>, /* ADG */
1093 <0 0xec540000 0 0x1000>, /* SSIU */
1094 <0 0xec541000 0 0x280>, /* SSI */
1095 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1096 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1097
1098 clocks = <&cpg CPG_MOD 1005>,
1099 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1100 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1101 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1102 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1103 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1104 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1105 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1106 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1107 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1108 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1109 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1110 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1111 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1112 <&audio_clk_a>, <&audio_clk_b>,
1113 <&audio_clk_c>,
1114 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
1115 clock-names = "ssi-all",
1116 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1117 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1118 "ssi.1", "ssi.0",
1119 "src.9", "src.8", "src.7", "src.6",
1120 "src.5", "src.4", "src.3", "src.2",
1121 "src.1", "src.0",
1122 "mix.1", "mix.0",
1123 "ctu.1", "ctu.0",
1124 "dvc.0", "dvc.1",
1125 "clk_a", "clk_b", "clk_c", "clk_i";
1126 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1127 resets = <&cpg 1005>,
1128 <&cpg 1006>, <&cpg 1007>,
1129 <&cpg 1008>, <&cpg 1009>,
1130 <&cpg 1010>, <&cpg 1011>,
1131 <&cpg 1012>, <&cpg 1013>,
1132 <&cpg 1014>, <&cpg 1015>;
1133 reset-names = "ssi-all",
1134 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1135 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1136 "ssi.1", "ssi.0";
1137 status = "disabled";
1138
1139 rcar_sound,dvc {
1140 dvc0: dvc-0 {
1141 dmas = <&audma1 0xbc>;
1142 dma-names = "tx";
1143 };
1144 dvc1: dvc-1 {
1145 dmas = <&audma1 0xbe>;
1146 dma-names = "tx";
1147 };
1148 };
1149
1150 rcar_sound,mix {
1151 mix0: mix-0 { };
1152 mix1: mix-1 { };
1153 };
1154
1155 rcar_sound,ctu {
1156 ctu00: ctu-0 { };
1157 ctu01: ctu-1 { };
1158 ctu02: ctu-2 { };
1159 ctu03: ctu-3 { };
1160 ctu10: ctu-4 { };
1161 ctu11: ctu-5 { };
1162 ctu12: ctu-6 { };
1163 ctu13: ctu-7 { };
1164 };
1165
1166 rcar_sound,src {
1167 src0: src-0 {
1168 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1169 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1170 dma-names = "rx", "tx";
1171 };
1172 src1: src-1 {
1173 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1174 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1175 dma-names = "rx", "tx";
1176 };
1177 src2: src-2 {
1178 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1179 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1180 dma-names = "rx", "tx";
1181 };
1182 src3: src-3 {
1183 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1184 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1185 dma-names = "rx", "tx";
1186 };
1187 src4: src-4 {
1188 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1189 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1190 dma-names = "rx", "tx";
1191 };
1192 src5: src-5 {
1193 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1194 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1195 dma-names = "rx", "tx";
1196 };
1197 src6: src-6 {
1198 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1199 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1200 dma-names = "rx", "tx";
1201 };
1202 src7: src-7 {
1203 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1204 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1205 dma-names = "rx", "tx";
1206 };
1207 src8: src-8 {
1208 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1209 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1210 dma-names = "rx", "tx";
1211 };
1212 src9: src-9 {
1213 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1214 dmas = <&audma0 0x97>, <&audma1 0xba>;
1215 dma-names = "rx", "tx";
1216 };
1217 };
1218
1219 rcar_sound,ssi {
1220 ssi0: ssi-0 {
1221 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1222 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1223 dma-names = "rx", "tx", "rxu", "txu";
1224 };
1225 ssi1: ssi-1 {
1226 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1227 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1228 dma-names = "rx", "tx", "rxu", "txu";
1229 };
1230 ssi2: ssi-2 {
1231 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1232 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1233 dma-names = "rx", "tx", "rxu", "txu";
1234 };
1235 ssi3: ssi-3 {
1236 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1237 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1238 dma-names = "rx", "tx", "rxu", "txu";
1239 };
1240 ssi4: ssi-4 {
1241 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1242 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1243 dma-names = "rx", "tx", "rxu", "txu";
1244 };
1245 ssi5: ssi-5 {
1246 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1248 dma-names = "rx", "tx", "rxu", "txu";
1249 };
1250 ssi6: ssi-6 {
1251 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1252 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1253 dma-names = "rx", "tx", "rxu", "txu";
1254 };
1255 ssi7: ssi-7 {
1256 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1257 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1258 dma-names = "rx", "tx", "rxu", "txu";
1259 };
1260 ssi8: ssi-8 {
1261 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1262 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1263 dma-names = "rx", "tx", "rxu", "txu";
1264 };
1265 ssi9: ssi-9 {
1266 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1267 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1268 dma-names = "rx", "tx", "rxu", "txu";
1269 };
1270 };
1271 };
1272
1273 sata: sata@ee300000 {
1274 compatible = "renesas,sata-r8a7795";
1275 reg = <0 0xee300000 0 0x200000>;
1276 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&cpg CPG_MOD 815>;
1278 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1279 resets = <&cpg 815>;
1280 status = "disabled";
1281 };
1282
1283 xhci0: usb@ee000000 {
1284 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
1285 reg = <0 0xee000000 0 0xc00>;
1286 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&cpg CPG_MOD 328>;
1288 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1289 resets = <&cpg 328>;
1290 status = "disabled";
1291 };
1292
1293 usb_dmac0: dma-controller@e65a0000 {
1294 compatible = "renesas,r8a7795-usb-dmac",
1295 "renesas,usb-dmac";
1296 reg = <0 0xe65a0000 0 0x100>;
1297 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
1298 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1299 interrupt-names = "ch0", "ch1";
1300 clocks = <&cpg CPG_MOD 330>;
1301 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1302 resets = <&cpg 330>;
1303 #dma-cells = <1>;
1304 dma-channels = <2>;
1305 };
1306
1307 usb_dmac1: dma-controller@e65b0000 {
1308 compatible = "renesas,r8a7795-usb-dmac",
1309 "renesas,usb-dmac";
1310 reg = <0 0xe65b0000 0 0x100>;
1311 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
1312 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1313 interrupt-names = "ch0", "ch1";
1314 clocks = <&cpg CPG_MOD 331>;
1315 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1316 resets = <&cpg 331>;
1317 #dma-cells = <1>;
1318 dma-channels = <2>;
1319 };
1320
1321 sdhi0: sd@ee100000 {
1322 compatible = "renesas,sdhi-r8a7795";
1323 reg = <0 0xee100000 0 0x2000>;
1324 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&cpg CPG_MOD 314>;
1326 max-frequency = <200000000>;
1327 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1328 resets = <&cpg 314>;
1329 status = "disabled";
1330 };
1331
1332 sdhi1: sd@ee120000 {
1333 compatible = "renesas,sdhi-r8a7795";
1334 reg = <0 0xee120000 0 0x2000>;
1335 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&cpg CPG_MOD 313>;
1337 max-frequency = <200000000>;
1338 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1339 resets = <&cpg 313>;
1340 status = "disabled";
1341 };
1342
1343 sdhi2: sd@ee140000 {
1344 compatible = "renesas,sdhi-r8a7795";
1345 reg = <0 0xee140000 0 0x2000>;
1346 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MOD 312>;
1348 max-frequency = <200000000>;
1349 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1350 resets = <&cpg 312>;
1351 status = "disabled";
1352 };
1353
1354 sdhi3: sd@ee160000 {
1355 compatible = "renesas,sdhi-r8a7795";
1356 reg = <0 0xee160000 0 0x2000>;
1357 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&cpg CPG_MOD 311>;
1359 max-frequency = <200000000>;
1360 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1361 resets = <&cpg 311>;
1362 status = "disabled";
1363 };
1364
1365 usb2_phy0: usb-phy@ee080200 {
1366 compatible = "renesas,usb2-phy-r8a7795",
1367 "renesas,rcar-gen3-usb2-phy";
1368 reg = <0 0xee080200 0 0x700>;
1369 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&cpg CPG_MOD 703>;
1371 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1372 resets = <&cpg 703>;
1373 #phy-cells = <0>;
1374 status = "disabled";
1375 };
1376
1377 usb2_phy1: usb-phy@ee0a0200 {
1378 compatible = "renesas,usb2-phy-r8a7795",
1379 "renesas,rcar-gen3-usb2-phy";
1380 reg = <0 0xee0a0200 0 0x700>;
1381 clocks = <&cpg CPG_MOD 702>;
1382 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1383 resets = <&cpg 702>;
1384 #phy-cells = <0>;
1385 status = "disabled";
1386 };
1387
1388 usb2_phy2: usb-phy@ee0c0200 {
1389 compatible = "renesas,usb2-phy-r8a7795",
1390 "renesas,rcar-gen3-usb2-phy";
1391 reg = <0 0xee0c0200 0 0x700>;
1392 clocks = <&cpg CPG_MOD 701>;
1393 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1394 resets = <&cpg 701>;
1395 #phy-cells = <0>;
1396 status = "disabled";
1397 };
1398
1399 ehci0: usb@ee080100 {
1400 compatible = "generic-ehci";
1401 reg = <0 0xee080100 0 0x100>;
1402 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1403 clocks = <&cpg CPG_MOD 703>;
1404 phys = <&usb2_phy0>;
1405 phy-names = "usb";
1406 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1407 resets = <&cpg 703>;
1408 status = "disabled";
1409 };
1410
1411 ehci1: usb@ee0a0100 {
1412 compatible = "generic-ehci";
1413 reg = <0 0xee0a0100 0 0x100>;
1414 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&cpg CPG_MOD 702>;
1416 phys = <&usb2_phy1>;
1417 phy-names = "usb";
1418 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1419 resets = <&cpg 702>;
1420 status = "disabled";
1421 };
1422
1423 ehci2: usb@ee0c0100 {
1424 compatible = "generic-ehci";
1425 reg = <0 0xee0c0100 0 0x100>;
1426 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1427 clocks = <&cpg CPG_MOD 701>;
1428 phys = <&usb2_phy2>;
1429 phy-names = "usb";
1430 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1431 resets = <&cpg 701>;
1432 status = "disabled";
1433 };
1434
1435 ohci0: usb@ee080000 {
1436 compatible = "generic-ohci";
1437 reg = <0 0xee080000 0 0x100>;
1438 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&cpg CPG_MOD 703>;
1440 phys = <&usb2_phy0>;
1441 phy-names = "usb";
1442 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1443 resets = <&cpg 703>;
1444 status = "disabled";
1445 };
1446
1447 ohci1: usb@ee0a0000 {
1448 compatible = "generic-ohci";
1449 reg = <0 0xee0a0000 0 0x100>;
1450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&cpg CPG_MOD 702>;
1452 phys = <&usb2_phy1>;
1453 phy-names = "usb";
1454 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1455 resets = <&cpg 702>;
1456 status = "disabled";
1457 };
1458
1459 ohci2: usb@ee0c0000 {
1460 compatible = "generic-ohci";
1461 reg = <0 0xee0c0000 0 0x100>;
1462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&cpg CPG_MOD 701>;
1464 phys = <&usb2_phy2>;
1465 phy-names = "usb";
1466 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1467 resets = <&cpg 701>;
1468 status = "disabled";
1469 };
1470
1471 hsusb: usb@e6590000 {
1472 compatible = "renesas,usbhs-r8a7795",
1473 "renesas,rcar-gen3-usbhs";
1474 reg = <0 0xe6590000 0 0x100>;
1475 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&cpg CPG_MOD 704>;
1477 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
1478 <&usb_dmac1 0>, <&usb_dmac1 1>;
1479 dma-names = "ch0", "ch1", "ch2", "ch3";
1480 renesas,buswait = <11>;
1481 phys = <&usb2_phy0>;
1482 phy-names = "usb";
1483 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1484 resets = <&cpg 704>;
1485 status = "disabled";
1486 };
1487
1488 pciec0: pcie@fe000000 {
1489 compatible = "renesas,pcie-r8a7795",
1490 "renesas,pcie-rcar-gen3";
1491 reg = <0 0xfe000000 0 0x80000>;
1492 #address-cells = <3>;
1493 #size-cells = <2>;
1494 bus-range = <0x00 0xff>;
1495 device_type = "pci";
1496 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1497 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1498 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1499 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1500 /* Map all possible DDR as inbound ranges */
1501 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1502 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1505 #interrupt-cells = <1>;
1506 interrupt-map-mask = <0 0 0 0>;
1507 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1509 clock-names = "pcie", "pcie_bus";
1510 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1511 resets = <&cpg 319>;
1512 status = "disabled";
1513 };
1514
1515 pciec1: pcie@ee800000 {
1516 compatible = "renesas,pcie-r8a7795",
1517 "renesas,pcie-rcar-gen3";
1518 reg = <0 0xee800000 0 0x80000>;
1519 #address-cells = <3>;
1520 #size-cells = <2>;
1521 bus-range = <0x00 0xff>;
1522 device_type = "pci";
1523 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
1524 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
1525 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
1526 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
1527 /* Map all possible DDR as inbound ranges */
1528 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1529 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1532 #interrupt-cells = <1>;
1533 interrupt-map-mask = <0 0 0 0>;
1534 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1535 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
1536 clock-names = "pcie", "pcie_bus";
1537 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1538 resets = <&cpg 318>;
1539 status = "disabled";
1540 };
1541
1542 vspbc: vsp@fe920000 {
1543 compatible = "renesas,vsp2";
1544 reg = <0 0xfe920000 0 0x8000>;
1545 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&cpg CPG_MOD 624>;
1547 power-domains = <&sysc R8A7795_PD_A3VP>;
1548 resets = <&cpg 624>;
1549
1550 renesas,fcp = <&fcpvb1>;
1551 };
1552
1553 fcpvb1: fcp@fe92f000 {
1554 compatible = "renesas,fcpv";
1555 reg = <0 0xfe92f000 0 0x200>;
1556 clocks = <&cpg CPG_MOD 606>;
1557 power-domains = <&sysc R8A7795_PD_A3VP>;
1558 resets = <&cpg 606>;
1559 };
1560
1561 fcpf0: fcp@fe950000 {
1562 compatible = "renesas,fcpf";
1563 reg = <0 0xfe950000 0 0x200>;
1564 clocks = <&cpg CPG_MOD 615>;
1565 power-domains = <&sysc R8A7795_PD_A3VP>;
1566 resets = <&cpg 615>;
1567 };
1568
1569 fcpf1: fcp@fe951000 {
1570 compatible = "renesas,fcpf";
1571 reg = <0 0xfe951000 0 0x200>;
1572 clocks = <&cpg CPG_MOD 614>;
1573 power-domains = <&sysc R8A7795_PD_A3VP>;
1574 resets = <&cpg 614>;
1575 };
1576
1577 vspbd: vsp@fe960000 {
1578 compatible = "renesas,vsp2";
1579 reg = <0 0xfe960000 0 0x8000>;
1580 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1581 clocks = <&cpg CPG_MOD 626>;
1582 power-domains = <&sysc R8A7795_PD_A3VP>;
1583 resets = <&cpg 626>;
1584
1585 renesas,fcp = <&fcpvb0>;
1586 };
1587
1588 fcpvb0: fcp@fe96f000 {
1589 compatible = "renesas,fcpv";
1590 reg = <0 0xfe96f000 0 0x200>;
1591 clocks = <&cpg CPG_MOD 607>;
1592 power-domains = <&sysc R8A7795_PD_A3VP>;
1593 resets = <&cpg 607>;
1594 };
1595
1596 vspi0: vsp@fe9a0000 {
1597 compatible = "renesas,vsp2";
1598 reg = <0 0xfe9a0000 0 0x8000>;
1599 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1600 clocks = <&cpg CPG_MOD 631>;
1601 power-domains = <&sysc R8A7795_PD_A3VP>;
1602 resets = <&cpg 631>;
1603
1604 renesas,fcp = <&fcpvi0>;
1605 };
1606
1607 fcpvi0: fcp@fe9af000 {
1608 compatible = "renesas,fcpv";
1609 reg = <0 0xfe9af000 0 0x200>;
1610 clocks = <&cpg CPG_MOD 611>;
1611 power-domains = <&sysc R8A7795_PD_A3VP>;
1612 resets = <&cpg 611>;
1613 };
1614
1615 vspi1: vsp@fe9b0000 {
1616 compatible = "renesas,vsp2";
1617 reg = <0 0xfe9b0000 0 0x8000>;
1618 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1619 clocks = <&cpg CPG_MOD 630>;
1620 power-domains = <&sysc R8A7795_PD_A3VP>;
1621 resets = <&cpg 630>;
1622
1623 renesas,fcp = <&fcpvi1>;
1624 };
1625
1626 fcpvi1: fcp@fe9bf000 {
1627 compatible = "renesas,fcpv";
1628 reg = <0 0xfe9bf000 0 0x200>;
1629 clocks = <&cpg CPG_MOD 610>;
1630 power-domains = <&sysc R8A7795_PD_A3VP>;
1631 resets = <&cpg 610>;
1632 };
1633
1634 vspd0: vsp@fea20000 {
1635 compatible = "renesas,vsp2";
1636 reg = <0 0xfea20000 0 0x4000>;
1637 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1638 clocks = <&cpg CPG_MOD 623>;
1639 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1640 resets = <&cpg 623>;
1641
1642 renesas,fcp = <&fcpvd0>;
1643 };
1644
1645 fcpvd0: fcp@fea27000 {
1646 compatible = "renesas,fcpv";
1647 reg = <0 0xfea27000 0 0x200>;
1648 clocks = <&cpg CPG_MOD 603>;
1649 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1650 resets = <&cpg 603>;
1651 };
1652
1653 vspd1: vsp@fea28000 {
1654 compatible = "renesas,vsp2";
1655 reg = <0 0xfea28000 0 0x4000>;
1656 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1657 clocks = <&cpg CPG_MOD 622>;
1658 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1659 resets = <&cpg 622>;
1660
1661 renesas,fcp = <&fcpvd1>;
1662 };
1663
1664 fcpvd1: fcp@fea2f000 {
1665 compatible = "renesas,fcpv";
1666 reg = <0 0xfea2f000 0 0x200>;
1667 clocks = <&cpg CPG_MOD 602>;
1668 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1669 resets = <&cpg 602>;
1670 };
1671
1672 vspd2: vsp@fea30000 {
1673 compatible = "renesas,vsp2";
1674 reg = <0 0xfea30000 0 0x4000>;
1675 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1676 clocks = <&cpg CPG_MOD 621>;
1677 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1678 resets = <&cpg 621>;
1679
1680 renesas,fcp = <&fcpvd2>;
1681 };
1682
1683 fcpvd2: fcp@fea37000 {
1684 compatible = "renesas,fcpv";
1685 reg = <0 0xfea37000 0 0x200>;
1686 clocks = <&cpg CPG_MOD 601>;
1687 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1688 resets = <&cpg 601>;
1689 };
1690
1691 fdp1@fe940000 {
1692 compatible = "renesas,fdp1";
1693 reg = <0 0xfe940000 0 0x2400>;
1694 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1695 clocks = <&cpg CPG_MOD 119>;
1696 power-domains = <&sysc R8A7795_PD_A3VP>;
1697 resets = <&cpg 119>;
1698 renesas,fcp = <&fcpf0>;
1699 };
1700
1701 fdp1@fe944000 {
1702 compatible = "renesas,fdp1";
1703 reg = <0 0xfe944000 0 0x2400>;
1704 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1705 clocks = <&cpg CPG_MOD 118>;
1706 power-domains = <&sysc R8A7795_PD_A3VP>;
1707 resets = <&cpg 118>;
1708 renesas,fcp = <&fcpf1>;
1709 };
1710
1711 hdmi0: hdmi0@fead0000 {
1712 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
1713 reg = <0 0xfead0000 0 0x10000>;
1714 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
1715 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
1716 clock-names = "iahb", "isfr";
1717 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1718 resets = <&cpg 729>;
1719 status = "disabled";
1720
1721 ports {
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1724 port@0 {
1725 reg = <0>;
1726 dw_hdmi0_in: endpoint {
1727 remote-endpoint = <&du_out_hdmi0>;
1728 };
1729 };
1730 port@1 {
1731 reg = <1>;
1732 };
1733 };
1734 };
1735
1736 hdmi1: hdmi1@feae0000 {
1737 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
1738 reg = <0 0xfeae0000 0 0x10000>;
1739 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
1740 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
1741 clock-names = "iahb", "isfr";
1742 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1743 resets = <&cpg 728>;
1744 status = "disabled";
1745
1746 ports {
1747 #address-cells = <1>;
1748 #size-cells = <0>;
1749 port@0 {
1750 reg = <0>;
1751 dw_hdmi1_in: endpoint {
1752 remote-endpoint = <&du_out_hdmi1>;
1753 };
1754 };
1755 port@1 {
1756 reg = <1>;
1757 };
1758 };
1759 };
1760
1761 du: display@feb00000 {
1762 reg = <0 0xfeb00000 0 0x80000>,
1763 <0 0xfeb90000 0 0x14>;
1764 reg-names = "du", "lvds.0";
1765 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
1769 clocks = <&cpg CPG_MOD 724>,
1770 <&cpg CPG_MOD 723>,
1771 <&cpg CPG_MOD 722>,
1772 <&cpg CPG_MOD 721>,
1773 <&cpg CPG_MOD 727>;
1774 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
1775 status = "disabled";
1776
1777 ports {
1778 #address-cells = <1>;
1779 #size-cells = <0>;
1780
1781 port@0 {
1782 reg = <0>;
1783 du_out_rgb: endpoint {
1784 };
1785 };
1786 port@1 {
1787 reg = <1>;
1788 du_out_hdmi0: endpoint {
1789 remote-endpoint = <&dw_hdmi0_in>;
1790 };
1791 };
1792 port@2 {
1793 reg = <2>;
1794 du_out_hdmi1: endpoint {
1795 remote-endpoint = <&dw_hdmi1_in>;
1796 };
1797 };
1798 port@3 {
1799 reg = <3>;
1800 du_out_lvds0: endpoint {
1801 };
1802 };
1803 };
1804 };
1805
1806 tsc: thermal@e6198000 {
1807 compatible = "renesas,r8a7795-thermal";
1808 reg = <0 0xe6198000 0 0x68>,
1809 <0 0xe61a0000 0 0x5c>,
1810 <0 0xe61a8000 0 0x5c>;
1811 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1814 clocks = <&cpg CPG_MOD 522>;
1815 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1816 resets = <&cpg 522>;
1817 #thermal-sensor-cells = <1>;
1818 status = "okay";
1819 };
1820
1821 thermal-zones {
1822 sensor_thermal1: sensor-thermal1 {
1823 polling-delay-passive = <250>;
1824 polling-delay = <1000>;
1825 thermal-sensors = <&tsc 0>;
1826
1827 trips {
1828 sensor1_crit: sensor1-crit {
1829 temperature = <120000>;
1830 hysteresis = <2000>;
1831 type = "critical";
1832 };
1833 };
1834 };
1835
1836 sensor_thermal2: sensor-thermal2 {
1837 polling-delay-passive = <250>;
1838 polling-delay = <1000>;
1839 thermal-sensors = <&tsc 1>;
1840
1841 trips {
1842 sensor2_crit: sensor2-crit {
1843 temperature = <120000>;
1844 hysteresis = <2000>;
1845 type = "critical";
1846 };
1847 };
1848 };
1849
1850 sensor_thermal3: sensor-thermal3 {
1851 polling-delay-passive = <250>;
1852 polling-delay = <1000>;
1853 thermal-sensors = <&tsc 2>;
1854
1855 trips {
1856 sensor3_crit: sensor3-crit {
1857 temperature = <120000>;
1858 hysteresis = <2000>;
1859 type = "critical";
1860 };
1861 };
1862 };
1863 };
1864 };
1865 };
"Das U-Boot" Source Tree