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ARM: dts: rmobile: Factor out U-Boot extras
[people/ms/u-boot.git] / arch / arm / dts / r8a7796.dtsi
1 /*
2 * Device Tree Source for the r8a7796 SoC
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a7796-sysc.h>
12
13 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
14
15 / {
16 compatible = "renesas,r8a7796";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
29 };
30
31 psci {
32 compatible = "arm,psci-1.0", "arm,psci-0.2";
33 method = "smc";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 a57_0: cpu@0 {
41 compatible = "arm,cortex-a57", "arm,armv8";
42 reg = <0x0>;
43 device_type = "cpu";
44 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
45 next-level-cache = <&L2_CA57>;
46 enable-method = "psci";
47 };
48
49 a57_1: cpu@1 {
50 compatible = "arm,cortex-a57","arm,armv8";
51 reg = <0x1>;
52 device_type = "cpu";
53 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
54 next-level-cache = <&L2_CA57>;
55 enable-method = "psci";
56 };
57
58 a53_0: cpu@100 {
59 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <0x100>;
61 device_type = "cpu";
62 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
63 next-level-cache = <&L2_CA53>;
64 enable-method = "psci";
65 };
66
67 a53_1: cpu@101 {
68 compatible = "arm,cortex-a53","arm,armv8";
69 reg = <0x101>;
70 device_type = "cpu";
71 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
72 next-level-cache = <&L2_CA53>;
73 enable-method = "psci";
74 };
75
76 a53_2: cpu@102 {
77 compatible = "arm,cortex-a53","arm,armv8";
78 reg = <0x102>;
79 device_type = "cpu";
80 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
81 next-level-cache = <&L2_CA53>;
82 enable-method = "psci";
83 };
84
85 a53_3: cpu@103 {
86 compatible = "arm,cortex-a53","arm,armv8";
87 reg = <0x103>;
88 device_type = "cpu";
89 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
90 next-level-cache = <&L2_CA53>;
91 enable-method = "psci";
92 };
93
94 L2_CA57: cache-controller-0 {
95 compatible = "cache";
96 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
97 cache-unified;
98 cache-level = <2>;
99 };
100
101 L2_CA53: cache-controller-1 {
102 compatible = "cache";
103 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
104 cache-unified;
105 cache-level = <2>;
106 };
107 };
108
109 extal_clk: extal {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 /* This value must be overridden by the board */
113 clock-frequency = <0>;
114 };
115
116 extalr_clk: extalr {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 /* This value must be overridden by the board */
120 clock-frequency = <0>;
121 };
122
123 /*
124 * The external audio clocks are configured as 0 Hz fixed frequency
125 * clocks by default.
126 * Boards that provide audio clocks should override them.
127 */
128 audio_clk_a: audio_clk_a {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <0>;
132 };
133
134 audio_clk_b: audio_clk_b {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <0>;
138 };
139
140 audio_clk_c: audio_clk_c {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <0>;
144 };
145
146 /* External CAN clock - to be overridden by boards that provide it */
147 can_clk: can {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <0>;
151 };
152
153 /* External SCIF clock - to be overridden by boards that provide it */
154 scif_clk: scif {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <0>;
158 };
159
160 /* External PCIe clock - can be overridden by the board */
161 pcie_bus_clk: pcie_bus {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <0>;
165 };
166
167 soc {
168 compatible = "simple-bus";
169 interrupt-parent = <&gic>;
170 #address-cells = <2>;
171 #size-cells = <2>;
172 ranges;
173
174 gic: interrupt-controller@f1010000 {
175 compatible = "arm,gic-400";
176 #interrupt-cells = <3>;
177 #address-cells = <0>;
178 interrupt-controller;
179 reg = <0x0 0xf1010000 0 0x1000>,
180 <0x0 0xf1020000 0 0x20000>,
181 <0x0 0xf1040000 0 0x20000>,
182 <0x0 0xf1060000 0 0x20000>;
183 interrupts = <GIC_PPI 9
184 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
185 clocks = <&cpg CPG_MOD 408>;
186 clock-names = "clk";
187 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
188 resets = <&cpg 408>;
189 };
190
191 timer {
192 compatible = "arm,armv8-timer";
193 interrupts = <GIC_PPI 13
194 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
195 <GIC_PPI 14
196 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11
198 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
199 <GIC_PPI 10
200 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
201 };
202
203 wdt0: watchdog@e6020000 {
204 compatible = "renesas,r8a7796-wdt",
205 "renesas,rcar-gen3-wdt";
206 reg = <0 0xe6020000 0 0x0c>;
207 clocks = <&cpg CPG_MOD 402>;
208 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
209 resets = <&cpg 402>;
210 status = "disabled";
211 };
212
213 gpio0: gpio@e6050000 {
214 compatible = "renesas,gpio-r8a7796",
215 "renesas,gpio-rcar";
216 reg = <0 0xe6050000 0 0x50>;
217 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
218 #gpio-cells = <2>;
219 gpio-controller;
220 gpio-ranges = <&pfc 0 0 16>;
221 #interrupt-cells = <2>;
222 interrupt-controller;
223 clocks = <&cpg CPG_MOD 912>;
224 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
225 resets = <&cpg 912>;
226 };
227
228 gpio1: gpio@e6051000 {
229 compatible = "renesas,gpio-r8a7796",
230 "renesas,gpio-rcar";
231 reg = <0 0xe6051000 0 0x50>;
232 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 32 29>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&cpg CPG_MOD 911>;
239 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
240 resets = <&cpg 911>;
241 };
242
243 gpio2: gpio@e6052000 {
244 compatible = "renesas,gpio-r8a7796",
245 "renesas,gpio-rcar";
246 reg = <0 0xe6052000 0 0x50>;
247 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
248 #gpio-cells = <2>;
249 gpio-controller;
250 gpio-ranges = <&pfc 0 64 15>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
253 clocks = <&cpg CPG_MOD 910>;
254 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
255 resets = <&cpg 910>;
256 };
257
258 gpio3: gpio@e6053000 {
259 compatible = "renesas,gpio-r8a7796",
260 "renesas,gpio-rcar";
261 reg = <0 0xe6053000 0 0x50>;
262 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
263 #gpio-cells = <2>;
264 gpio-controller;
265 gpio-ranges = <&pfc 0 96 16>;
266 #interrupt-cells = <2>;
267 interrupt-controller;
268 clocks = <&cpg CPG_MOD 909>;
269 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
270 resets = <&cpg 909>;
271 };
272
273 gpio4: gpio@e6054000 {
274 compatible = "renesas,gpio-r8a7796",
275 "renesas,gpio-rcar";
276 reg = <0 0xe6054000 0 0x50>;
277 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
278 #gpio-cells = <2>;
279 gpio-controller;
280 gpio-ranges = <&pfc 0 128 18>;
281 #interrupt-cells = <2>;
282 interrupt-controller;
283 clocks = <&cpg CPG_MOD 908>;
284 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
285 resets = <&cpg 908>;
286 };
287
288 gpio5: gpio@e6055000 {
289 compatible = "renesas,gpio-r8a7796",
290 "renesas,gpio-rcar";
291 reg = <0 0xe6055000 0 0x50>;
292 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
293 #gpio-cells = <2>;
294 gpio-controller;
295 gpio-ranges = <&pfc 0 160 26>;
296 #interrupt-cells = <2>;
297 interrupt-controller;
298 clocks = <&cpg CPG_MOD 907>;
299 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
300 resets = <&cpg 907>;
301 };
302
303 gpio6: gpio@e6055400 {
304 compatible = "renesas,gpio-r8a7796",
305 "renesas,gpio-rcar";
306 reg = <0 0xe6055400 0 0x50>;
307 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
308 #gpio-cells = <2>;
309 gpio-controller;
310 gpio-ranges = <&pfc 0 192 32>;
311 #interrupt-cells = <2>;
312 interrupt-controller;
313 clocks = <&cpg CPG_MOD 906>;
314 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
315 resets = <&cpg 906>;
316 };
317
318 gpio7: gpio@e6055800 {
319 compatible = "renesas,gpio-r8a7796",
320 "renesas,gpio-rcar";
321 reg = <0 0xe6055800 0 0x50>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
323 #gpio-cells = <2>;
324 gpio-controller;
325 gpio-ranges = <&pfc 0 224 4>;
326 #interrupt-cells = <2>;
327 interrupt-controller;
328 clocks = <&cpg CPG_MOD 905>;
329 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
330 resets = <&cpg 905>;
331 };
332
333 pfc: pin-controller@e6060000 {
334 compatible = "renesas,pfc-r8a7796";
335 reg = <0 0xe6060000 0 0x50c>;
336 };
337
338 pmu_a57 {
339 compatible = "arm,cortex-a57-pmu";
340 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-affinity = <&a57_0>,
343 <&a57_1>;
344 };
345
346 pmu_a53 {
347 compatible = "arm,cortex-a53-pmu";
348 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
352 interrupt-affinity = <&a53_0>,
353 <&a53_1>,
354 <&a53_2>,
355 <&a53_3>;
356 };
357
358 cpg: clock-controller@e6150000 {
359 compatible = "renesas,r8a7796-cpg-mssr";
360 reg = <0 0xe6150000 0 0x1000>;
361 clocks = <&extal_clk>, <&extalr_clk>;
362 clock-names = "extal", "extalr";
363 #clock-cells = <2>;
364 #power-domain-cells = <0>;
365 #reset-cells = <1>;
366 };
367
368 rst: reset-controller@e6160000 {
369 compatible = "renesas,r8a7796-rst";
370 reg = <0 0xe6160000 0 0x0200>;
371 };
372
373 prr: chipid@fff00044 {
374 compatible = "renesas,prr";
375 reg = <0 0xfff00044 0 4>;
376 };
377
378 sysc: system-controller@e6180000 {
379 compatible = "renesas,r8a7796-sysc";
380 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = <1>;
382 };
383
384 i2c_dvfs: i2c@e60b0000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 compatible = "renesas,iic-r8a7796",
388 "renesas,rcar-gen3-iic",
389 "renesas,rmobile-iic";
390 reg = <0 0xe60b0000 0 0x425>;
391 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cpg CPG_MOD 926>;
393 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
394 resets = <&cpg 926>;
395 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
396 dma-names = "tx", "rx";
397 status = "disabled";
398 };
399
400 pwm0: pwm@e6e30000 {
401 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
402 reg = <0 0xe6e30000 0 8>;
403 #pwm-cells = <2>;
404 clocks = <&cpg CPG_MOD 523>;
405 resets = <&cpg 523>;
406 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
407 status = "disabled";
408 };
409
410 pwm1: pwm@e6e31000 {
411 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
412 reg = <0 0xe6e31000 0 8>;
413 #pwm-cells = <2>;
414 clocks = <&cpg CPG_MOD 523>;
415 resets = <&cpg 523>;
416 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
417 status = "disabled";
418 };
419
420 pwm2: pwm@e6e32000 {
421 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
422 reg = <0 0xe6e32000 0 8>;
423 #pwm-cells = <2>;
424 clocks = <&cpg CPG_MOD 523>;
425 resets = <&cpg 523>;
426 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
427 status = "disabled";
428 };
429
430 pwm3: pwm@e6e33000 {
431 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
432 reg = <0 0xe6e33000 0 8>;
433 #pwm-cells = <2>;
434 clocks = <&cpg CPG_MOD 523>;
435 resets = <&cpg 523>;
436 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
437 status = "disabled";
438 };
439
440 pwm4: pwm@e6e34000 {
441 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
442 reg = <0 0xe6e34000 0 8>;
443 #pwm-cells = <2>;
444 clocks = <&cpg CPG_MOD 523>;
445 resets = <&cpg 523>;
446 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
447 status = "disabled";
448 };
449
450 pwm5: pwm@e6e35000 {
451 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
452 reg = <0 0xe6e35000 0 8>;
453 #pwm-cells = <2>;
454 clocks = <&cpg CPG_MOD 523>;
455 resets = <&cpg 523>;
456 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
457 status = "disabled";
458 };
459
460 pwm6: pwm@e6e36000 {
461 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
462 reg = <0 0xe6e36000 0 8>;
463 #pwm-cells = <2>;
464 clocks = <&cpg CPG_MOD 523>;
465 resets = <&cpg 523>;
466 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
467 status = "disabled";
468 };
469
470 i2c0: i2c@e6500000 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,i2c-r8a7796",
474 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6500000 0 0x40>;
476 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 931>;
478 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
479 resets = <&cpg 931>;
480 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
481 <&dmac2 0x91>, <&dmac2 0x90>;
482 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay-ns = <110>;
484 status = "disabled";
485 };
486
487 i2c1: i2c@e6508000 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "renesas,i2c-r8a7796",
491 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6508000 0 0x40>;
493 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 930>;
495 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
496 resets = <&cpg 930>;
497 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
498 <&dmac2 0x93>, <&dmac2 0x92>;
499 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c2: i2c@e6510000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a7796",
508 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe6510000 0 0x40>;
510 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 929>;
512 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
513 resets = <&cpg 929>;
514 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
515 <&dmac2 0x95>, <&dmac2 0x94>;
516 dma-names = "tx", "rx", "tx", "rx";
517 i2c-scl-internal-delay-ns = <6>;
518 status = "disabled";
519 };
520
521 i2c3: i2c@e66d0000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "renesas,i2c-r8a7796",
525 "renesas,rcar-gen3-i2c";
526 reg = <0 0xe66d0000 0 0x40>;
527 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cpg CPG_MOD 928>;
529 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
530 resets = <&cpg 928>;
531 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
532 dma-names = "tx", "rx";
533 i2c-scl-internal-delay-ns = <110>;
534 status = "disabled";
535 };
536
537 i2c4: i2c@e66d8000 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 compatible = "renesas,i2c-r8a7796",
541 "renesas,rcar-gen3-i2c";
542 reg = <0 0xe66d8000 0 0x40>;
543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cpg CPG_MOD 927>;
545 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
546 resets = <&cpg 927>;
547 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
548 dma-names = "tx", "rx";
549 i2c-scl-internal-delay-ns = <110>;
550 status = "disabled";
551 };
552
553 i2c5: i2c@e66e0000 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "renesas,i2c-r8a7796",
557 "renesas,rcar-gen3-i2c";
558 reg = <0 0xe66e0000 0 0x40>;
559 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cpg CPG_MOD 919>;
561 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
562 resets = <&cpg 919>;
563 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
564 dma-names = "tx", "rx";
565 i2c-scl-internal-delay-ns = <110>;
566 status = "disabled";
567 };
568
569 i2c6: i2c@e66e8000 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "renesas,i2c-r8a7796",
573 "renesas,rcar-gen3-i2c";
574 reg = <0 0xe66e8000 0 0x40>;
575 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cpg CPG_MOD 918>;
577 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
578 resets = <&cpg 918>;
579 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
580 dma-names = "tx", "rx";
581 i2c-scl-internal-delay-ns = <6>;
582 status = "disabled";
583 };
584
585 can0: can@e6c30000 {
586 compatible = "renesas,can-r8a7796",
587 "renesas,rcar-gen3-can";
588 reg = <0 0xe6c30000 0 0x1000>;
589 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 916>,
591 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
592 <&can_clk>;
593 clock-names = "clkp1", "clkp2", "can_clk";
594 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
595 assigned-clock-rates = <40000000>;
596 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
597 resets = <&cpg 916>;
598 status = "disabled";
599 };
600
601 can1: can@e6c38000 {
602 compatible = "renesas,can-r8a7796",
603 "renesas,rcar-gen3-can";
604 reg = <0 0xe6c38000 0 0x1000>;
605 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 915>,
607 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
608 <&can_clk>;
609 clock-names = "clkp1", "clkp2", "can_clk";
610 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
611 assigned-clock-rates = <40000000>;
612 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
613 resets = <&cpg 915>;
614 status = "disabled";
615 };
616
617 canfd: can@e66c0000 {
618 compatible = "renesas,r8a7796-canfd",
619 "renesas,rcar-gen3-canfd";
620 reg = <0 0xe66c0000 0 0x8000>;
621 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&cpg CPG_MOD 914>,
624 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
625 <&can_clk>;
626 clock-names = "fck", "canfd", "can_clk";
627 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
628 assigned-clock-rates = <40000000>;
629 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
630 resets = <&cpg 914>;
631 status = "disabled";
632
633 channel0 {
634 status = "disabled";
635 };
636
637 channel1 {
638 status = "disabled";
639 };
640 };
641
642 drif00: rif@e6f40000 {
643 compatible = "renesas,r8a7796-drif",
644 "renesas,rcar-gen3-drif";
645 reg = <0 0xe6f40000 0 0x64>;
646 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cpg CPG_MOD 515>;
648 clock-names = "fck";
649 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
650 dma-names = "rx", "rx";
651 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
652 resets = <&cpg 515>;
653 renesas,bonding = <&drif01>;
654 status = "disabled";
655 };
656
657 drif01: rif@e6f50000 {
658 compatible = "renesas,r8a7796-drif",
659 "renesas,rcar-gen3-drif";
660 reg = <0 0xe6f50000 0 0x64>;
661 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 514>;
663 clock-names = "fck";
664 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
665 dma-names = "rx", "rx";
666 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
667 resets = <&cpg 514>;
668 renesas,bonding = <&drif00>;
669 status = "disabled";
670 };
671
672 drif10: rif@e6f60000 {
673 compatible = "renesas,r8a7796-drif",
674 "renesas,rcar-gen3-drif";
675 reg = <0 0xe6f60000 0 0x64>;
676 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cpg CPG_MOD 513>;
678 clock-names = "fck";
679 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
680 dma-names = "rx", "rx";
681 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
682 resets = <&cpg 513>;
683 renesas,bonding = <&drif11>;
684 status = "disabled";
685 };
686
687 drif11: rif@e6f70000 {
688 compatible = "renesas,r8a7796-drif",
689 "renesas,rcar-gen3-drif";
690 reg = <0 0xe6f70000 0 0x64>;
691 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cpg CPG_MOD 512>;
693 clock-names = "fck";
694 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
695 dma-names = "rx", "rx";
696 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
697 resets = <&cpg 512>;
698 renesas,bonding = <&drif10>;
699 status = "disabled";
700 };
701
702 drif20: rif@e6f80000 {
703 compatible = "renesas,r8a7796-drif",
704 "renesas,rcar-gen3-drif";
705 reg = <0 0xe6f80000 0 0x64>;
706 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&cpg CPG_MOD 511>;
708 clock-names = "fck";
709 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
710 dma-names = "rx", "rx";
711 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
712 resets = <&cpg 511>;
713 renesas,bonding = <&drif21>;
714 status = "disabled";
715 };
716
717 drif21: rif@e6f90000 {
718 compatible = "renesas,r8a7796-drif",
719 "renesas,rcar-gen3-drif";
720 reg = <0 0xe6f90000 0 0x64>;
721 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&cpg CPG_MOD 510>;
723 clock-names = "fck";
724 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
725 dma-names = "rx", "rx";
726 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
727 resets = <&cpg 510>;
728 renesas,bonding = <&drif20>;
729 status = "disabled";
730 };
731
732 drif30: rif@e6fa0000 {
733 compatible = "renesas,r8a7796-drif",
734 "renesas,rcar-gen3-drif";
735 reg = <0 0xe6fa0000 0 0x64>;
736 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 509>;
738 clock-names = "fck";
739 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
740 dma-names = "rx", "rx";
741 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
742 resets = <&cpg 509>;
743 renesas,bonding = <&drif31>;
744 status = "disabled";
745 };
746
747 drif31: rif@e6fb0000 {
748 compatible = "renesas,r8a7796-drif",
749 "renesas,rcar-gen3-drif";
750 reg = <0 0xe6fb0000 0 0x64>;
751 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cpg CPG_MOD 508>;
753 clock-names = "fck";
754 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
755 dma-names = "rx", "rx";
756 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
757 resets = <&cpg 508>;
758 renesas,bonding = <&drif30>;
759 status = "disabled";
760 };
761
762 avb: ethernet@e6800000 {
763 compatible = "renesas,etheravb-r8a7796",
764 "renesas,etheravb-rcar-gen3";
765 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
766 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
791 interrupt-names = "ch0", "ch1", "ch2", "ch3",
792 "ch4", "ch5", "ch6", "ch7",
793 "ch8", "ch9", "ch10", "ch11",
794 "ch12", "ch13", "ch14", "ch15",
795 "ch16", "ch17", "ch18", "ch19",
796 "ch20", "ch21", "ch22", "ch23",
797 "ch24";
798 clocks = <&cpg CPG_MOD 812>;
799 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
800 resets = <&cpg 812>;
801 phy-mode = "rgmii-txid";
802 #address-cells = <1>;
803 #size-cells = <0>;
804 status = "disabled";
805 };
806
807 hscif0: serial@e6540000 {
808 compatible = "renesas,hscif-r8a7796",
809 "renesas,rcar-gen3-hscif",
810 "renesas,hscif";
811 reg = <0 0xe6540000 0 0x60>;
812 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cpg CPG_MOD 520>,
814 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
815 <&scif_clk>;
816 clock-names = "fck", "brg_int", "scif_clk";
817 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
818 <&dmac2 0x31>, <&dmac2 0x30>;
819 dma-names = "tx", "rx", "tx", "rx";
820 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
821 resets = <&cpg 520>;
822 status = "disabled";
823 };
824
825 hscif1: serial@e6550000 {
826 compatible = "renesas,hscif-r8a7796",
827 "renesas,rcar-gen3-hscif",
828 "renesas,hscif";
829 reg = <0 0xe6550000 0 0x60>;
830 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cpg CPG_MOD 519>,
832 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
833 <&scif_clk>;
834 clock-names = "fck", "brg_int", "scif_clk";
835 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
836 <&dmac2 0x33>, <&dmac2 0x32>;
837 dma-names = "tx", "rx", "tx", "rx";
838 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
839 resets = <&cpg 519>;
840 status = "disabled";
841 };
842
843 hscif2: serial@e6560000 {
844 compatible = "renesas,hscif-r8a7796",
845 "renesas,rcar-gen3-hscif",
846 "renesas,hscif";
847 reg = <0 0xe6560000 0 0x60>;
848 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cpg CPG_MOD 518>,
850 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
851 <&scif_clk>;
852 clock-names = "fck", "brg_int", "scif_clk";
853 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
854 <&dmac2 0x35>, <&dmac2 0x34>;
855 dma-names = "tx", "rx", "tx", "rx";
856 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
857 resets = <&cpg 518>;
858 status = "disabled";
859 };
860
861 hscif3: serial@e66a0000 {
862 compatible = "renesas,hscif-r8a7796",
863 "renesas,rcar-gen3-hscif",
864 "renesas,hscif";
865 reg = <0 0xe66a0000 0 0x60>;
866 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&cpg CPG_MOD 517>,
868 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
869 <&scif_clk>;
870 clock-names = "fck", "brg_int", "scif_clk";
871 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
872 dma-names = "tx", "rx";
873 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
874 resets = <&cpg 517>;
875 status = "disabled";
876 };
877
878 hscif4: serial@e66b0000 {
879 compatible = "renesas,hscif-r8a7796",
880 "renesas,rcar-gen3-hscif",
881 "renesas,hscif";
882 reg = <0 0xe66b0000 0 0x60>;
883 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&cpg CPG_MOD 516>,
885 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
886 <&scif_clk>;
887 clock-names = "fck", "brg_int", "scif_clk";
888 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
889 dma-names = "tx", "rx";
890 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
891 resets = <&cpg 516>;
892 status = "disabled";
893 };
894
895 scif0: serial@e6e60000 {
896 compatible = "renesas,scif-r8a7796",
897 "renesas,rcar-gen3-scif", "renesas,scif";
898 reg = <0 0xe6e60000 0 64>;
899 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&cpg CPG_MOD 207>,
901 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
902 <&scif_clk>;
903 clock-names = "fck", "brg_int", "scif_clk";
904 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
905 <&dmac2 0x51>, <&dmac2 0x50>;
906 dma-names = "tx", "rx", "tx", "rx";
907 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
908 resets = <&cpg 207>;
909 status = "disabled";
910 };
911
912 scif1: serial@e6e68000 {
913 compatible = "renesas,scif-r8a7796",
914 "renesas,rcar-gen3-scif", "renesas,scif";
915 reg = <0 0xe6e68000 0 64>;
916 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&cpg CPG_MOD 206>,
918 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
919 <&scif_clk>;
920 clock-names = "fck", "brg_int", "scif_clk";
921 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
922 <&dmac2 0x53>, <&dmac2 0x52>;
923 dma-names = "tx", "rx", "tx", "rx";
924 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
925 resets = <&cpg 206>;
926 status = "disabled";
927 };
928
929 scif2: serial@e6e88000 {
930 compatible = "renesas,scif-r8a7796",
931 "renesas,rcar-gen3-scif", "renesas,scif";
932 reg = <0 0xe6e88000 0 64>;
933 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&cpg CPG_MOD 310>,
935 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
936 <&scif_clk>;
937 clock-names = "fck", "brg_int", "scif_clk";
938 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
939 resets = <&cpg 310>;
940 status = "disabled";
941 };
942
943 scif3: serial@e6c50000 {
944 compatible = "renesas,scif-r8a7796",
945 "renesas,rcar-gen3-scif", "renesas,scif";
946 reg = <0 0xe6c50000 0 64>;
947 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cpg CPG_MOD 204>,
949 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
950 <&scif_clk>;
951 clock-names = "fck", "brg_int", "scif_clk";
952 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
953 dma-names = "tx", "rx";
954 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
955 resets = <&cpg 204>;
956 status = "disabled";
957 };
958
959 scif4: serial@e6c40000 {
960 compatible = "renesas,scif-r8a7796",
961 "renesas,rcar-gen3-scif", "renesas,scif";
962 reg = <0 0xe6c40000 0 64>;
963 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&cpg CPG_MOD 203>,
965 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
966 <&scif_clk>;
967 clock-names = "fck", "brg_int", "scif_clk";
968 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
969 dma-names = "tx", "rx";
970 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
971 resets = <&cpg 203>;
972 status = "disabled";
973 };
974
975 scif5: serial@e6f30000 {
976 compatible = "renesas,scif-r8a7796",
977 "renesas,rcar-gen3-scif", "renesas,scif";
978 reg = <0 0xe6f30000 0 64>;
979 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&cpg CPG_MOD 202>,
981 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
982 <&scif_clk>;
983 clock-names = "fck", "brg_int", "scif_clk";
984 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
985 <&dmac2 0x5b>, <&dmac2 0x5a>;
986 dma-names = "tx", "rx", "tx", "rx";
987 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
988 resets = <&cpg 202>;
989 status = "disabled";
990 };
991
992 msiof0: spi@e6e90000 {
993 compatible = "renesas,msiof-r8a7796",
994 "renesas,rcar-gen3-msiof";
995 reg = <0 0xe6e90000 0 0x0064>;
996 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&cpg CPG_MOD 211>;
998 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
999 <&dmac2 0x41>, <&dmac2 0x40>;
1000 dma-names = "tx", "rx", "tx", "rx";
1001 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1002 resets = <&cpg 211>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 status = "disabled";
1006 };
1007
1008 msiof1: spi@e6ea0000 {
1009 compatible = "renesas,msiof-r8a7796",
1010 "renesas,rcar-gen3-msiof";
1011 reg = <0 0xe6ea0000 0 0x0064>;
1012 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cpg CPG_MOD 210>;
1014 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1015 <&dmac2 0x43>, <&dmac2 0x42>;
1016 dma-names = "tx", "rx", "tx", "rx";
1017 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1018 resets = <&cpg 210>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
1024 msiof2: spi@e6c00000 {
1025 compatible = "renesas,msiof-r8a7796",
1026 "renesas,rcar-gen3-msiof";
1027 reg = <0 0xe6c00000 0 0x0064>;
1028 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&cpg CPG_MOD 209>;
1030 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1031 dma-names = "tx", "rx";
1032 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1033 resets = <&cpg 209>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 status = "disabled";
1037 };
1038
1039 msiof3: spi@e6c10000 {
1040 compatible = "renesas,msiof-r8a7796",
1041 "renesas,rcar-gen3-msiof";
1042 reg = <0 0xe6c10000 0 0x0064>;
1043 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&cpg CPG_MOD 208>;
1045 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1046 dma-names = "tx", "rx";
1047 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1048 resets = <&cpg 208>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 status = "disabled";
1052 };
1053
1054 dmac0: dma-controller@e6700000 {
1055 compatible = "renesas,dmac-r8a7796",
1056 "renesas,rcar-dmac";
1057 reg = <0 0xe6700000 0 0x10000>;
1058 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
1059 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
1060 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
1061 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
1062 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
1063 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
1064 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
1065 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
1066 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
1067 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
1068 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
1069 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
1070 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
1071 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
1072 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
1073 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
1074 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1075 interrupt-names = "error",
1076 "ch0", "ch1", "ch2", "ch3",
1077 "ch4", "ch5", "ch6", "ch7",
1078 "ch8", "ch9", "ch10", "ch11",
1079 "ch12", "ch13", "ch14", "ch15";
1080 clocks = <&cpg CPG_MOD 219>;
1081 clock-names = "fck";
1082 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1083 resets = <&cpg 219>;
1084 #dma-cells = <1>;
1085 dma-channels = <16>;
1086 };
1087
1088 dmac1: dma-controller@e7300000 {
1089 compatible = "renesas,dmac-r8a7796",
1090 "renesas,rcar-dmac";
1091 reg = <0 0xe7300000 0 0x10000>;
1092 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
1093 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
1094 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
1095 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
1096 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
1097 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
1098 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
1099 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
1100 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
1101 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
1102 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
1103 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
1104 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
1105 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
1106 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
1107 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
1108 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1109 interrupt-names = "error",
1110 "ch0", "ch1", "ch2", "ch3",
1111 "ch4", "ch5", "ch6", "ch7",
1112 "ch8", "ch9", "ch10", "ch11",
1113 "ch12", "ch13", "ch14", "ch15";
1114 clocks = <&cpg CPG_MOD 218>;
1115 clock-names = "fck";
1116 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1117 resets = <&cpg 218>;
1118 #dma-cells = <1>;
1119 dma-channels = <16>;
1120 };
1121
1122 dmac2: dma-controller@e7310000 {
1123 compatible = "renesas,dmac-r8a7796",
1124 "renesas,rcar-dmac";
1125 reg = <0 0xe7310000 0 0x10000>;
1126 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
1127 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
1128 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
1129 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
1130 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
1131 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
1132 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
1133 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
1134 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
1135 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
1136 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
1137 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
1138 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
1139 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
1140 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
1141 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
1142 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1143 interrupt-names = "error",
1144 "ch0", "ch1", "ch2", "ch3",
1145 "ch4", "ch5", "ch6", "ch7",
1146 "ch8", "ch9", "ch10", "ch11",
1147 "ch12", "ch13", "ch14", "ch15";
1148 clocks = <&cpg CPG_MOD 217>;
1149 clock-names = "fck";
1150 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1151 resets = <&cpg 217>;
1152 #dma-cells = <1>;
1153 dma-channels = <16>;
1154 };
1155
1156 audma0: dma-controller@ec700000 {
1157 compatible = "renesas,dmac-r8a7796",
1158 "renesas,rcar-dmac";
1159 reg = <0 0xec700000 0 0x10000>;
1160 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1161 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1162 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1163 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1164 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1165 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1166 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1167 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1168 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1169 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1170 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1171 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1172 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1173 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1174 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1175 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1176 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "error",
1178 "ch0", "ch1", "ch2", "ch3",
1179 "ch4", "ch5", "ch6", "ch7",
1180 "ch8", "ch9", "ch10", "ch11",
1181 "ch12", "ch13", "ch14", "ch15";
1182 clocks = <&cpg CPG_MOD 502>;
1183 clock-names = "fck";
1184 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1185 resets = <&cpg 502>;
1186 #dma-cells = <1>;
1187 dma-channels = <16>;
1188 };
1189
1190 audma1: dma-controller@ec720000 {
1191 compatible = "renesas,dmac-r8a7796",
1192 "renesas,rcar-dmac";
1193 reg = <0 0xec720000 0 0x10000>;
1194 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1195 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1196 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1197 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1198 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1199 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1200 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1201 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1202 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1203 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1204 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1205 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1206 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1207 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1208 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1209 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1210 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1211 interrupt-names = "error",
1212 "ch0", "ch1", "ch2", "ch3",
1213 "ch4", "ch5", "ch6", "ch7",
1214 "ch8", "ch9", "ch10", "ch11",
1215 "ch12", "ch13", "ch14", "ch15";
1216 clocks = <&cpg CPG_MOD 501>;
1217 clock-names = "fck";
1218 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1219 resets = <&cpg 501>;
1220 #dma-cells = <1>;
1221 dma-channels = <16>;
1222 };
1223
1224 usb_dmac0: dma-controller@e65a0000 {
1225 compatible = "renesas,r8a7796-usb-dmac",
1226 "renesas,usb-dmac";
1227 reg = <0 0xe65a0000 0 0x100>;
1228 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
1229 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1230 interrupt-names = "ch0", "ch1";
1231 clocks = <&cpg CPG_MOD 330>;
1232 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1233 resets = <&cpg 330>;
1234 #dma-cells = <1>;
1235 dma-channels = <2>;
1236 };
1237
1238 usb_dmac1: dma-controller@e65b0000 {
1239 compatible = "renesas,r8a7796-usb-dmac",
1240 "renesas,usb-dmac";
1241 reg = <0 0xe65b0000 0 0x100>;
1242 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
1243 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1244 interrupt-names = "ch0", "ch1";
1245 clocks = <&cpg CPG_MOD 331>;
1246 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1247 resets = <&cpg 331>;
1248 #dma-cells = <1>;
1249 dma-channels = <2>;
1250 };
1251
1252 hsusb: usb@e6590000 {
1253 compatible = "renesas,usbhs-r8a7796",
1254 "renesas,rcar-gen3-usbhs";
1255 reg = <0 0xe6590000 0 0x100>;
1256 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&cpg CPG_MOD 704>;
1258 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
1259 <&usb_dmac1 0>, <&usb_dmac1 1>;
1260 dma-names = "ch0", "ch1", "ch2", "ch3";
1261 renesas,buswait = <11>;
1262 phys = <&usb2_phy0>;
1263 phy-names = "usb";
1264 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1265 resets = <&cpg 704>;
1266 status = "disabled";
1267 };
1268
1269 xhci0: usb@ee000000 {
1270 compatible = "renesas,xhci-r8a7796",
1271 "renesas,rcar-gen3-xhci";
1272 reg = <0 0xee000000 0 0xc00>;
1273 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1274 clocks = <&cpg CPG_MOD 328>;
1275 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1276 resets = <&cpg 328>;
1277 status = "disabled";
1278 };
1279
1280 ohci0: usb@ee080000 {
1281 compatible = "generic-ohci";
1282 reg = <0 0xee080000 0 0x100>;
1283 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&cpg CPG_MOD 703>;
1285 phys = <&usb2_phy0>;
1286 phy-names = "usb";
1287 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1288 resets = <&cpg 703>;
1289 status = "disabled";
1290 };
1291
1292 ehci0: usb@ee080100 {
1293 compatible = "generic-ehci";
1294 reg = <0 0xee080100 0 0x100>;
1295 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&cpg CPG_MOD 703>;
1297 phys = <&usb2_phy0>;
1298 phy-names = "usb";
1299 companion= <&ohci0>;
1300 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1301 resets = <&cpg 703>;
1302 status = "disabled";
1303 };
1304
1305 usb2_phy0: usb-phy@ee080200 {
1306 compatible = "renesas,usb2-phy-r8a7796",
1307 "renesas,rcar-gen3-usb2-phy";
1308 reg = <0 0xee080200 0 0x700>;
1309 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&cpg CPG_MOD 703>;
1311 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 resets = <&cpg 703>;
1313 #phy-cells = <0>;
1314 status = "disabled";
1315 };
1316
1317 ohci1: usb@ee0a0000 {
1318 compatible = "generic-ohci";
1319 reg = <0 0xee0a0000 0 0x100>;
1320 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cpg CPG_MOD 702>;
1322 phys = <&usb2_phy1>;
1323 phy-names = "usb";
1324 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1325 resets = <&cpg 702>;
1326 status = "disabled";
1327 };
1328
1329 ehci1: usb@ee0a0100 {
1330 compatible = "generic-ehci";
1331 reg = <0 0xee0a0100 0 0x100>;
1332 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1333 clocks = <&cpg CPG_MOD 702>;
1334 phys = <&usb2_phy1>;
1335 phy-names = "usb";
1336 companion= <&ohci1>;
1337 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 702>;
1339 status = "disabled";
1340 };
1341
1342 usb2_phy1: usb-phy@ee0a0200 {
1343 compatible = "renesas,usb2-phy-r8a7796",
1344 "renesas,rcar-gen3-usb2-phy";
1345 reg = <0 0xee0a0200 0 0x700>;
1346 clocks = <&cpg CPG_MOD 702>;
1347 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1348 resets = <&cpg 702>;
1349 #phy-cells = <0>;
1350 status = "disabled";
1351 };
1352
1353 sdhi0: sd@ee100000 {
1354 compatible = "renesas,sdhi-r8a7796";
1355 reg = <0 0xee100000 0 0x2000>;
1356 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cpg CPG_MOD 314>;
1358 max-frequency = <200000000>;
1359 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1360 resets = <&cpg 314>;
1361 status = "disabled";
1362 };
1363
1364 sdhi1: sd@ee120000 {
1365 compatible = "renesas,sdhi-r8a7796";
1366 reg = <0 0xee120000 0 0x2000>;
1367 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&cpg CPG_MOD 313>;
1369 max-frequency = <200000000>;
1370 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1371 resets = <&cpg 313>;
1372 status = "disabled";
1373 };
1374
1375 sdhi2: sd@ee140000 {
1376 compatible = "renesas,sdhi-r8a7796";
1377 reg = <0 0xee140000 0 0x2000>;
1378 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1379 clocks = <&cpg CPG_MOD 312>;
1380 max-frequency = <200000000>;
1381 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1382 resets = <&cpg 312>;
1383 status = "disabled";
1384 };
1385
1386 sdhi3: sd@ee160000 {
1387 compatible = "renesas,sdhi-r8a7796";
1388 reg = <0 0xee160000 0 0x2000>;
1389 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&cpg CPG_MOD 311>;
1391 max-frequency = <200000000>;
1392 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1393 resets = <&cpg 311>;
1394 status = "disabled";
1395 };
1396
1397 tsc: thermal@e6198000 {
1398 compatible = "renesas,r8a7796-thermal";
1399 reg = <0 0xe6198000 0 0x68>,
1400 <0 0xe61a0000 0 0x5c>,
1401 <0 0xe61a8000 0 0x5c>;
1402 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1405 clocks = <&cpg CPG_MOD 522>;
1406 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1407 resets = <&cpg 522>;
1408 #thermal-sensor-cells = <1>;
1409 status = "okay";
1410 };
1411
1412 thermal-zones {
1413 sensor_thermal1: sensor-thermal1 {
1414 polling-delay-passive = <250>;
1415 polling-delay = <1000>;
1416 thermal-sensors = <&tsc 0>;
1417
1418 trips {
1419 sensor1_crit: sensor1-crit {
1420 temperature = <120000>;
1421 hysteresis = <2000>;
1422 type = "critical";
1423 };
1424 };
1425 };
1426
1427 sensor_thermal2: sensor-thermal2 {
1428 polling-delay-passive = <250>;
1429 polling-delay = <1000>;
1430 thermal-sensors = <&tsc 1>;
1431
1432 trips {
1433 sensor2_crit: sensor2-crit {
1434 temperature = <120000>;
1435 hysteresis = <2000>;
1436 type = "critical";
1437 };
1438 };
1439 };
1440
1441 sensor_thermal3: sensor-thermal3 {
1442 polling-delay-passive = <250>;
1443 polling-delay = <1000>;
1444 thermal-sensors = <&tsc 2>;
1445
1446 trips {
1447 sensor3_crit: sensor3-crit {
1448 temperature = <120000>;
1449 hysteresis = <2000>;
1450 type = "critical";
1451 };
1452 };
1453 };
1454 };
1455
1456 rcar_sound: sound@ec500000 {
1457 /*
1458 * #sound-dai-cells is required
1459 *
1460 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1461 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1462 */
1463 /*
1464 * #clock-cells is required for audio_clkout0/1/2/3
1465 *
1466 * clkout : #clock-cells = <0>; <&rcar_sound>;
1467 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1468 */
1469 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1470 reg = <0 0xec500000 0 0x1000>, /* SCU */
1471 <0 0xec5a0000 0 0x100>, /* ADG */
1472 <0 0xec540000 0 0x1000>, /* SSIU */
1473 <0 0xec541000 0 0x280>, /* SSI */
1474 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1475 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1476
1477 clocks = <&cpg CPG_MOD 1005>,
1478 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1479 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1480 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1481 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1482 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1483 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1484 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1485 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1486 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1487 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1488 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1489 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1490 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1491 <&audio_clk_a>, <&audio_clk_b>,
1492 <&audio_clk_c>,
1493 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1494 clock-names = "ssi-all",
1495 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1496 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1497 "ssi.1", "ssi.0",
1498 "src.9", "src.8", "src.7", "src.6",
1499 "src.5", "src.4", "src.3", "src.2",
1500 "src.1", "src.0",
1501 "mix.1", "mix.0",
1502 "ctu.1", "ctu.0",
1503 "dvc.0", "dvc.1",
1504 "clk_a", "clk_b", "clk_c", "clk_i";
1505 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1506 resets = <&cpg 1005>,
1507 <&cpg 1006>, <&cpg 1007>,
1508 <&cpg 1008>, <&cpg 1009>,
1509 <&cpg 1010>, <&cpg 1011>,
1510 <&cpg 1012>, <&cpg 1013>,
1511 <&cpg 1014>, <&cpg 1015>;
1512 reset-names = "ssi-all",
1513 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1", "ssi.0";
1516 status = "disabled";
1517
1518 rcar_sound,dvc {
1519 dvc0: dvc-0 {
1520 dmas = <&audma1 0xbc>;
1521 dma-names = "tx";
1522 };
1523 dvc1: dvc-1 {
1524 dmas = <&audma1 0xbe>;
1525 dma-names = "tx";
1526 };
1527 };
1528
1529 rcar_sound,mix {
1530 mix0: mix-0 { };
1531 mix1: mix-1 { };
1532 };
1533
1534 rcar_sound,ctu {
1535 ctu00: ctu-0 { };
1536 ctu01: ctu-1 { };
1537 ctu02: ctu-2 { };
1538 ctu03: ctu-3 { };
1539 ctu10: ctu-4 { };
1540 ctu11: ctu-5 { };
1541 ctu12: ctu-6 { };
1542 ctu13: ctu-7 { };
1543 };
1544
1545 rcar_sound,src {
1546 src0: src-0 {
1547 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1548 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1549 dma-names = "rx", "tx";
1550 };
1551 src1: src-1 {
1552 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1553 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1554 dma-names = "rx", "tx";
1555 };
1556 src2: src-2 {
1557 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1558 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1559 dma-names = "rx", "tx";
1560 };
1561 src3: src-3 {
1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1564 dma-names = "rx", "tx";
1565 };
1566 src4: src-4 {
1567 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1568 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1569 dma-names = "rx", "tx";
1570 };
1571 src5: src-5 {
1572 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1573 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1574 dma-names = "rx", "tx";
1575 };
1576 src6: src-6 {
1577 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1578 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1579 dma-names = "rx", "tx";
1580 };
1581 src7: src-7 {
1582 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1583 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1584 dma-names = "rx", "tx";
1585 };
1586 src8: src-8 {
1587 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1588 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1589 dma-names = "rx", "tx";
1590 };
1591 src9: src-9 {
1592 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1593 dmas = <&audma0 0x97>, <&audma1 0xba>;
1594 dma-names = "rx", "tx";
1595 };
1596 };
1597
1598 rcar_sound,ssi {
1599 ssi0: ssi-0 {
1600 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1602 dma-names = "rx", "tx", "rxu", "txu";
1603 };
1604 ssi1: ssi-1 {
1605 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1607 dma-names = "rx", "tx", "rxu", "txu";
1608 };
1609 ssi2: ssi-2 {
1610 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1612 dma-names = "rx", "tx", "rxu", "txu";
1613 };
1614 ssi3: ssi-3 {
1615 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1616 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1617 dma-names = "rx", "tx", "rxu", "txu";
1618 };
1619 ssi4: ssi-4 {
1620 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1621 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1622 dma-names = "rx", "tx", "rxu", "txu";
1623 };
1624 ssi5: ssi-5 {
1625 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1626 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1627 dma-names = "rx", "tx", "rxu", "txu";
1628 };
1629 ssi6: ssi-6 {
1630 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1632 dma-names = "rx", "tx", "rxu", "txu";
1633 };
1634 ssi7: ssi-7 {
1635 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1636 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1637 dma-names = "rx", "tx", "rxu", "txu";
1638 };
1639 ssi8: ssi-8 {
1640 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1641 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1642 dma-names = "rx", "tx", "rxu", "txu";
1643 };
1644 ssi9: ssi-9 {
1645 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1646 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1647 dma-names = "rx", "tx", "rxu", "txu";
1648 };
1649 };
1650 };
1651
1652 pciec0: pcie@fe000000 {
1653 /* placeholder */
1654 };
1655
1656 pciec1: pcie@ee800000 {
1657 /* placeholder */
1658 };
1659
1660 fcpf0: fcp@fe950000 {
1661 compatible = "renesas,fcpf";
1662 reg = <0 0xfe950000 0 0x200>;
1663 clocks = <&cpg CPG_MOD 615>;
1664 power-domains = <&sysc R8A7796_PD_A3VC>;
1665 resets = <&cpg 615>;
1666 };
1667
1668 vspb: vsp@fe960000 {
1669 compatible = "renesas,vsp2";
1670 reg = <0 0xfe960000 0 0x8000>;
1671 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1672 clocks = <&cpg CPG_MOD 626>;
1673 power-domains = <&sysc R8A7796_PD_A3VC>;
1674 resets = <&cpg 626>;
1675
1676 renesas,fcp = <&fcpvb0>;
1677 };
1678
1679 fcpvb0: fcp@fe96f000 {
1680 compatible = "renesas,fcpv";
1681 reg = <0 0xfe96f000 0 0x200>;
1682 clocks = <&cpg CPG_MOD 607>;
1683 power-domains = <&sysc R8A7796_PD_A3VC>;
1684 resets = <&cpg 607>;
1685 };
1686
1687 vspi0: vsp@fe9a0000 {
1688 compatible = "renesas,vsp2";
1689 reg = <0 0xfe9a0000 0 0x8000>;
1690 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1691 clocks = <&cpg CPG_MOD 631>;
1692 power-domains = <&sysc R8A7796_PD_A3VC>;
1693 resets = <&cpg 631>;
1694
1695 renesas,fcp = <&fcpvi0>;
1696 };
1697
1698 fcpvi0: fcp@fe9af000 {
1699 compatible = "renesas,fcpv";
1700 reg = <0 0xfe9af000 0 0x200>;
1701 clocks = <&cpg CPG_MOD 611>;
1702 power-domains = <&sysc R8A7796_PD_A3VC>;
1703 resets = <&cpg 611>;
1704 };
1705
1706 vspd0: vsp@fea20000 {
1707 compatible = "renesas,vsp2";
1708 reg = <0 0xfea20000 0 0x4000>;
1709 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1710 clocks = <&cpg CPG_MOD 623>;
1711 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1712 resets = <&cpg 623>;
1713
1714 renesas,fcp = <&fcpvd0>;
1715 };
1716
1717 fcpvd0: fcp@fea27000 {
1718 compatible = "renesas,fcpv";
1719 reg = <0 0xfea27000 0 0x200>;
1720 clocks = <&cpg CPG_MOD 603>;
1721 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1722 resets = <&cpg 603>;
1723 };
1724
1725 vspd1: vsp@fea28000 {
1726 compatible = "renesas,vsp2";
1727 reg = <0 0xfea28000 0 0x4000>;
1728 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1729 clocks = <&cpg CPG_MOD 622>;
1730 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1731 resets = <&cpg 622>;
1732
1733 renesas,fcp = <&fcpvd1>;
1734 };
1735
1736 fcpvd1: fcp@fea2f000 {
1737 compatible = "renesas,fcpv";
1738 reg = <0 0xfea2f000 0 0x200>;
1739 clocks = <&cpg CPG_MOD 602>;
1740 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1741 resets = <&cpg 602>;
1742 };
1743
1744 vspd2: vsp@fea30000 {
1745 compatible = "renesas,vsp2";
1746 reg = <0 0xfea30000 0 0x4000>;
1747 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1748 clocks = <&cpg CPG_MOD 621>;
1749 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1750 resets = <&cpg 621>;
1751
1752 renesas,fcp = <&fcpvd2>;
1753 };
1754
1755 fcpvd2: fcp@fea37000 {
1756 compatible = "renesas,fcpv";
1757 reg = <0 0xfea37000 0 0x200>;
1758 clocks = <&cpg CPG_MOD 601>;
1759 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1760 resets = <&cpg 601>;
1761 };
1762
1763 hdmi0: hdmi@fead0000 {
1764 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
1765 reg = <0 0xfead0000 0 0x10000>;
1766 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
1768 clock-names = "iahb", "isfr";
1769 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1770 resets = <&cpg 729>;
1771 status = "disabled";
1772
1773 ports {
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1776 port@0 {
1777 reg = <0>;
1778 dw_hdmi0_in: endpoint {
1779 remote-endpoint = <&du_out_hdmi0>;
1780 };
1781 };
1782 port@1 {
1783 reg = <1>;
1784 };
1785 };
1786 };
1787
1788 du: display@feb00000 {
1789 compatible = "renesas,du-r8a7796";
1790 reg = <0 0xfeb00000 0 0x70000>,
1791 <0 0xfeb90000 0 0x14>;
1792 reg-names = "du", "lvds.0";
1793 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1796 clocks = <&cpg CPG_MOD 724>,
1797 <&cpg CPG_MOD 723>,
1798 <&cpg CPG_MOD 722>,
1799 <&cpg CPG_MOD 727>;
1800 clock-names = "du.0", "du.1", "du.2", "lvds.0";
1801 status = "disabled";
1802
1803 vsps = <&vspd0 &vspd1 &vspd2>;
1804
1805 ports {
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1808
1809 port@0 {
1810 reg = <0>;
1811 du_out_rgb: endpoint {
1812 };
1813 };
1814 port@1 {
1815 reg = <1>;
1816 du_out_hdmi0: endpoint {
1817 remote-endpoint = <&dw_hdmi0_in>;
1818 };
1819 };
1820 port@2 {
1821 reg = <2>;
1822 du_out_lvds0: endpoint {
1823 };
1824 };
1825 };
1826 };
1827
1828 imr-lx4@fe860000 {
1829 compatible = "renesas,r8a7796-imr-lx4",
1830 "renesas,imr-lx4";
1831 reg = <0 0xfe860000 0 0x2000>;
1832 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MOD 823>;
1834 power-domains = <&sysc R8A7796_PD_A3VC>;
1835 resets = <&cpg 823>;
1836 };
1837
1838 imr-lx4@fe870000 {
1839 compatible = "renesas,r8a7796-imr-lx4",
1840 "renesas,imr-lx4";
1841 reg = <0 0xfe870000 0 0x2000>;
1842 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
1843 clocks = <&cpg CPG_MOD 822>;
1844 power-domains = <&sysc R8A7796_PD_A3VC>;
1845 resets = <&cpg 822>;
1846 };
1847 };
1848 };
"Das U-Boot" Source Tree