arch/arm/dts/r8a77970.dtsi

   1 /*
   2  * Device Tree Source for the r8a77970 SoC
   3  *
   4  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Cogent Embedded, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  13
  14 / {
  15         compatible = "renesas,r8a77970";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         psci {
  20                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  21                 method = "smc";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 a53_0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         reg = <0>;
  32                         clocks = <&cpg CPG_CORE 0>;
  33                         power-domains = <&sysc 5>;
  34                         next-level-cache = <&L2_CA53>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 L2_CA53: cache-controller {
  39                         compatible = "cache";
  40                         power-domains = <&sysc 21>;
  41                         cache-unified;
  42                         cache-level = <2>;
  43                 };
  44         };
  45
  46         extal_clk: extal {
  47                 compatible = "fixed-clock";
  48                 #clock-cells = <0>;
  49                 /* This value must be overridden by the board */
  50                 clock-frequency = <0>;
  51                 u-boot,dm-pre-reloc;
  52         };
  53
  54         extalr_clk: extalr {
  55                 compatible = "fixed-clock";
  56                 #clock-cells = <0>;
  57                 /* This value must be overridden by the board */
  58                 clock-frequency = <0>;
  59                 u-boot,dm-pre-reloc;
  60         };
  61
  62         /* External SCIF clock - to be overridden by boards that provide it */
  63         scif_clk: scif {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <0>;
  67         };
  68
  69         soc {
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76                 u-boot,dm-pre-reloc;
  77
  78                 gic: interrupt-controller@f1010000 {
  79                         compatible = "arm,gic-400";
  80                         #interrupt-cells = <3>;
  81                         #address-cells = <0>;
  82                         interrupt-controller;
  83                         reg = <0 0xf1010000 0 0x1000>,
  84                               <0 0xf1020000 0 0x20000>,
  85                               <0 0xf1040000 0 0x20000>,
  86                               <0 0xf1060000 0 0x20000>;
  87                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  88                                       IRQ_TYPE_LEVEL_HIGH)>;
  89                         clocks = <&cpg CPG_MOD 408>;
  90                         clock-names = "clk";
  91                         power-domains = <&sysc 32>;
  92                         resets = <&cpg 408>;
  93                 };
  94
  95                 timer {
  96                         compatible = "arm,armv8-timer";
  97                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
  98                                                   IRQ_TYPE_LEVEL_LOW)>,
  99                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
 100                                                   IRQ_TYPE_LEVEL_LOW)>,
 101                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
 102                                                   IRQ_TYPE_LEVEL_LOW)>,
 103                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 104                                                   IRQ_TYPE_LEVEL_LOW)>;
 105                 };
 106
 107                 cpg: clock-controller@e6150000 {
 108                         compatible = "renesas,r8a77970-cpg-mssr";
 109                         reg = <0 0xe6150000 0 0x1000>;
 110                         clocks = <&extal_clk>, <&extalr_clk>;
 111                         clock-names = "extal", "extalr";
 112                         #clock-cells = <2>;
 113                         #power-domain-cells = <0>;
 114                         #reset-cells = <1>;
 115                         u-boot,dm-pre-reloc;
 116                 };
 117
 118                 rst: reset-controller@e6160000 {
 119                         compatible = "renesas,r8a77970-rst";
 120                         reg = <0 0xe6160000 0 0x200>;
 121                 };
 122
 123                 sysc: system-controller@e6180000 {
 124                         compatible = "renesas,r8a77970-sysc";
 125                         reg = <0 0xe6180000 0 0x440>;
 126                         #power-domain-cells = <1>;
 127                 };
 128
 129                 pfc: pfc@e6060000 {
 130                         compatible = "renesas,pfc-r8a77970";
 131                         reg = <0 0xe6060000 0 0x50c>;
 132                 };
 133
 134                 intc_ex: interrupt-controller@e61c0000 {
 135                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 136                         #interrupt-cells = <2>;
 137                         interrupt-controller;
 138                         reg = <0 0xe61c0000 0 0x200>;
 139                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 140                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 141                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 142                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 143                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 144                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 145                         clocks = <&cpg CPG_MOD 407>;
 146                         power-domains = <&sysc 32>;
 147                         resets = <&cpg 407>;
 148                 };
 149
 150                 prr: chipid@fff00044 {
 151                         compatible = "renesas,prr";
 152                         reg = <0 0xfff00044 0 4>;
 153                         u-boot,dm-pre-reloc;
 154                 };
 155
 156                 dmac1: dma-controller@e7300000 {
 157                         compatible = "renesas,dmac-r8a77970",
 158                                      "renesas,rcar-dmac";
 159                         reg = <0 0xe7300000 0 0x10000>;
 160                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 161                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 162                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 163                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 164                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 165                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 166                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 167                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 168                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 169                         interrupt-names = "error",
 170                                           "ch0", "ch1", "ch2", "ch3",
 171                                           "ch4", "ch5", "ch6", "ch7";
 172                         clocks = <&cpg CPG_MOD 218>;
 173                         clock-names = "fck";
 174                         power-domains = <&sysc 32>;
 175                         resets = <&cpg 218>;
 176                         #dma-cells = <1>;
 177                         dma-channels = <8>;
 178                 };
 179
 180                 dmac2: dma-controller@e7310000 {
 181                         compatible = "renesas,dmac-r8a77970",
 182                                      "renesas,rcar-dmac";
 183                         reg = <0 0xe7310000 0 0x10000>;
 184                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 185                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 186                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 187                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 188                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 189                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 190                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 191                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 192                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 193                         interrupt-names = "error",
 194                                           "ch0", "ch1", "ch2", "ch3",
 195                                           "ch4", "ch5", "ch6", "ch7";
 196                         clocks = <&cpg CPG_MOD 217>;
 197                         clock-names = "fck";
 198                         power-domains = <&sysc 32>;
 199                         resets = <&cpg 217>;
 200                         #dma-cells = <1>;
 201                         dma-channels = <8>;
 202                 };
 203
 204                 hscif0: serial@e6540000 {
 205                         compatible = "renesas,hscif-r8a77970",
 206                                      "renesas,rcar-gen3-hscif",
 207                                      "renesas,hscif";
 208                         reg = <0 0xe6540000 0 96>;
 209                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&cpg CPG_MOD 520>,
 211                                  <&cpg CPG_CORE 9>,
 212                                  <&scif_clk>;
 213                         clock-names = "fck", "brg_int", "scif_clk";
 214                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 215                                <&dmac2 0x31>, <&dmac2 0x30>;
 216                         dma-names = "tx", "rx", "tx", "rx";
 217                         power-domains = <&sysc 32>;
 218                         resets = <&cpg 520>;
 219                         status = "disabled";
 220                 };
 221
 222                 hscif1: serial@e6550000 {
 223                         compatible = "renesas,hscif-r8a77970",
 224                                      "renesas,rcar-gen3-hscif",
 225                                      "renesas,hscif";
 226                         reg = <0 0xe6550000 0 96>;
 227                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 228                         clocks = <&cpg CPG_MOD 519>,
 229                                  <&cpg CPG_CORE 9>,
 230                                  <&scif_clk>;
 231                         clock-names = "fck", "brg_int", "scif_clk";
 232                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 233                                <&dmac2 0x33>, <&dmac2 0x32>;
 234                         dma-names = "tx", "rx", "tx", "rx";
 235                         power-domains = <&sysc 32>;
 236                         resets = <&cpg 519>;
 237                         status = "disabled";
 238                 };
 239
 240                 hscif2: serial@e6560000 {
 241                         compatible = "renesas,hscif-r8a77970",
 242                                      "renesas,rcar-gen3-hscif",
 243                                      "renesas,hscif";
 244                         reg = <0 0xe6560000 0 96>;
 245                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 246                         clocks = <&cpg CPG_MOD 518>,
 247                                  <&cpg CPG_CORE 9>,
 248                                  <&scif_clk>;
 249                         clock-names = "fck", "brg_int", "scif_clk";
 250                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 251                                <&dmac2 0x35>, <&dmac2 0x34>;
 252                         dma-names = "tx", "rx", "tx", "rx";
 253                         power-domains = <&sysc 32>;
 254                         resets = <&cpg 518>;
 255                         status = "disabled";
 256                 };
 257
 258                 hscif3: serial@e66a0000 {
 259                         compatible = "renesas,hscif-r8a77970",
 260                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 261                         reg = <0 0xe66a0000 0 96>;
 262                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 263                         clocks = <&cpg CPG_MOD 517>,
 264                                  <&cpg CPG_CORE 9>,
 265                                  <&scif_clk>;
 266                         clock-names = "fck", "brg_int", "scif_clk";
 267                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 268                                <&dmac2 0x37>, <&dmac2 0x36>;
 269                         dma-names = "tx", "rx", "tx", "rx";
 270                         power-domains = <&sysc 32>;
 271                         resets = <&cpg 517>;
 272                         status = "disabled";
 273                 };
 274
 275                 scif0: serial@e6e60000 {
 276                         compatible = "renesas,scif-r8a77970",
 277                                      "renesas,rcar-gen3-scif",
 278                                      "renesas,scif";
 279                         reg = <0 0xe6e60000 0 64>;
 280                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&cpg CPG_MOD 207>,
 282                                  <&cpg CPG_CORE 9>,
 283                                  <&scif_clk>;
 284                         clock-names = "fck", "brg_int", "scif_clk";
 285                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 286                                <&dmac2 0x51>, <&dmac2 0x50>;
 287                         dma-names = "tx", "rx", "tx", "rx";
 288                         power-domains = <&sysc 32>;
 289                         resets = <&cpg 207>;
 290                         status = "disabled";
 291                 };
 292
 293                 scif1: serial@e6e68000 {
 294                         compatible = "renesas,scif-r8a77970",
 295                                      "renesas,rcar-gen3-scif",
 296                                      "renesas,scif";
 297                         reg = <0 0xe6e68000 0 64>;
 298                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&cpg CPG_MOD 206>,
 300                                  <&cpg CPG_CORE 9>,
 301                                  <&scif_clk>;
 302                         clock-names = "fck", "brg_int", "scif_clk";
 303                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 304                                <&dmac2 0x53>, <&dmac2 0x52>;
 305                         dma-names = "tx", "rx", "tx", "rx";
 306                         power-domains = <&sysc 32>;
 307                         resets = <&cpg 206>;
 308                         status = "disabled";
 309                 };
 310
 311                 scif3: serial@e6c50000 {
 312                         compatible = "renesas,scif-r8a77970",
 313                                      "renesas,rcar-gen3-scif",
 314                                      "renesas,scif";
 315                         reg = <0 0xe6c50000 0 64>;
 316                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&cpg CPG_MOD 204>,
 318                                  <&cpg CPG_CORE 9>,
 319                                  <&scif_clk>;
 320                         clock-names = "fck", "brg_int", "scif_clk";
 321                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 322                                <&dmac2 0x57>, <&dmac2 0x56>;
 323                         dma-names = "tx", "rx", "tx", "rx";
 324                         power-domains = <&sysc 32>;
 325                         resets = <&cpg 204>;
 326                         status = "disabled";
 327                 };
 328
 329                 scif4: serial@e6c40000 {
 330                         compatible = "renesas,scif-r8a77970",
 331                                      "renesas,rcar-gen3-scif", "renesas,scif";
 332                         reg = <0 0xe6c40000 0 64>;
 333                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&cpg CPG_MOD 203>,
 335                                  <&cpg CPG_CORE 9>,
 336                                  <&scif_clk>;
 337                         clock-names = "fck", "brg_int", "scif_clk";
 338                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 339                                <&dmac2 0x59>, <&dmac2 0x58>;
 340                         dma-names = "tx", "rx", "tx", "rx";
 341                         power-domains = <&sysc 32>;
 342                         resets = <&cpg 203>;
 343                         status = "disabled";
 344                 };
 345
 346                 avb: ethernet@e6800000 {
 347                         compatible = "renesas,etheravb-r8a77970",
 348                                      "renesas,etheravb-rcar-gen3";
 349                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 350                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 367                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 368                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 372                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 373                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 375                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 376                                           "ch4", "ch5", "ch6", "ch7",
 377                                           "ch8", "ch9", "ch10", "ch11",
 378                                           "ch12", "ch13", "ch14", "ch15",
 379                                           "ch16", "ch17", "ch18", "ch19",
 380                                           "ch20", "ch21", "ch22", "ch23",
 381                                           "ch24";
 382                         clocks = <&cpg CPG_MOD 812>;
 383                         power-domains = <&sysc 32>;
 384                         resets = <&cpg 812>;
 385                         phy-mode = "rgmii-id";
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                 };
 389         };
 390 };