arch/arm/dts/rk3229-evb.dts

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+ X11
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "rk322x.dtsi"
  10
  11 / {
  12         model = "Rockchip RK3229 Evaluation board";
  13         compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
  14
  15         chosen {
  16                 stdout-path = &uart2;
  17         };
  18
  19         memory@60000000 {
  20                 device_type = "memory";
  21                 reg = <0x60000000 0x40000000>;
  22         };
  23
  24         ext_gmac: ext_gmac {
  25                 compatible = "fixed-clock";
  26                 clock-frequency = <125000000>;
  27                 clock-output-names = "ext_gmac";
  28                 #clock-cells = <0>;
  29         };
  30
  31         vcc_phy: vcc-phy-regulator {
  32                 compatible = "regulator-fixed";
  33                 enable-active-high;
  34                 regulator-name = "vcc_phy";
  35                 regulator-min-microvolt = <1800000>;
  36                 regulator-max-microvolt = <1800000>;
  37                 regulator-always-on;
  38                 regulator-boot-on;
  39         };
  40 };
  41
  42 &dmc {
  43         rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
  44         rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
  45                 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
  46                 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
  47                 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
  48                 0x0 0x924>;
  49         rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
  50         rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
  51                 0 300 3 0 120>;
  52 };
  53
  54 &gmac {
  55         assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
  56         assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
  57         clock_in_out = "input";
  58         phy-supply = <&vcc_phy>;
  59         phy-mode = "rgmii";
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&rgmii_pins>;
  62         snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
  63         snps,reset-active-low;
  64         snps,reset-delays-us = <0 10000 1000000>;
  65         tx_delay = <0x30>;
  66         rx_delay = <0x10>;
  67         status = "okay";
  68 };
  69
  70 &emmc {
  71         u-boot,dm-pre-reloc;
  72         status = "okay";
  73 };
  74
  75 &sdmmc {
  76         status = "okay";
  77         bus-width = <4>;
  78         cap-mmc-highspeed;
  79         cap-sd-highspeed;
  80         card-detect-delay = <200>;
  81         disable-wp;
  82         num-slots = <1>;
  83         supports-sd;
  84 };
  85
  86 &uart2 {
  87         status = "okay";
  88 };
  89
  90 &usb20_otg {
  91        status = "okay";
  92 };