arch/arm/dts/sama5d2.dtsi

   1 #include "skeleton.dtsi"
   2
   3 / {
   4         model = "Atmel SAMA5D2 family SoC";
   5         compatible = "atmel,sama5d2";
   6
   7         aliases {
   8                 spi0 = &spi0;
   9                 spi1 = &qspi0;
  10                 i2c0 = &i2c0;
  11                 i2c1 = &i2c1;
  12         };
  13
  14         clocks {
  15                 slow_xtal: slow_xtal {
  16                         compatible = "fixed-clock";
  17                         #clock-cells = <0>;
  18                         clock-frequency = <0>;
  19                 };
  20
  21                 main_xtal: main_xtal {
  22                         compatible = "fixed-clock";
  23                         #clock-cells = <0>;
  24                         clock-frequency = <0>;
  25                 };
  26         };
  27
  28         ahb {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 u-boot,dm-pre-reloc;
  33
  34                 usb1: ohci@00400000 {
  35                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  36                         reg = <0x00400000 0x100000>;
  37                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  38                         clock-names = "ohci_clk", "hclk", "uhpck";
  39                         status = "disabled";
  40                 };
  41
  42                 usb2: ehci@00500000 {
  43                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  44                         reg = <0x00500000 0x100000>;
  45                         clocks = <&utmi>, <&uhphs_clk>;
  46                         clock-names = "usb_clk", "ehci_clk";
  47                         status = "disabled";
  48                 };
  49
  50                 sdmmc0: sdio-host@a0000000 {
  51                         compatible = "atmel,sama5d2-sdhci";
  52                         reg = <0xa0000000 0x300>;
  53                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
  54                         clock-names = "hclock", "multclk", "baseclk";
  55                         status = "disabled";
  56                 };
  57
  58                 sdmmc1: sdio-host@b0000000 {
  59                         compatible = "atmel,sama5d2-sdhci";
  60                         reg = <0xb0000000 0x300>;
  61                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
  62                         clock-names = "hclock", "multclk", "baseclk";
  63                         status = "disabled";
  64                 };
  65
  66                 apb {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         u-boot,dm-pre-reloc;
  71
  72                         hlcdc: hlcdc@f0000000 {
  73                                 compatible = "atmel,at91sam9x5-hlcdc";
  74                                 reg = <0xf0000000 0x2000>;
  75                                 clocks = <&lcdc_clk>;
  76                                 status = "disabled";
  77                         };
  78
  79                         pmc: pmc@f0014000 {
  80                                 compatible = "atmel,sama5d2-pmc", "syscon";
  81                                 reg = <0xf0014000 0x160>;
  82                                 #address-cells = <1>;
  83                                 #size-cells = <0>;
  84                                 #interrupt-cells = <1>;
  85                                 u-boot,dm-pre-reloc;
  86
  87                                 main: mainck {
  88                                         compatible = "atmel,at91sam9x5-clk-main";
  89                                         #clock-cells = <0>;
  90                                         u-boot,dm-pre-reloc;
  91                                 };
  92
  93                                 plla: pllack@0 {
  94                                         compatible = "atmel,sama5d3-clk-pll";
  95                                         #clock-cells = <0>;
  96                                         clocks = <&main>;
  97                                         reg = <0>;
  98                                         atmel,clk-input-range = <12000000 12000000>;
  99                                         #atmel,pll-clk-output-range-cells = <4>;
 100                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 101                                         u-boot,dm-pre-reloc;
 102                                 };
 103
 104                                 plladiv: plladivck {
 105                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 106                                         #clock-cells = <0>;
 107                                         clocks = <&plla>;
 108                                 };
 109
 110                                 audio_pll_frac: audiopll_fracck {
 111                                         compatible = "atmel,sama5d2-clk-audio-pll-frac";
 112                                         #clock-cells = <0>;
 113                                         clocks = <&main>;
 114                                 };
 115
 116                                 audio_pll_pad: audiopll_padck {
 117                                         compatible = "atmel,sama5d2-clk-audio-pll-pad";
 118                                         #clock-cells = <0>;
 119                                         clocks = <&audio_pll_frac>;
 120                                 };
 121
 122                                 audio_pll_pmc: audiopll_pmcck {
 123                                         compatible = "atmel,sama5d2-clk-audio-pll-pmc";
 124                                         #clock-cells = <0>;
 125                                         clocks = <&audio_pll_frac>;
 126                                 };
 127
 128                                 utmi: utmick {
 129                                         compatible = "atmel,at91sam9x5-clk-utmi";
 130                                         #clock-cells = <0>;
 131                                         clocks = <&main>;
 132                                         regmap-sfr = <&sfr>;
 133                                         u-boot,dm-pre-reloc;
 134                                 };
 135
 136                                 mck: masterck {
 137                                         compatible = "atmel,at91sam9x5-clk-master";
 138                                         #clock-cells = <0>;
 139                                         clocks = <&main>, <&plladiv>, <&utmi>;
 140                                         atmel,clk-output-range = <124000000 166000000>;
 141                                         atmel,clk-divisors = <1 2 4 3>;
 142                                         u-boot,dm-pre-reloc;
 143                                 };
 144
 145                                 h32ck: h32mxck {
 146                                         #clock-cells = <0>;
 147                                         compatible = "atmel,sama5d4-clk-h32mx";
 148                                         clocks = <&mck>;
 149                                         u-boot,dm-pre-reloc;
 150                                 };
 151
 152                                 usb: usbck {
 153                                         compatible = "atmel,at91sam9x5-clk-usb";
 154                                         #clock-cells = <0>;
 155                                         clocks = <&plladiv>, <&utmi>;
 156                                 };
 157
 158                                 prog: progck {
 159                                         compatible = "atmel,at91sam9x5-clk-programmable";
 160                                         #address-cells = <1>;
 161                                         #size-cells = <0>;
 162                                         interrupt-parent = <&pmc>;
 163                                         clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
 164
 165                                         prog0: prog@0 {
 166                                                 #clock-cells = <0>;
 167                                                 reg = <0>;
 168                                         };
 169
 170                                         prog1: prog@1 {
 171                                                 #clock-cells = <0>;
 172                                                 reg = <1>;
 173                                         };
 174
 175                                         prog2: prog@2 {
 176                                                 #clock-cells = <0>;
 177                                                 reg = <2>;
 178                                         };
 179                                 };
 180
 181                                 systemck {
 182                                         compatible = "atmel,at91rm9200-clk-system";
 183                                         #address-cells = <1>;
 184                                         #size-cells = <0>;
 185
 186                                         ddrck: ddrck@2 {
 187                                                 #clock-cells = <0>;
 188                                                 reg = <2>;
 189                                                 clocks = <&mck>;
 190                                         };
 191
 192                                         lcdck: lcdck@3 {
 193                                                 #clock-cells = <0>;
 194                                                 reg = <3>;
 195                                                 clocks = <&mck>;
 196                                         };
 197
 198                                         uhpck: uhpck@6 {
 199                                                 #clock-cells = <0>;
 200                                                 reg = <6>;
 201                                                 clocks = <&usb>;
 202                                         };
 203
 204                                         udpck: udpck@7 {
 205                                                 #clock-cells = <0>;
 206                                                 reg = <7>;
 207                                                 clocks = <&usb>;
 208                                         };
 209
 210                                         pck0: pck0@8 {
 211                                                 #clock-cells = <0>;
 212                                                 reg = <8>;
 213                                                 clocks = <&prog0>;
 214                                         };
 215
 216                                         pck1: pck1@9 {
 217                                                 #clock-cells = <0>;
 218                                                 reg = <9>;
 219                                                 clocks = <&prog1>;
 220                                         };
 221
 222                                         pck2: pck2@10 {
 223                                                 #clock-cells = <0>;
 224                                                 reg = <10>;
 225                                                 clocks = <&prog2>;
 226                                         };
 227
 228                                         iscck: iscck@18 {
 229                                                 #clock-cells = <0>;
 230                                                 reg = <18>;
 231                                                 clocks = <&mck>;
 232                                         };
 233                                 };
 234
 235                                 periph32ck {
 236                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 237                                         #address-cells = <1>;
 238                                         #size-cells = <0>;
 239                                         clocks = <&h32ck>;
 240                                         u-boot,dm-pre-reloc;
 241
 242                                         macb0_clk: macb0_clk@5 {
 243                                                 #clock-cells = <0>;
 244                                                 reg = <5>;
 245                                                 atmel,clk-output-range = <0 83000000>;
 246                                         };
 247
 248                                         tdes_clk: tdes_clk@11 {
 249                                                 #clock-cells = <0>;
 250                                                 reg = <11>;
 251                                                 atmel,clk-output-range = <0 83000000>;
 252                                         };
 253
 254                                         matrix1_clk: matrix1_clk@14 {
 255                                                 #clock-cells = <0>;
 256                                                 reg = <14>;
 257                                         };
 258
 259                                         hsmc_clk: hsmc_clk@17 {
 260                                                 #clock-cells = <0>;
 261                                                 reg = <17>;
 262                                         };
 263
 264                                         pioA_clk: pioA_clk@18 {
 265                                                 #clock-cells = <0>;
 266                                                 reg = <18>;
 267                                                 atmel,clk-output-range = <0 83000000>;
 268                                                 u-boot,dm-pre-reloc;
 269                                         };
 270
 271                                         flx0_clk: flx0_clk@19 {
 272                                                 #clock-cells = <0>;
 273                                                 reg = <19>;
 274                                                 atmel,clk-output-range = <0 83000000>;
 275                                         };
 276
 277                                         flx1_clk: flx1_clk@20 {
 278                                                 #clock-cells = <0>;
 279                                                 reg = <20>;
 280                                                 atmel,clk-output-range = <0 83000000>;
 281                                         };
 282
 283                                         flx2_clk: flx2_clk@21 {
 284                                                 #clock-cells = <0>;
 285                                                 reg = <21>;
 286                                                 atmel,clk-output-range = <0 83000000>;
 287                                         };
 288
 289                                         flx3_clk: flx3_clk@22 {
 290                                                 #clock-cells = <0>;
 291                                                 reg = <22>;
 292                                                 atmel,clk-output-range = <0 83000000>;
 293                                         };
 294
 295                                         flx4_clk: flx4_clk@23 {
 296                                                 #clock-cells = <0>;
 297                                                 reg = <23>;
 298                                                 atmel,clk-output-range = <0 83000000>;
 299                                         };
 300
 301                                         uart0_clk: uart0_clk@24 {
 302                                                 #clock-cells = <0>;
 303                                                 reg = <24>;
 304                                                 atmel,clk-output-range = <0 83000000>;
 305                                         };
 306
 307                                         uart1_clk: uart1_clk@25 {
 308                                                 #clock-cells = <0>;
 309                                                 reg = <25>;
 310                                                 atmel,clk-output-range = <0 83000000>;
 311                                                 u-boot,dm-pre-reloc;
 312                                         };
 313
 314                                         uart2_clk: uart2_clk@26 {
 315                                                 #clock-cells = <0>;
 316                                                 reg = <26>;
 317                                                 atmel,clk-output-range = <0 83000000>;
 318                                         };
 319
 320                                         uart3_clk: uart3_clk@27 {
 321                                                 #clock-cells = <0>;
 322                                                 reg = <27>;
 323                                                 atmel,clk-output-range = <0 83000000>;
 324                                         };
 325
 326                                         uart4_clk: uart4_clk@28 {
 327                                                 #clock-cells = <0>;
 328                                                 reg = <28>;
 329                                                 atmel,clk-output-range = <0 83000000>;
 330                                         };
 331
 332                                         twi0_clk: twi0_clk@29 {
 333                                                 reg = <29>;
 334                                                 #clock-cells = <0>;
 335                                                 atmel,clk-output-range = <0 83000000>;
 336                                         };
 337
 338                                         twi1_clk: twi1_clk@30 {
 339                                                 #clock-cells = <0>;
 340                                                 reg = <30>;
 341                                                 atmel,clk-output-range = <0 83000000>;
 342                                         };
 343
 344                                         spi0_clk: spi0_clk@33 {
 345                                                 #clock-cells = <0>;
 346                                                 reg = <33>;
 347                                                 atmel,clk-output-range = <0 83000000>;
 348                                                 u-boot,dm-pre-reloc;
 349                                         };
 350
 351                                         spi1_clk: spi1_clk@34 {
 352                                                 #clock-cells = <0>;
 353                                                 reg = <34>;
 354                                                 atmel,clk-output-range = <0 83000000>;
 355                                         };
 356
 357                                         tcb0_clk: tcb0_clk@35 {
 358                                                 #clock-cells = <0>;
 359                                                 reg = <35>;
 360                                                 atmel,clk-output-range = <0 83000000>;
 361                                         };
 362
 363                                         tcb1_clk: tcb1_clk@36 {
 364                                                 #clock-cells = <0>;
 365                                                 reg = <36>;
 366                                                 atmel,clk-output-range = <0 83000000>;
 367                                         };
 368
 369                                         pwm_clk: pwm_clk@38 {
 370                                                 #clock-cells = <0>;
 371                                                 reg = <38>;
 372                                                 atmel,clk-output-range = <0 83000000>;
 373                                         };
 374
 375                                         adc_clk: adc_clk@40 {
 376                                                 #clock-cells = <0>;
 377                                                 reg = <40>;
 378                                                 atmel,clk-output-range = <0 83000000>;
 379                                         };
 380
 381                                         uhphs_clk: uhphs_clk@41 {
 382                                                 #clock-cells = <0>;
 383                                                 reg = <41>;
 384                                                 atmel,clk-output-range = <0 83000000>;
 385                                         };
 386
 387                                         udphs_clk: udphs_clk@42 {
 388                                                 #clock-cells = <0>;
 389                                                 reg = <42>;
 390                                                 atmel,clk-output-range = <0 83000000>;
 391                                         };
 392
 393                                         ssc0_clk: ssc0_clk@43 {
 394                                                 #clock-cells = <0>;
 395                                                 reg = <43>;
 396                                                 atmel,clk-output-range = <0 83000000>;
 397                                         };
 398
 399                                         ssc1_clk: ssc1_clk@44 {
 400                                                 #clock-cells = <0>;
 401                                                 reg = <44>;
 402                                                 atmel,clk-output-range = <0 83000000>;
 403                                         };
 404
 405                                         trng_clk: trng_clk@47 {
 406                                                 #clock-cells = <0>;
 407                                                 reg = <47>;
 408                                                 atmel,clk-output-range = <0 83000000>;
 409                                         };
 410
 411                                         pdmic_clk: pdmic_clk@48 {
 412                                                 #clock-cells = <0>;
 413                                                 reg = <48>;
 414                                                 atmel,clk-output-range = <0 83000000>;
 415                                         };
 416
 417                                         i2s0_clk: i2s0_clk@54 {
 418                                                 #clock-cells = <0>;
 419                                                 reg = <54>;
 420                                                 atmel,clk-output-range = <0 83000000>;
 421                                         };
 422
 423                                         i2s1_clk: i2s1_clk@55 {
 424                                                 #clock-cells = <0>;
 425                                                 reg = <55>;
 426                                                 atmel,clk-output-range = <0 83000000>;
 427                                         };
 428
 429                                         can0_clk: can0_clk@56 {
 430                                                 #clock-cells = <0>;
 431                                                 reg = <56>;
 432                                                 atmel,clk-output-range = <0 83000000>;
 433                                         };
 434
 435                                         can1_clk: can1_clk@57 {
 436                                                 #clock-cells = <0>;
 437                                                 reg = <57>;
 438                                                 atmel,clk-output-range = <0 83000000>;
 439                                         };
 440
 441                                         classd_clk: classd_clk@59 {
 442                                                 #clock-cells = <0>;
 443                                                 reg = <59>;
 444                                                 atmel,clk-output-range = <0 83000000>;
 445                                         };
 446                                 };
 447
 448                                 periph64ck {
 449                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 450                                         #address-cells = <1>;
 451                                         #size-cells = <0>;
 452                                         clocks = <&mck>;
 453                                         u-boot,dm-pre-reloc;
 454
 455                                         dma0_clk: dma0_clk@6 {
 456                                                 #clock-cells = <0>;
 457                                                 reg = <6>;
 458                                         };
 459
 460                                         dma1_clk: dma1_clk@7 {
 461                                                 #clock-cells = <0>;
 462                                                 reg = <7>;
 463                                         };
 464
 465                                         aes_clk: aes_clk@9 {
 466                                                 #clock-cells = <0>;
 467                                                 reg = <9>;
 468                                         };
 469
 470                                         aesb_clk: aesb_clk@10 {
 471                                                 #clock-cells = <0>;
 472                                                 reg = <10>;
 473                                         };
 474
 475                                         sha_clk: sha_clk@12 {
 476                                                 #clock-cells = <0>;
 477                                                 reg = <12>;
 478                                         };
 479
 480                                         mpddr_clk: mpddr_clk@13 {
 481                                                 #clock-cells = <0>;
 482                                                 reg = <13>;
 483                                         };
 484
 485                                         matrix0_clk: matrix0_clk@15 {
 486                                                 #clock-cells = <0>;
 487                                                 reg = <15>;
 488                                         };
 489
 490                                         sdmmc0_hclk: sdmmc0_hclk@31 {
 491                                                 #clock-cells = <0>;
 492                                                 reg = <31>;
 493                                                 u-boot,dm-pre-reloc;
 494                                         };
 495
 496                                         sdmmc1_hclk: sdmmc1_hclk@32 {
 497                                                 #clock-cells = <0>;
 498                                                 reg = <32>;
 499                                                 u-boot,dm-pre-reloc;
 500                                         };
 501
 502                                         lcdc_clk: lcdc_clk@45 {
 503                                                 #clock-cells = <0>;
 504                                                 reg = <45>;
 505                                         };
 506
 507                                         isc_clk: isc_clk@46 {
 508                                                 #clock-cells = <0>;
 509                                                 reg = <46>;
 510                                         };
 511
 512                                         qspi0_clk: qspi0_clk@52 {
 513                                                 #clock-cells = <0>;
 514                                                 reg = <52>;
 515                                                 u-boot,dm-pre-reloc;
 516                                         };
 517
 518                                         qspi1_clk: qspi1_clk@53 {
 519                                                 #clock-cells = <0>;
 520                                                 reg = <53>;
 521                                                 u-boot,dm-pre-reloc;
 522                                         };
 523                                 };
 524
 525                                 gck {
 526                                         compatible = "atmel,sama5d2-clk-generated";
 527                                         #address-cells = <1>;
 528                                         #size-cells = <0>;
 529                                         interrupt-parent = <&pmc>;
 530                                         clocks = <&main>, <&plla>, <&utmi>, <&mck>;
 531                                         u-boot,dm-pre-reloc;
 532
 533                                         sdmmc0_gclk: sdmmc0_gclk@31 {
 534                                                 #clock-cells = <0>;
 535                                                 reg = <31>;
 536                                                 u-boot,dm-pre-reloc;
 537                                         };
 538
 539                                         sdmmc1_gclk: sdmmc1_gclk@32 {
 540                                                 #clock-cells = <0>;
 541                                                 reg = <32>;
 542                                                 u-boot,dm-pre-reloc;
 543                                         };
 544
 545                                         tcb0_gclk: tcb0_gclk@35 {
 546                                                 #clock-cells = <0>;
 547                                                 reg = <35>;
 548                                                 atmel,clk-output-range = <0 83000000>;
 549                                         };
 550
 551                                         tcb1_gclk: tcb1_gclk@36 {
 552                                                 #clock-cells = <0>;
 553                                                 reg = <36>;
 554                                                 atmel,clk-output-range = <0 83000000>;
 555                                         };
 556
 557                                         pwm_gclk: pwm_gclk@38 {
 558                                                 #clock-cells = <0>;
 559                                                 reg = <38>;
 560                                                 atmel,clk-output-range = <0 83000000>;
 561                                         };
 562
 563                                         pdmic_gclk: pdmic_gclk@48 {
 564                                                 #clock-cells = <0>;
 565                                                 reg = <48>;
 566                                         };
 567
 568                                         i2s0_gclk: i2s0_gclk@54 {
 569                                                 #clock-cells = <0>;
 570                                                 reg = <54>;
 571                                         };
 572
 573                                         i2s1_gclk: i2s1_gclk@55 {
 574                                                 #clock-cells = <0>;
 575                                                 reg = <55>;
 576                                         };
 577
 578                                         can0_gclk: can0_gclk@56 {
 579                                                 #clock-cells = <0>;
 580                                                 reg = <56>;
 581                                                 atmel,clk-output-range = <0 80000000>;
 582                                         };
 583
 584                                         can1_gclk: can1_gclk@57 {
 585                                                 #clock-cells = <0>;
 586                                                 reg = <57>;
 587                                                 atmel,clk-output-range = <0 80000000>;
 588                                         };
 589
 590                                         classd_gclk: classd_gclk@59 {
 591                                                 #clock-cells = <0>;
 592                                                 reg = <59>;
 593                                                 atmel,clk-output-range = <0 100000000>;
 594                                         };
 595                                 };
 596                         };
 597
 598                         qspi0: spi@f0020000 {
 599                                 compatible = "atmel,sama5d2-qspi";
 600                                 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
 601                                 reg-names = "qspi_base", "qspi_mmap";
 602                                 #address-cells = <1>;
 603                                 #size-cells = <0>;
 604                                 clocks = <&qspi0_clk>;
 605                                 status = "disabled";
 606                         };
 607
 608                         qspi1: spi@f0024000 {
 609                                 compatible = "atmel,sama5d2-qspi";
 610                                 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
 611                                 reg-names = "qspi_base", "qspi_mmap";
 612                                 #address-cells = <1>;
 613                                 #size-cells = <0>;
 614                                 clocks = <&qspi1_clk>;
 615                                 status = "disabled";
 616                         };
 617
 618                         spi0: spi@f8000000 {
 619                                 compatible = "atmel,at91rm9200-spi";
 620                                 reg = <0xf8000000 0x100>;
 621                                 clocks = <&spi0_clk>;
 622                                 clock-names = "spi_clk";
 623                                 #address-cells = <1>;
 624                                 #size-cells = <0>;
 625                                 status = "disabled";
 626                         };
 627
 628                         macb0: ethernet@f8008000 {
 629                                 compatible = "cdns,macb";
 630                                 reg = <0xf8008000 0x1000>;
 631                                 #address-cells = <1>;
 632                                 #size-cells = <0>;
 633                                 clocks = <&macb0_clk>, <&macb0_clk>;
 634                                 clock-names = "hclk", "pclk";
 635                                 status = "disabled";
 636                         };
 637
 638                         uart1: serial@f8020000 {
 639                                 compatible = "atmel,at91sam9260-usart";
 640                                 reg = <0xf8020000 0x100>;
 641                                 clocks = <&uart1_clk>;
 642                                 clock-names = "usart";
 643                                 status = "disabled";
 644                         };
 645
 646                         i2c0: i2c@f8028000 {
 647                                 compatible = "atmel,sama5d2-i2c";
 648                                 reg = <0xf8028000 0x100>;
 649                                 #address-cells = <1>;
 650                                 #size-cells = <0>;
 651                                 clocks = <&twi0_clk>;
 652                                 status = "disabled";
 653                         };
 654
 655                         rstc@f8048000 {
 656                                 compatible = "atmel,sama5d3-rstc";
 657                                 reg = <0xf8048000 0x10>;
 658                                 clocks = <&clk32k>;
 659                         };
 660
 661                         shdwc@f8048010 {
 662                                 compatible = "atmel,sama5d2-shdwc";
 663                                 reg = <0xf8048010 0x10>;
 664                                 clocks = <&clk32k>;
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667                                 atmel,wakeup-rtc-timer;
 668                         };
 669
 670                         pit: timer@f8048030 {
 671                                 compatible = "atmel,at91sam9260-pit";
 672                                 reg = <0xf8048030 0x10>;
 673                                 clocks = <&h32ck>;
 674                         };
 675
 676                         watchdog@f8048040 {
 677                                 compatible = "atmel,sama5d4-wdt";
 678                                 reg = <0xf8048040 0x10>;
 679                                 clocks = <&clk32k>;
 680                                 status = "disabled";
 681                         };
 682
 683                         sfr: sfr@f8030000 {
 684                                 compatible = "atmel,sama5d2-sfr", "syscon";
 685                                 reg = <0xf8030000 0x98>;
 686                         };
 687
 688                         sckc@f8048050 {
 689                                 compatible = "atmel,at91sam9x5-sckc";
 690                                 reg = <0xf8048050 0x4>;
 691
 692                                 slow_rc_osc: slow_rc_osc {
 693                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 694                                         #clock-cells = <0>;
 695                                         clock-frequency = <32768>;
 696                                         clock-accuracy = <250000000>;
 697                                         atmel,startup-time-usec = <75>;
 698                                 };
 699
 700                                 slow_osc: slow_osc {
 701                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 702                                         #clock-cells = <0>;
 703                                         clocks = <&slow_xtal>;
 704                                         atmel,startup-time-usec = <1200000>;
 705                                 };
 706
 707                                 clk32k: slowck {
 708                                         compatible = "atmel,at91sam9x5-clk-slow";
 709                                         #clock-cells = <0>;
 710                                         clocks = <&slow_rc_osc &slow_osc>;
 711                                 };
 712                         };
 713
 714                         spi1: spi@fc000000 {
 715                                 compatible = "atmel,at91rm9200-spi";
 716                                 reg = <0xfc000000 0x100>;
 717                                 #address-cells = <1>;
 718                                 #size-cells = <0>;
 719                                 status = "disabled";
 720                         };
 721
 722                         uart3: serial@fc008000 {
 723                                 compatible = "atmel,at91sam9260-usart";
 724                                 reg = <0xfc008000 0x100>;
 725                                 clocks = <&uart3_clk>;
 726                                 clock-names = "usart";
 727                                 status = "disabled";
 728                         };
 729
 730                         i2c1: i2c@fc028000 {
 731                                 compatible = "atmel,sama5d2-i2c";
 732                                 reg = <0xfc028000 0x100>;
 733                                 #address-cells = <1>;
 734                                 #size-cells = <0>;
 735                                 clocks = <&twi1_clk>;
 736                                 status = "disabled";
 737                         };
 738
 739                         pioA: gpio@fc038000 {
 740                                 compatible = "atmel,sama5d2-gpio";
 741                                 reg = <0xfc038000 0x600>;
 742                                 clocks = <&pioA_clk>;
 743                                 gpio-controller;
 744                                 #gpio-cells = <2>;
 745                                 u-boot,dm-pre-reloc;
 746
 747                                 pinctrl {
 748                                         compatible = "atmel,sama5d2-pinctrl";
 749                                         u-boot,dm-pre-reloc;
 750                                 };
 751                         };
 752                 };
 753         };
 754 };