arch/arm/dts/stm32f746-disco.dts

   1 /*
   2  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
   3  * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
   4  *
   5  * Based on:
   6  * stm32f469-disco.dts from Linux
   7  * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This file is distributed in the hope that it will be useful,
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 /dts-v1/;
  49 #include "stm32f746.dtsi"
  50 #include <dt-bindings/memory/stm32-sdram.h>
  51
  52 / {
  53         model = "STMicroelectronics STM32F746-DISCO board";
  54         compatible = "st,stm32f746-disco", "st,stm32f746";
  55
  56         chosen {
  57                 bootargs = "root=/dev/ram rdinit=/linuxrc";
  58                 stdout-path = "serial0:115200n8";
  59         };
  60
  61         memory {
  62                 reg = <0xC0000000 0x800000>;
  63         };
  64
  65         aliases {
  66                 serial0 = &usart1;
  67                 spi0 = &qspi;
  68                 mmc0 = &sdio;
  69                 /* Aliases for gpios so as to use sequence */
  70                 gpio0 = &gpioa;
  71                 gpio1 = &gpiob;
  72                 gpio2 = &gpioc;
  73                 gpio3 = &gpiod;
  74                 gpio4 = &gpioe;
  75                 gpio5 = &gpiof;
  76                 gpio6 = &gpiog;
  77                 gpio7 = &gpioh;
  78                 gpio8 = &gpioi;
  79                 gpio9 = &gpioj;
  80                 gpio10 = &gpiok;
  81         };
  82
  83         led1 {
  84                 compatible = "st,led1";
  85                 led-gpio = <&gpioi 1 0>;
  86         };
  87
  88         button1 {
  89                 compatible = "st,button1";
  90                 button-gpio = <&gpioi 11 0>;
  91         };
  92 };
  93
  94 &clk_hse {
  95         clock-frequency = <25000000>;
  96 };
  97
  98 &pinctrl {
  99         usart1_pins_a: usart1@0 {
 100                 pins1 {
 101                        pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
 102                                 bias-disable;
 103                                 drive-push-pull;
 104                                 slew-rate = <2>;
 105                 };
 106                 pins2 {
 107                         pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
 108                         bias-disable;
 109                 };
 110         };
 111
 112         ethernet_mii: mii@0 {
 113               pins {
 114                       pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 115                              <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 116                              <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 117                              <STM32F746_PA2_FUNC_ETH_MDIO>,
 118                              <STM32F746_PC1_FUNC_ETH_MDC>,
 119                              <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 120                              <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 121                              <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 122                              <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
 123                       slew-rate = <2>;
 124               };
 125         };
 126
 127         qspi_pins: qspi@0 {
 128                 pins {
 129                         pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
 130                                <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
 131                                <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
 132                                <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
 133                                <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
 134                                <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
 135                         slew-rate = <2>;
 136                 };
 137         };
 138
 139         fmc_pins: fmc@0 {
 140                 pins {
 141                         pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
 142                                  <STM32F746_PD9_FUNC_FMC_D14>,
 143                                  <STM32F746_PD8_FUNC_FMC_D13>,
 144                                  <STM32F746_PE15_FUNC_FMC_D12>,
 145                                  <STM32F746_PE14_FUNC_FMC_D11>,
 146                                  <STM32F746_PE13_FUNC_FMC_D10>,
 147                                  <STM32F746_PE12_FUNC_FMC_D9>,
 148                                  <STM32F746_PE11_FUNC_FMC_D8>,
 149                                  <STM32F746_PE10_FUNC_FMC_D7>,
 150                                  <STM32F746_PE9_FUNC_FMC_D6>,
 151                                  <STM32F746_PE8_FUNC_FMC_D5>,
 152                                  <STM32F746_PE7_FUNC_FMC_D4>,
 153                                  <STM32F746_PD1_FUNC_FMC_D3>,
 154                                  <STM32F746_PD0_FUNC_FMC_D2>,
 155                                  <STM32F746_PD15_FUNC_FMC_D1>,
 156                                  <STM32F746_PD14_FUNC_FMC_D0>,
 157
 158                                  <STM32F746_PE1_FUNC_FMC_NBL1>,
 159                                  <STM32F746_PE0_FUNC_FMC_NBL0>,
 160
 161                                  <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
 162                                  <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
 163
 164                                  <STM32F746_PG1_FUNC_FMC_A11>,
 165                                  <STM32F746_PG0_FUNC_FMC_A10>,
 166                                  <STM32F746_PF15_FUNC_FMC_A9>,
 167                                  <STM32F746_PF14_FUNC_FMC_A8>,
 168                                  <STM32F746_PF13_FUNC_FMC_A7>,
 169                                  <STM32F746_PF12_FUNC_FMC_A6>,
 170                                  <STM32F746_PF5_FUNC_FMC_A5>,
 171                                  <STM32F746_PF4_FUNC_FMC_A4>,
 172                                  <STM32F746_PF3_FUNC_FMC_A3>,
 173                                  <STM32F746_PF2_FUNC_FMC_A2>,
 174                                  <STM32F746_PF1_FUNC_FMC_A1>,
 175                                  <STM32F746_PF0_FUNC_FMC_A0>,
 176
 177                                  <STM32F746_PH3_FUNC_FMC_SDNE0>,
 178                                  <STM32F746_PH5_FUNC_FMC_SDNWE>,
 179                                  <STM32F746_PF11_FUNC_FMC_SDNRAS>,
 180                                  <STM32F746_PG15_FUNC_FMC_SDNCAS>,
 181                                  <STM32F746_PC3_FUNC_FMC_SDCKE0>,
 182                                  <STM32F746_PG8_FUNC_FMC_SDCLK>;
 183                           slew-rate = <2>;
 184                 };
 185         };
 186 };
 187
 188 &usart1 {
 189         pinctrl-0 = <&usart1_pins_a>;
 190         pinctrl-names = "default";
 191         status = "okay";
 192 };
 193
 194 &fmc {
 195         pinctrl-0 = <&fmc_pins>;
 196         pinctrl-names = "default";
 197         status = "okay";
 198
 199         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
 200         bank1: bank@0 {
 201                st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
 202                                             CAS_3 SDCLK_2 RD_BURST_EN
 203                                             RD_PIPE_DL_0>;
 204                st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
 205                                            TRP_2 TRCD_2>;
 206                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
 207                st,sdram-refcount = < 1542 >;
 208        };
 209 };
 210
 211 &mac {
 212         status = "okay";
 213         pinctrl-0 = <&ethernet_mii>;
 214         phy-mode = "rmii";
 215         phy-handle = <&phy0>;
 216
 217         mdio0 {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 compatible = "snps,dwmac-mdio";
 221                 phy0: ethernet-phy@0 {
 222                         reg = <0>;
 223                 };
 224         };
 225 };
 226
 227 &qspi {
 228         pinctrl-0 = <&qspi_pins>;
 229         status = "okay";
 230
 231         qflash0: n25q128a {
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         compatible = "micron,n25q128a13", "spi-flash";
 235                         spi-max-frequency = <108000000>;
 236                         spi-tx-bus-width = <1>;
 237                         spi-rx-bus-width = <1>;
 238                         memory-map = <0x90000000 0x1000000>;
 239                         reg = <0>;
 240         };
 241 };
 242
 243 &sdio {
 244         status = "okay";
 245         cd-gpios = <&gpioc 13 0>;
 246         cd-inverted;
 247         pinctrl-names = "default", "opendrain";
 248         pinctrl-0 = <&sdio_pins>;
 249         pinctrl-1 = <&sdio_pins_od>;
 250         bus-width = <4>;
 251         max-frequency = <25000000>;
 252 };