2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/sun4i-a10.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
51 interrupt-parent = <&gic>;
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
80 compatible = "arm,cortex-a7";
87 compatible = "arm,armv7-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
114 compatible = "fixed-factor-clock";
119 clock-output-names = "apb0";
122 apb0_gates: clk@01f01428 {
123 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
124 "allwinner,sun4i-a10-gates-clk";
125 reg = <0x01f01428 0x4>;
128 clock-indices = <0>, <1>;
129 clock-output-names = "apb0_pio", "apb0_ir";
132 ir_clk: ir_clk@01f01454 {
133 compatible = "allwinner,sun4i-a10-mod0-clk";
134 reg = <0x01f01454 0x4>;
136 clocks = <&osc32k>, <&osc24M>;
137 clock-output-names = "ir";
142 compatible = "simple-bus";
143 #address-cells = <1>;
147 syscon: syscon@01c00000 {
148 compatible = "allwinner,sun8i-h3-syscon","syscon";
149 reg = <0x01c00000 0x34>;
152 dma: dma-controller@01c02000 {
153 compatible = "allwinner,sun8i-h3-dma";
154 reg = <0x01c02000 0x1000>;
155 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&ccu CLK_BUS_DMA>;
157 resets = <&ccu RST_BUS_DMA>;
162 compatible = "allwinner,sun7i-a20-mmc",
163 "allwinner,sun5i-a13-mmc";
164 reg = <0x01c0f000 0x1000>;
165 clocks = <&ccu CLK_BUS_MMC0>,
167 <&ccu CLK_MMC0_OUTPUT>,
168 <&ccu CLK_MMC0_SAMPLE>;
173 resets = <&ccu RST_BUS_MMC0>;
175 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
177 #address-cells = <1>;
182 compatible = "allwinner,sun7i-a20-mmc",
183 "allwinner,sun5i-a13-mmc";
184 reg = <0x01c10000 0x1000>;
185 clocks = <&ccu CLK_BUS_MMC1>,
187 <&ccu CLK_MMC1_OUTPUT>,
188 <&ccu CLK_MMC1_SAMPLE>;
193 resets = <&ccu RST_BUS_MMC1>;
195 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
202 compatible = "allwinner,sun7i-a20-mmc",
203 "allwinner,sun5i-a13-mmc";
204 reg = <0x01c11000 0x1000>;
205 clocks = <&ccu CLK_BUS_MMC2>,
207 <&ccu CLK_MMC2_OUTPUT>,
208 <&ccu CLK_MMC2_SAMPLE>;
213 resets = <&ccu RST_BUS_MMC2>;
215 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
221 usbphy: phy@01c19400 {
222 compatible = "allwinner,sun8i-h3-usb-phy";
223 reg = <0x01c19400 0x2c>,
228 reg-names = "phy_ctrl",
233 clocks = <&ccu CLK_USB_PHY0>,
237 clock-names = "usb0_phy",
241 resets = <&ccu RST_USB_PHY0>,
245 reset-names = "usb0_reset",
253 ehci1: usb@01c1b000 {
254 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
255 reg = <0x01c1b000 0x100>;
256 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
264 ohci1: usb@01c1b400 {
265 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
266 reg = <0x01c1b400 0x100>;
267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
269 <&ccu CLK_USB_OHCI1>;
270 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
276 ehci2: usb@01c1c000 {
277 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
278 reg = <0x01c1c000 0x100>;
279 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
287 ohci2: usb@01c1c400 {
288 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
289 reg = <0x01c1c400 0x100>;
290 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
292 <&ccu CLK_USB_OHCI2>;
293 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
299 ehci3: usb@01c1d000 {
300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
301 reg = <0x01c1d000 0x100>;
302 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
310 ohci3: usb@01c1d400 {
311 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
312 reg = <0x01c1d400 0x100>;
313 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
315 <&ccu CLK_USB_OHCI3>;
316 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
322 ccu: clock@01c20000 {
323 compatible = "allwinner,sun8i-h3-ccu";
324 reg = <0x01c20000 0x400>;
325 clocks = <&osc24M>, <&osc32k>;
326 clock-names = "hosc", "losc";
331 pio: pinctrl@01c20800 {
332 compatible = "allwinner,sun8i-h3-pinctrl";
333 reg = <0x01c20800 0x400>;
334 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&ccu CLK_BUS_PIO>;
339 interrupt-controller;
340 #interrupt-cells = <3>;
342 emac_rgmii_pins: emac0@0 {
343 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
345 "PD8", "PD9", "PD10",
346 "PD12", "PD13", "PD15",
348 allwinner,function = "emac";
349 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
350 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
354 pins = "PA11", "PA12";
358 mmc0_pins_a: mmc0@0 {
359 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
361 allwinner,function = "mmc0";
362 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
363 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
366 mmc0_cd_pin: mmc0_cd_pin@0 {
367 allwinner,pins = "PF6";
368 allwinner,function = "gpio_in";
369 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
370 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
373 mmc1_pins_a: mmc1@0 {
374 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
376 allwinner,function = "mmc1";
377 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
378 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
381 mmc2_8bit_pins: mmc2_8bit {
382 allwinner,pins = "PC5", "PC6", "PC8",
383 "PC9", "PC10", "PC11",
384 "PC12", "PC13", "PC14",
386 allwinner,function = "mmc2";
387 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
388 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
391 uart0_pins_a: uart0@0 {
392 allwinner,pins = "PA4", "PA5";
393 allwinner,function = "uart0";
394 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
395 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
398 uart1_pins_a: uart1@0 {
399 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
400 allwinner,function = "uart1";
401 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
402 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
407 compatible = "allwinner,sun4i-a10-timer";
408 reg = <0x01c20c00 0xa0>;
409 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
414 wdt0: watchdog@01c20ca0 {
415 compatible = "allwinner,sun6i-a31-wdt";
416 reg = <0x01c20ca0 0x20>;
417 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
420 uart0: serial@01c28000 {
421 compatible = "snps,dw-apb-uart";
422 reg = <0x01c28000 0x400>;
423 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&ccu CLK_BUS_UART0>;
427 resets = <&ccu RST_BUS_UART0>;
428 dmas = <&dma 6>, <&dma 6>;
429 dma-names = "rx", "tx";
433 uart1: serial@01c28400 {
434 compatible = "snps,dw-apb-uart";
435 reg = <0x01c28400 0x400>;
436 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&ccu CLK_BUS_UART1>;
440 resets = <&ccu RST_BUS_UART1>;
441 dmas = <&dma 7>, <&dma 7>;
442 dma-names = "rx", "tx";
446 uart2: serial@01c28800 {
447 compatible = "snps,dw-apb-uart";
448 reg = <0x01c28800 0x400>;
449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&ccu CLK_BUS_UART2>;
453 resets = <&ccu RST_BUS_UART2>;
454 dmas = <&dma 8>, <&dma 8>;
455 dma-names = "rx", "tx";
459 uart3: serial@01c28c00 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0x01c28c00 0x400>;
462 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&ccu CLK_BUS_UART3>;
466 resets = <&ccu RST_BUS_UART3>;
467 dmas = <&dma 9>, <&dma 9>;
468 dma-names = "rx", "tx";
472 emac: ethernet@1c30000 {
473 compatible = "allwinner,sun8i-h3-emac";
474 reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
475 reg-names = "emac", "syscon";
476 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
477 resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
478 reset-names = "ahb", "ephy";
479 clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
480 clock-names = "ahb", "ephy";
481 #address-cells = <1>;
486 gic: interrupt-controller@01c81000 {
487 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
488 reg = <0x01c81000 0x1000>,
492 interrupt-controller;
493 #interrupt-cells = <3>;
494 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
498 compatible = "allwinner,sun6i-a31-rtc";
499 reg = <0x01f00000 0x54>;
500 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
504 apb0_reset: reset@01f014b0 {
505 reg = <0x01f014b0 0x4>;
506 compatible = "allwinner,sun6i-a31-clock-reset";
511 compatible = "allwinner,sun5i-a13-ir";
512 clocks = <&apb0_gates 1>, <&ir_clk>;
513 clock-names = "apb", "ir";
514 resets = <&apb0_reset 1>;
515 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
516 reg = <0x01f02000 0x40>;
520 r_pio: pinctrl@01f02c00 {
521 compatible = "allwinner,sun8i-h3-r-pinctrl";
522 reg = <0x01f02c00 0x400>;
523 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&apb0_gates 0>;
525 resets = <&apb0_reset 0>;
528 interrupt-controller;
529 #interrupt-cells = <3>;
532 allwinner,pins = "PL11";
533 allwinner,function = "s_cir_rx";
534 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
535 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
540 compatible = "allwinner,sun6i-a31-i2c";
541 reg = <0x01c2ac00 0x400>;
542 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&ccu CLK_BUS_I2C0>;
544 resets = <&ccu RST_BUS_I2C0>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c0_pins>;
548 #address-cells = <1>;