arch/arm/dts/uniphier-ph1-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD4 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-ld4";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         reg = <0>;
  22                         next-level-cache = <&l2>;
  23                 };
  24         };
  25
  26         clocks {
  27                 arm_timer_clk: arm_timer_clk {
  28                         #clock-cells = <0>;
  29                         compatible = "fixed-clock";
  30                         clock-frequency = <50000000>;
  31                 };
  32
  33                 iobus_clk: iobus_clk {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <100000000>;
  37                 };
  38         };
  39 };
  40
  41 &soc {
  42         l2: l2-cache@500c0000 {
  43                 compatible = "socionext,uniphier-system-cache";
  44                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  45                 interrupts = <0 174 4>, <0 175 4>;
  46                 cache-unified;
  47                 cache-size = <(512 * 1024)>;
  48                 cache-sets = <256>;
  49                 cache-line-size = <128>;
  50                 cache-level = <2>;
  51         };
  52
  53         port0x: gpio@55000008 {
  54                 compatible = "socionext,uniphier-gpio";
  55                 reg = <0x55000008 0x8>;
  56                 gpio-controller;
  57                 #gpio-cells = <2>;
  58         };
  59
  60         port1x: gpio@55000010 {
  61                 compatible = "socionext,uniphier-gpio";
  62                 reg = <0x55000010 0x8>;
  63                 gpio-controller;
  64                 #gpio-cells = <2>;
  65         };
  66
  67         port2x: gpio@55000018 {
  68                 compatible = "socionext,uniphier-gpio";
  69                 reg = <0x55000018 0x8>;
  70                 gpio-controller;
  71                 #gpio-cells = <2>;
  72         };
  73
  74         port3x: gpio@55000020 {
  75                 compatible = "socionext,uniphier-gpio";
  76                 reg = <0x55000020 0x8>;
  77                 gpio-controller;
  78                 #gpio-cells = <2>;
  79         };
  80
  81         port4: gpio@55000028 {
  82                 compatible = "socionext,uniphier-gpio";
  83                 reg = <0x55000028 0x8>;
  84                 gpio-controller;
  85                 #gpio-cells = <2>;
  86         };
  87
  88         port5x: gpio@55000030 {
  89                 compatible = "socionext,uniphier-gpio";
  90                 reg = <0x55000030 0x8>;
  91                 gpio-controller;
  92                 #gpio-cells = <2>;
  93         };
  94
  95         port6x: gpio@55000038 {
  96                 compatible = "socionext,uniphier-gpio";
  97                 reg = <0x55000038 0x8>;
  98                 gpio-controller;
  99                 #gpio-cells = <2>;
 100         };
 101
 102         port7x: gpio@55000040 {
 103                 compatible = "socionext,uniphier-gpio";
 104                 reg = <0x55000040 0x8>;
 105                 gpio-controller;
 106                 #gpio-cells = <2>;
 107         };
 108
 109         port8x: gpio@55000048 {
 110                 compatible = "socionext,uniphier-gpio";
 111                 reg = <0x55000048 0x8>;
 112                 gpio-controller;
 113                 #gpio-cells = <2>;
 114         };
 115
 116         port9x: gpio@55000050 {
 117                 compatible = "socionext,uniphier-gpio";
 118                 reg = <0x55000050 0x8>;
 119                 gpio-controller;
 120                 #gpio-cells = <2>;
 121         };
 122
 123         port10x: gpio@55000058 {
 124                 compatible = "socionext,uniphier-gpio";
 125                 reg = <0x55000058 0x8>;
 126                 gpio-controller;
 127                 #gpio-cells = <2>;
 128         };
 129
 130         port11x: gpio@55000060 {
 131                 compatible = "socionext,uniphier-gpio";
 132                 reg = <0x55000060 0x8>;
 133                 gpio-controller;
 134                 #gpio-cells = <2>;
 135         };
 136
 137         port12x: gpio@55000068 {
 138                 compatible = "socionext,uniphier-gpio";
 139                 reg = <0x55000068 0x8>;
 140                 gpio-controller;
 141                 #gpio-cells = <2>;
 142         };
 143
 144         port13x: gpio@55000070 {
 145                 compatible = "socionext,uniphier-gpio";
 146                 reg = <0x55000070 0x8>;
 147                 gpio-controller;
 148                 #gpio-cells = <2>;
 149         };
 150
 151         port14x: gpio@55000078 {
 152                 compatible = "socionext,uniphier-gpio";
 153                 reg = <0x55000078 0x8>;
 154                 gpio-controller;
 155                 #gpio-cells = <2>;
 156         };
 157
 158         port16x: gpio@55000088 {
 159                 compatible = "socionext,uniphier-gpio";
 160                 reg = <0x55000088 0x8>;
 161                 gpio-controller;
 162                 #gpio-cells = <2>;
 163         };
 164
 165         i2c0: i2c@58400000 {
 166                 compatible = "socionext,uniphier-i2c";
 167                 status = "disabled";
 168                 reg = <0x58400000 0x40>;
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 interrupts = <0 41 1>;
 172                 pinctrl-names = "default";
 173                 pinctrl-0 = <&pinctrl_i2c0>;
 174                 clocks = <&iobus_clk>;
 175                 clock-frequency = <100000>;
 176         };
 177
 178         i2c1: i2c@58480000 {
 179                 compatible = "socionext,uniphier-i2c";
 180                 status = "disabled";
 181                 reg = <0x58480000 0x40>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 interrupts = <0 42 1>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&pinctrl_i2c1>;
 187                 clocks = <&iobus_clk>;
 188                 clock-frequency = <100000>;
 189         };
 190
 191         /* chip-internal connection for DMD */
 192         i2c2: i2c@58500000 {
 193                 compatible = "socionext,uniphier-i2c";
 194                 reg = <0x58500000 0x40>;
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 interrupts = <0 43 1>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&pinctrl_i2c2>;
 200                 clocks = <&iobus_clk>;
 201                 clock-frequency = <400000>;
 202         };
 203
 204         i2c3: i2c@58580000 {
 205                 compatible = "socionext,uniphier-i2c";
 206                 status = "disabled";
 207                 reg = <0x58580000 0x40>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 interrupts = <0 44 1>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&pinctrl_i2c3>;
 213                 clocks = <&iobus_clk>;
 214                 clock-frequency = <100000>;
 215         };
 216
 217         sd: sdhc@5a400000 {
 218                 compatible = "socionext,uniphier-sdhc";
 219                 status = "disabled";
 220                 reg = <0x5a400000 0x200>;
 221                 interrupts = <0 76 4>;
 222                 pinctrl-names = "default", "1.8v";
 223                 pinctrl-0 = <&pinctrl_sd>;
 224                 pinctrl-1 = <&pinctrl_sd_1v8>;
 225                 clocks = <&mio_clk 0>;
 226                 bus-width = <4>;
 227         };
 228
 229         emmc: sdhc@5a500000 {
 230                 compatible = "socionext,uniphier-sdhc";
 231                 status = "disabled";
 232                 reg = <0x5a500000 0x200>;
 233                 interrupts = <0 78 4>;
 234                 pinctrl-names = "default", "1.8v";
 235                 pinctrl-0 = <&pinctrl_emmc>;
 236                 pinctrl-1 = <&pinctrl_emmc_1v8>;
 237                 clocks = <&mio_clk 1>;
 238                 bus-width = <8>;
 239                 non-removable;
 240         };
 241
 242         usb0: usb@5a800100 {
 243                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 244                 status = "disabled";
 245                 reg = <0x5a800100 0x100>;
 246                 interrupts = <0 80 4>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&pinctrl_usb0>;
 249                 clocks = <&mio_clk 3>, <&mio_clk 6>;
 250         };
 251
 252         usb1: usb@5a810100 {
 253                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 254                 status = "disabled";
 255                 reg = <0x5a810100 0x100>;
 256                 interrupts = <0 81 4>;
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&pinctrl_usb1>;
 259                 clocks = <&mio_clk 4>, <&mio_clk 6>;
 260         };
 261
 262         usb2: usb@5a820100 {
 263                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 264                 status = "disabled";
 265                 reg = <0x5a820100 0x100>;
 266                 interrupts = <0 82 4>;
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&pinctrl_usb2>;
 269                 clocks = <&mio_clk 5>, <&mio_clk 6>;
 270         };
 271
 272         aidet@61830000 {
 273                 compatible = "simple-mfd", "syscon";
 274                 reg = <0x61830000 0x200>;
 275         };
 276 };
 277
 278 &refclk {
 279         clock-frequency = <24576000>;
 280 };
 281
 282 &serial0 {
 283         clock-frequency = <36864000>;
 284 };
 285
 286 &serial1 {
 287         clock-frequency = <36864000>;
 288 };
 289
 290 &serial2 {
 291         clock-frequency = <36864000>;
 292 };
 293
 294 &serial3 {
 295         interrupts = <0 29 4>;
 296         clock-frequency = <36864000>;
 297 };
 298
 299 &mio_clk {
 300         compatible = "socionext,uniphier-ld4-mio-clock";
 301 };
 302
 303 &mio_rst {
 304         compatible = "socionext,uniphier-ld4-mio-reset";
 305 };
 306
 307 &peri_clk {
 308         compatible = "socionext,uniphier-ld4-peri-clock";
 309 };
 310
 311 &peri_rst {
 312         compatible = "socionext,uniphier-ld4-peri-reset";
 313 };
 314
 315 &pinctrl {
 316         compatible = "socionext,uniphier-ld4-pinctrl";
 317 };
 318
 319 &sys_clk {
 320         compatible = "socionext,uniphier-ld4-clock";
 321 };
 322
 323 &sys_rst {
 324         compatible = "socionext,uniphier-ld4-reset";
 325 };