arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 uart_clk: uart_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <36864000>;
  49                 };
  50
  51                 iobus_clk: iobus_clk {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <100000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63                 interrupt-parent = <&intc>;
  64
  65                 timer@20000200 {
  66                         compatible = "arm,cortex-a9-global-timer";
  67                         reg = <0x20000200 0x20>;
  68                         interrupts = <1 11 0x304>;
  69                         clocks = <&arm_timer_clk>;
  70                 };
  71
  72                 timer@20000600 {
  73                         compatible = "arm,cortex-a9-twd-timer";
  74                         reg = <0x20000600 0x20>;
  75                         interrupts = <1 13 0x304>;
  76                         clocks = <&arm_timer_clk>;
  77                 };
  78
  79                 intc: interrupt-controller@20001000 {
  80                         compatible = "arm,cortex-a9-gic";
  81                         #interrupt-cells = <3>;
  82                         interrupt-controller;
  83                         reg = <0x20001000 0x1000>,
  84                               <0x20000100 0x100>;
  85                 };
  86
  87                 serial0: serial@54006800 {
  88                         compatible = "socionext,uniphier-uart";
  89                         status = "disabled";
  90                         reg = <0x54006800 0x40>;
  91                         interrupts = <0 33 4>;
  92                         clocks = <&uart_clk>;
  93                         clock-frequency = <36864000>;
  94                 };
  95
  96                 serial1: serial@54006900 {
  97                         compatible = "socionext,uniphier-uart";
  98                         status = "disabled";
  99                         reg = <0x54006900 0x40>;
 100                         interrupts = <0 35 4>;
 101                         clocks = <&uart_clk>;
 102                         clock-frequency = <36864000>;
 103                 };
 104
 105                 serial2: serial@54006a00 {
 106                         compatible = "socionext,uniphier-uart";
 107                         status = "disabled";
 108                         reg = <0x54006a00 0x40>;
 109                         interrupts = <0 37 4>;
 110                         clocks = <&uart_clk>;
 111                         clock-frequency = <36864000>;
 112                 };
 113
 114                 i2c0: i2c@58400000 {
 115                         compatible = "socionext,uniphier-i2c";
 116                         status = "disabled";
 117                         reg = <0x58400000 0x40>;
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         interrupts = <0 41 1>;
 121                         clocks = <&iobus_clk>;
 122                         clock-frequency = <100000>;
 123                 };
 124
 125                 i2c1: i2c@58480000 {
 126                         compatible = "socionext,uniphier-i2c";
 127                         status = "disabled";
 128                         reg = <0x58480000 0x40>;
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         interrupts = <0 42 1>;
 132                         clocks = <&iobus_clk>;
 133                         clock-frequency = <100000>;
 134                 };
 135
 136                 i2c2: i2c@58500000 {
 137                         compatible = "socionext,uniphier-i2c";
 138                         status = "disabled";
 139                         reg = <0x58500000 0x40>;
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         interrupts = <0 43 1>;
 143                         clocks = <&iobus_clk>;
 144                         clock-frequency = <100000>;
 145                 };
 146
 147                 i2c3: i2c@58580000 {
 148                         compatible = "socionext,uniphier-i2c";
 149                         status = "disabled";
 150                         reg = <0x58580000 0x40>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         interrupts = <0 44 1>;
 154                         clocks = <&iobus_clk>;
 155                         clock-frequency = <100000>;
 156                 };
 157
 158                 /* chip-internal connection for DMD */
 159                 i2c4: i2c@58600000 {
 160                         compatible = "socionext,uniphier-i2c";
 161                         reg = <0x58600000 0x40>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         interrupts = <0 45 1>;
 165                         clocks = <&iobus_clk>;
 166                         clock-frequency = <400000>;
 167                 };
 168
 169                 system_bus: system-bus@58c00000 {
 170                         compatible = "socionext,uniphier-system-bus";
 171                         reg = <0x58c00000 0x400>;
 172                         #address-cells = <2>;
 173                         #size-cells = <1>;
 174                 };
 175
 176                 smpctrl@59800000 {
 177                         compatible = "socionext,uniphier-smpctrl";
 178                         reg = <0x59801000 0x400>;
 179                 };
 180
 181                 mio: mioctrl@59810000 {
 182                         compatible = "socionext,ph1-sld3-mioctrl";
 183                         reg = <0x59810000 0x800>;
 184                         #clock-cells = <1>;
 185                         clock-names = "stdmac", "ehci";
 186                         clocks = <&sysctrl 10>, <&sysctrl 18>;
 187                 };
 188
 189                 usb0: usb@5a800100 {
 190                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 191                         status = "disabled";
 192                         reg = <0x5a800100 0x100>;
 193                         interrupts = <0 80 4>;
 194                         clocks = <&mio 3>, <&mio 6>;
 195                 };
 196
 197                 usb1: usb@5a810100 {
 198                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 199                         status = "disabled";
 200                         reg = <0x5a810100 0x100>;
 201                         interrupts = <0 81 4>;
 202                         clocks = <&mio 4>, <&mio 6>;
 203                 };
 204
 205                 usb2: usb@5a820100 {
 206                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 207                         status = "disabled";
 208                         reg = <0x5a820100 0x100>;
 209                         interrupts = <0 82 4>;
 210                         clocks = <&mio 5>, <&mio 6>;
 211                 };
 212
 213                 usb3: usb@5a830100 {
 214                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 215                         status = "disabled";
 216                         reg = <0x5a830100 0x100>;
 217                         interrupts = <0 83 4>;
 218                         clocks = <&mio 7>, <&mio 6>;
 219                 };
 220
 221                 sysctrl: sysctrl@f1840000 {
 222                         compatible = "socionext,ph1-sld3-sysctrl";
 223                         reg = <0xf1840000 0x4000>;
 224                         #clock-cells = <1>;
 225                         clock-names = "ref";
 226                         clocks = <&refclk>;
 227                 };
 228
 229                 nand: nand@f8000000 {
 230                         compatible = "denali,denali-nand-dt";
 231                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 232                         reg-names = "nand_data", "denali_reg";
 233                 };
 234         };
 235 };