2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-pxs3";
16 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a53", "arm,armv8";
43 clocks = <&sys_clk 33>;
44 enable-method = "psci";
45 operating-points-v2 = <&cluster0_opp>;
50 compatible = "arm,cortex-a53", "arm,armv8";
52 clocks = <&sys_clk 33>;
53 enable-method = "psci";
54 operating-points-v2 = <&cluster0_opp>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 clocks = <&sys_clk 33>;
62 enable-method = "psci";
63 operating-points-v2 = <&cluster0_opp>;
68 compatible = "arm,cortex-a53", "arm,armv8";
70 clocks = <&sys_clk 33>;
71 enable-method = "psci";
72 operating-points-v2 = <&cluster0_opp>;
76 cluster0_opp: opp_table {
77 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <250000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <325000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <500000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <650000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <666667000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <866667000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1000000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <1300000000>;
110 clock-latency-ns = <300>;
115 compatible = "arm,psci-1.0";
121 compatible = "fixed-clock";
123 clock-frequency = <25000000>;
128 compatible = "arm,armv8-timer";
129 interrupts = <1 13 4>,
136 compatible = "simple-bus";
137 #address-cells = <1>;
139 ranges = <0 0 0 0xffffffff>;
141 serial0: serial@54006800 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006800 0x40>;
145 interrupts = <0 33 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
148 clocks = <&peri_clk 0>;
149 clock-frequency = <58820000>;
152 serial1: serial@54006900 {
153 compatible = "socionext,uniphier-uart";
155 reg = <0x54006900 0x40>;
156 interrupts = <0 35 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
159 clocks = <&peri_clk 1>;
160 clock-frequency = <58820000>;
163 serial2: serial@54006a00 {
164 compatible = "socionext,uniphier-uart";
166 reg = <0x54006a00 0x40>;
167 interrupts = <0 37 4>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 clocks = <&peri_clk 2>;
171 clock-frequency = <58820000>;
174 serial3: serial@54006b00 {
175 compatible = "socionext,uniphier-uart";
177 reg = <0x54006b00 0x40>;
178 interrupts = <0 177 4>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
181 clocks = <&peri_clk 3>;
182 clock-frequency = <58820000>;
185 gpio: gpio@55000000 {
186 compatible = "socionext,uniphier-gpio";
187 reg = <0x55000000 0x200>;
188 interrupt-parent = <&aidet>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 gpio-ranges = <&pinctrl 0 0 0>,
196 gpio-ranges-group-names = "gpio_range0",
203 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58780000 0x80>;
206 #address-cells = <1>;
208 interrupts = <0 41 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c0>;
211 clocks = <&peri_clk 4>;
212 clock-frequency = <100000>;
216 compatible = "socionext,uniphier-fi2c";
218 reg = <0x58781000 0x80>;
219 #address-cells = <1>;
221 interrupts = <0 42 4>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c1>;
224 clocks = <&peri_clk 5>;
225 clock-frequency = <100000>;
229 compatible = "socionext,uniphier-fi2c";
231 reg = <0x58782000 0x80>;
232 #address-cells = <1>;
234 interrupts = <0 43 4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_i2c2>;
237 clocks = <&peri_clk 6>;
238 clock-frequency = <100000>;
242 compatible = "socionext,uniphier-fi2c";
244 reg = <0x58783000 0x80>;
245 #address-cells = <1>;
247 interrupts = <0 44 4>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_i2c3>;
250 clocks = <&peri_clk 7>;
251 clock-frequency = <100000>;
254 /* chip-internal connection for HDMI */
256 compatible = "socionext,uniphier-fi2c";
257 reg = <0x58786000 0x80>;
258 #address-cells = <1>;
260 interrupts = <0 26 4>;
261 clocks = <&peri_clk 10>;
262 clock-frequency = <400000>;
265 system_bus: system-bus@58c00000 {
266 compatible = "socionext,uniphier-system-bus";
268 reg = <0x58c00000 0x400>;
269 #address-cells = <2>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_system_bus>;
276 compatible = "socionext,uniphier-smpctrl";
277 reg = <0x59801000 0x400>;
281 compatible = "socionext,uniphier-pxs3-sdctrl",
282 "simple-mfd", "syscon";
283 reg = <0x59810000 0x400>;
286 compatible = "socionext,uniphier-pxs3-sd-clock";
291 compatible = "socionext,uniphier-pxs3-sd-reset";
297 compatible = "socionext,uniphier-pxs3-perictrl",
298 "simple-mfd", "syscon";
299 reg = <0x59820000 0x200>;
302 compatible = "socionext,uniphier-pxs3-peri-clock";
307 compatible = "socionext,uniphier-pxs3-peri-reset";
312 emmc: sdhc@5a000000 {
313 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
314 reg = <0x5a000000 0x400>;
315 interrupts = <0 78 4>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_emmc_1v8>;
318 clocks = <&sys_clk 4>;
322 cdns,phy-input-delay-legacy = <4>;
323 cdns,phy-input-delay-mmc-highspeed = <2>;
324 cdns,phy-input-delay-mmc-ddr = <3>;
325 cdns,phy-dll-delay-sdclk = <21>;
326 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
330 compatible = "socionext,uniphier-sdhc";
332 reg = <0x5a400000 0x800>;
333 interrupts = <0 76 4>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_sd>;
336 clocks = <&sd_clk 0>;
337 reset-names = "host";
338 resets = <&sd_rst 0>;
344 compatible = "socionext,uniphier-pxs3-soc-glue",
345 "simple-mfd", "syscon";
346 reg = <0x5f800000 0x2000>;
349 compatible = "socionext,uniphier-pxs3-pinctrl";
353 aidet: aidet@5fc20000 {
354 compatible = "socionext,uniphier-pxs3-aidet";
355 reg = <0x5fc20000 0x200>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 gic: interrupt-controller@5fe00000 {
361 compatible = "arm,gic-v3";
362 reg = <0x5fe00000 0x10000>, /* GICD */
363 <0x5fe80000 0x80000>; /* GICR */
364 interrupt-controller;
365 #interrupt-cells = <3>;
366 interrupts = <1 9 4>;
370 compatible = "socionext,uniphier-pxs3-sysctrl",
371 "simple-mfd", "syscon";
372 reg = <0x61840000 0x10000>;
375 compatible = "socionext,uniphier-pxs3-clock";
380 compatible = "socionext,uniphier-pxs3-reset";
385 compatible = "socionext,uniphier-wdt";
390 compatible = "socionext,uniphier-pxs3-dwc3";
392 reg = <0x65b00000 0x1000>;
393 #address-cells = <1>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
399 compatible = "snps,dwc3";
400 reg = <0x65a00000 0x10000>;
401 interrupts = <0 134 4>;
408 compatible = "socionext,uniphier-pxs3-dwc3";
410 reg = <0x65d00000 0x1000>;
411 #address-cells = <1>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
417 compatible = "snps,dwc3";
418 reg = <0x65c00000 0x10000>;
419 interrupts = <0 137 4>;
425 nand: nand@68000000 {
426 compatible = "socionext,uniphier-denali-nand-v5b";
428 reg-names = "nand_data", "denali_reg";
429 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
430 interrupts = <0 65 4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_nand>;
433 clocks = <&sys_clk 2>;
438 #include "uniphier-pinctrl.dtsi"