arch/arm/dts/zynqmp-ep108.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ep108 development board
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-ep108-clk.dtsi"
  15
  16 / {
  17         model = "ZynqMP EP108";
  18
  19         aliases {
  20                 ethernet0 = &gem0;
  21                 mmc0 = &sdhci0;
  22                 mmc1 = &sdhci1;
  23                 serial0 = &uart0;
  24                 spi0 = &qspi;
  25                 spi1 = &spi0;
  26                 spi2 = &spi1;
  27                 usb0 = &usb0;
  28                 usb1 = &usb1;
  29         };
  30
  31         chosen {
  32                 bootargs = "earlycon";
  33                 stdout-path = "serial0:115200n8";
  34         };
  35
  36         memory@0 {
  37                 device_type = "memory";
  38                 reg = <0x0 0x0 0x0 0x40000000>;
  39         };
  40 };
  41
  42 &can0 {
  43         status = "okay";
  44 };
  45
  46 &can1 {
  47         status = "okay";
  48 };
  49
  50 &gem0 {
  51         status = "okay";
  52         phy-handle = <&phy0>;
  53         phy-mode = "rgmii-id";
  54         phy0: phy@0 {
  55                 reg = <0>;
  56                 max-speed = <100>;
  57         };
  58 };
  59
  60 &gpio {
  61         status = "okay";
  62 };
  63
  64 &i2c0 {
  65         status = "okay";
  66         clock-frequency = <400000>;
  67         eeprom@54 {
  68                 compatible = "at,24c64";
  69                 reg = <0x54>;
  70         };
  71 };
  72
  73 &i2c1 {
  74         status = "okay";
  75         clock-frequency = <400000>;
  76         eeprom@55 {
  77                 compatible = "at,24c64";
  78                 reg = <0x55>;
  79         };
  80 };
  81
  82 &nand0 {
  83         status = "okay";
  84         arasan,has-mdma;
  85         num-cs = <1>;
  86
  87         partition@0 {   /* for testing purpose */
  88                 label = "nand-fsbl-uboot";
  89                 reg = <0x0 0x0 0x400000>;
  90         };
  91         partition@1 {   /* for testing purpose */
  92                 label = "nand-linux";
  93                 reg = <0x0 0x400000 0x1400000>;
  94         };
  95         partition@2 {   /* for testing purpose */
  96                 label = "nand-device-tree";
  97                 reg = <0x0 0x1800000 0x400000>;
  98         };
  99         partition@3 {   /* for testing purpose */
 100                 label = "nand-rootfs";
 101                 reg = <0x0 0x1C00000 0x1400000>;
 102         };
 103         partition@4 {   /* for testing purpose */
 104                 label = "nand-bitstream";
 105                 reg = <0x0 0x3000000 0x400000>;
 106         };
 107         partition@5 {   /* for testing purpose */
 108                 label = "nand-misc";
 109                 reg = <0x0 0x3400000 0xFCC00000>;
 110         };
 111 };
 112
 113 &qspi {
 114         status = "okay";
 115         flash@0 {
 116                 compatible = "m25p80";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 reg = <0x0>;
 120                 spi-tx-bus-width = <1>;
 121                 spi-rx-bus-width = <4>;
 122                 spi-max-frequency = <10000000>;
 123                 partition@qspi-fsbl-uboot { /* for testing purpose */
 124                         label = "qspi-fsbl-uboot";
 125                         reg = <0x0 0x100000>;
 126                 };
 127                 partition@qspi-linux { /* for testing purpose */
 128                         label = "qspi-linux";
 129                         reg = <0x100000 0x500000>;
 130                 };
 131                 partition@qspi-device-tree { /* for testing purpose */
 132                         label = "qspi-device-tree";
 133                         reg = <0x600000 0x20000>;
 134                 };
 135                 partition@qspi-rootfs { /* for testing purpose */
 136                         label = "qspi-rootfs";
 137                         reg = <0x620000 0x5E0000>;
 138                 };
 139         };
 140 };
 141
 142 &sata {
 143         status = "okay";
 144         ceva,broken-gen2;
 145         /* SATA Phy OOB timing settings */
 146         ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
 147         ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
 148         ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
 149         ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
 150         ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
 151         ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
 152         ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
 153         ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 154 };
 155
 156 &sdhci0 {
 157         status = "okay";
 158         bus-width = <8>;
 159         xlnx,mio_bank = <2>;
 160 };
 161
 162 &sdhci1 {
 163         status = "okay";
 164         xlnx,mio_bank = <1>;
 165 };
 166
 167 &spi0 {
 168         status = "okay";
 169         num-cs = <1>;
 170         spi0_flash0: spi0_flash0@0 {
 171                 compatible = "m25p80";
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 spi-max-frequency = <50000000>;
 175                 reg = <0>;
 176
 177                 spi0_flash0@0 {
 178                         label = "spi0_flash0";
 179                         reg = <0x0 0x100000>;
 180                 };
 181         };
 182 };
 183
 184 &spi1 {
 185         status = "okay";
 186         num-cs = <1>;
 187         spi1_flash0: spi1_flash0@0 {
 188                 compatible = "m25p80";
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191                 spi-max-frequency = <50000000>;
 192                 reg = <0>;
 193
 194                 spi1_flash0@0 {
 195                         label = "spi1_flash0";
 196                         reg = <0x0 0x100000>;
 197                 };
 198         };
 199 };
 200
 201 &uart0 {
 202         status = "okay";
 203 };
 204
 205 &usb0 {
 206         status = "okay";
 207 };
 208
 209 &dwc3_0 {
 210         status = "okay";
 211         dr_mode = "peripheral";
 212         maximum-speed = "high-speed";
 213 };
 214
 215 &usb1 {
 216         status = "okay";
 217 };
 218
 219 &dwc3_1 {
 220         status = "okay";
 221         dr_mode = "host";
 222         maximum-speed = "high-speed";
 223 };
 224
 225 &watchdog0 {
 226         status = "okay";
 227 };
 228
 229 &xlnx_dp {
 230         xlnx,max-pclock-frequency = <200000>;
 231 };
 232
 233 &xlnx_dpdma {
 234         xlnx,axi-clock-freq = <200000000>;
 235 };