arch/arm/imx-common/cpu.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <ipu_pixfmt.h>
  18
  19 #ifdef CONFIG_FSL_ESDHC
  20 #include <fsl_esdhc.h>
  21 #endif
  22
  23 char *get_reset_cause(void)
  24 {
  25         u32 cause;
  26         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  27
  28         cause = readl(&src_regs->srsr);
  29         writel(cause, &src_regs->srsr);
  30
  31         switch (cause) {
  32         case 0x00001:
  33         case 0x00011:
  34                 return "POR";
  35         case 0x00004:
  36                 return "CSU";
  37         case 0x00008:
  38                 return "IPP USER";
  39         case 0x00010:
  40                 return "WDOG";
  41         case 0x00020:
  42                 return "JTAG HIGH-Z";
  43         case 0x00040:
  44                 return "JTAG SW";
  45         case 0x10000:
  46                 return "WARM BOOT";
  47         default:
  48                 return "unknown reset";
  49         }
  50 }
  51
  52 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  53 #if defined(CONFIG_MX53)
  54 #define MEMCTL_BASE     ESDCTL_BASE_ADDR;
  55 #else
  56 #define MEMCTL_BASE     MMDC_P0_BASE_ADDR;
  57 #endif
  58 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  59 static const unsigned char bank_lookup[] = {3, 2};
  60
  61 struct esd_mmdc_regs {
  62         uint32_t        ctl;
  63         uint32_t        pdc;
  64         uint32_t        otc;
  65         uint32_t        cfg0;
  66         uint32_t        cfg1;
  67         uint32_t        cfg2;
  68         uint32_t        misc;
  69         uint32_t        scr;
  70         uint32_t        ref;
  71         uint32_t        rsvd1;
  72         uint32_t        rsvd2;
  73         uint32_t        rwd;
  74         uint32_t        or;
  75         uint32_t        mrr;
  76         uint32_t        cfg3lp;
  77         uint32_t        mr4;
  78 };
  79
  80 #define ESD_MMDC_CTL_GET_ROW(mdctl)     ((ctl >> 24) & 7)
  81 #define ESD_MMDC_CTL_GET_COLUMN(mdctl)  ((ctl >> 20) & 7)
  82 #define ESD_MMDC_CTL_GET_WIDTH(mdctl)   ((ctl >> 16) & 3)
  83 #define ESD_MMDC_CTL_GET_CS1(mdctl)     ((ctl >> 30) & 1)
  84 #define ESD_MMDC_MISC_GET_BANK(mdmisc)  ((misc >> 5) & 1)
  85
  86 unsigned imx_ddr_size(void)
  87 {
  88         struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
  89         unsigned ctl = readl(&mem->ctl);
  90         unsigned misc = readl(&mem->misc);
  91         int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
  92
  93         bits += ESD_MMDC_CTL_GET_ROW(ctl);
  94         bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
  95         bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
  96         bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
  97         bits += ESD_MMDC_CTL_GET_CS1(ctl);
  98         return 1 << bits;
  99 }
 100 #endif
 101
 102 #if defined(CONFIG_DISPLAY_CPUINFO)
 103
 104 const char *get_imx_type(u32 imxtype)
 105 {
 106         switch (imxtype) {
 107         case MXC_CPU_MX6Q:
 108                 return "6Q";    /* Quad-core version of the mx6 */
 109         case MXC_CPU_MX6DL:
 110                 return "6DL";   /* Dual Lite version of the mx6 */
 111         case MXC_CPU_MX6SOLO:
 112                 return "6SOLO"; /* Solo version of the mx6 */
 113         case MXC_CPU_MX6SL:
 114                 return "6SL";   /* Solo-Lite version of the mx6 */
 115         case MXC_CPU_MX51:
 116                 return "51";
 117         case MXC_CPU_MX53:
 118                 return "53";
 119         default:
 120                 return "??";
 121         }
 122 }
 123
 124 int print_cpuinfo(void)
 125 {
 126         u32 cpurev;
 127
 128         cpurev = get_cpu_rev();
 129
 130         printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
 131                 get_imx_type((cpurev & 0xFF000) >> 12),
 132                 (cpurev & 0x000F0) >> 4,
 133                 (cpurev & 0x0000F) >> 0,
 134                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 135         printf("Reset cause: %s\n", get_reset_cause());
 136         return 0;
 137 }
 138 #endif
 139
 140 int cpu_eth_init(bd_t *bis)
 141 {
 142         int rc = -ENODEV;
 143
 144 #if defined(CONFIG_FEC_MXC)
 145         rc = fecmxc_initialize(bis);
 146 #endif
 147
 148         return rc;
 149 }
 150
 151 #ifdef CONFIG_FSL_ESDHC
 152 /*
 153  * Initializes on-chip MMC controllers.
 154  * to override, implement board_mmc_init()
 155  */
 156 int cpu_mmc_init(bd_t *bis)
 157 {
 158         return fsl_esdhc_mmc_init(bis);
 159 }
 160 #endif
 161
 162 u32 get_ahb_clk(void)
 163 {
 164         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 165         u32 reg, ahb_podf;
 166
 167         reg = __raw_readl(&imx_ccm->cbcdr);
 168         reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
 169         ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 170
 171         return get_periph_clk() / (ahb_podf + 1);
 172 }
 173
 174 #if defined(CONFIG_VIDEO_IPUV3)
 175 void arch_preboot_os(void)
 176 {
 177         /* disable video before launching O/S */
 178         ipuv3_fb_shutdown();
 179 }
 180 #endif