arch/arm/imx-common/cpu.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <bootm.h>
  11 #include <common.h>
  12 #include <netdev.h>
  13 #include <asm/errno.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <imx_thermal.h>
  20 #include <ipu_pixfmt.h>
  21 #include <thermal.h>
  22 #include <sata.h>
  23
  24 #ifdef CONFIG_FSL_ESDHC
  25 #include <fsl_esdhc.h>
  26 #endif
  27
  28 #if defined(CONFIG_DISPLAY_CPUINFO)
  29 static u32 reset_cause = -1;
  30
  31 static char *get_reset_cause(void)
  32 {
  33         u32 cause;
  34         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  35
  36         cause = readl(&src_regs->srsr);
  37         writel(cause, &src_regs->srsr);
  38         reset_cause = cause;
  39
  40         switch (cause) {
  41         case 0x00001:
  42         case 0x00011:
  43                 return "POR";
  44         case 0x00004:
  45                 return "CSU";
  46         case 0x00008:
  47                 return "IPP USER";
  48         case 0x00010:
  49 #ifdef  CONFIG_MX7
  50                 return "WDOG1";
  51 #else
  52                 return "WDOG";
  53 #endif
  54         case 0x00020:
  55                 return "JTAG HIGH-Z";
  56         case 0x00040:
  57                 return "JTAG SW";
  58         case 0x00080:
  59                 return "WDOG3";
  60 #ifdef CONFIG_MX7
  61         case 0x00100:
  62                 return "WDOG4";
  63         case 0x00200:
  64                 return "TEMPSENSE";
  65 #else
  66         case 0x00100:
  67                 return "TEMPSENSE";
  68         case 0x10000:
  69                 return "WARM BOOT";
  70 #endif
  71         default:
  72                 return "unknown reset";
  73         }
  74 }
  75
  76 u32 get_imx_reset_cause(void)
  77 {
  78         return reset_cause;
  79 }
  80 #endif
  81
  82 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  83 #if defined(CONFIG_MX53)
  84 #define MEMCTL_BASE     ESDCTL_BASE_ADDR
  85 #else
  86 #define MEMCTL_BASE     MMDC_P0_BASE_ADDR
  87 #endif
  88 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  89 static const unsigned char bank_lookup[] = {3, 2};
  90
  91 /* these MMDC registers are common to the IMX53 and IMX6 */
  92 struct esd_mmdc_regs {
  93         uint32_t        ctl;
  94         uint32_t        pdc;
  95         uint32_t        otc;
  96         uint32_t        cfg0;
  97         uint32_t        cfg1;
  98         uint32_t        cfg2;
  99         uint32_t        misc;
 100 };
 101
 102 #define ESD_MMDC_CTL_GET_ROW(mdctl)     ((ctl >> 24) & 7)
 103 #define ESD_MMDC_CTL_GET_COLUMN(mdctl)  ((ctl >> 20) & 7)
 104 #define ESD_MMDC_CTL_GET_WIDTH(mdctl)   ((ctl >> 16) & 3)
 105 #define ESD_MMDC_CTL_GET_CS1(mdctl)     ((ctl >> 30) & 1)
 106 #define ESD_MMDC_MISC_GET_BANK(mdmisc)  ((misc >> 5) & 1)
 107
 108 /*
 109  * imx_ddr_size - return size in bytes of DRAM according MMDC config
 110  * The MMDC MDCTL register holds the number of bits for row, col, and data
 111  * width and the MMDC MDMISC register holds the number of banks. Combine
 112  * all these bits to determine the meme size the MMDC has been configured for
 113  */
 114 unsigned imx_ddr_size(void)
 115 {
 116         struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
 117         unsigned ctl = readl(&mem->ctl);
 118         unsigned misc = readl(&mem->misc);
 119         int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
 120
 121         bits += ESD_MMDC_CTL_GET_ROW(ctl);
 122         bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
 123         bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
 124         bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
 125         bits += ESD_MMDC_CTL_GET_CS1(ctl);
 126
 127         /* The MX6 can do only 3840 MiB of DRAM */
 128         if (bits == 32)
 129                 return 0xf0000000;
 130
 131         return 1 << bits;
 132 }
 133 #endif
 134
 135 #if defined(CONFIG_DISPLAY_CPUINFO)
 136
 137 const char *get_imx_type(u32 imxtype)
 138 {
 139         switch (imxtype) {
 140         case MXC_CPU_MX7D:
 141                 return "7D";    /* Dual-core version of the mx7 */
 142         case MXC_CPU_MX6QP:
 143                 return "6QP";   /* Quad-Plus version of the mx6 */
 144         case MXC_CPU_MX6DP:
 145                 return "6DP";   /* Dual-Plus version of the mx6 */
 146         case MXC_CPU_MX6Q:
 147                 return "6Q";    /* Quad-core version of the mx6 */
 148         case MXC_CPU_MX6D:
 149                 return "6D";    /* Dual-core version of the mx6 */
 150         case MXC_CPU_MX6DL:
 151                 return "6DL";   /* Dual Lite version of the mx6 */
 152         case MXC_CPU_MX6SOLO:
 153                 return "6SOLO"; /* Solo version of the mx6 */
 154         case MXC_CPU_MX6SL:
 155                 return "6SL";   /* Solo-Lite version of the mx6 */
 156         case MXC_CPU_MX6SX:
 157                 return "6SX";   /* SoloX version of the mx6 */
 158         case MXC_CPU_MX6UL:
 159                 return "6UL";   /* Ultra-Lite version of the mx6 */
 160         case MXC_CPU_MX51:
 161                 return "51";
 162         case MXC_CPU_MX53:
 163                 return "53";
 164         default:
 165                 return "??";
 166         }
 167 }
 168
 169 int print_cpuinfo(void)
 170 {
 171         u32 cpurev;
 172         __maybe_unused u32 max_freq;
 173
 174         cpurev = get_cpu_rev();
 175
 176 #if defined(CONFIG_IMX_THERMAL)
 177         struct udevice *thermal_dev;
 178         int cpu_tmp, minc, maxc, ret;
 179
 180         printf("CPU:   Freescale i.MX%s rev%d.%d",
 181                get_imx_type((cpurev & 0xFF000) >> 12),
 182                (cpurev & 0x000F0) >> 4,
 183                (cpurev & 0x0000F) >> 0);
 184         max_freq = get_cpu_speed_grade_hz();
 185         if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
 186                 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
 187         } else {
 188                 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
 189                        mxc_get_clock(MXC_ARM_CLK) / 1000000);
 190         }
 191 #else
 192         printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
 193                 get_imx_type((cpurev & 0xFF000) >> 12),
 194                 (cpurev & 0x000F0) >> 4,
 195                 (cpurev & 0x0000F) >> 0,
 196                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 197 #endif
 198
 199 #if defined(CONFIG_IMX_THERMAL)
 200         puts("CPU:   ");
 201         switch (get_cpu_temp_grade(&minc, &maxc)) {
 202         case TEMP_AUTOMOTIVE:
 203                 puts("Automotive temperature grade ");
 204                 break;
 205         case TEMP_INDUSTRIAL:
 206                 puts("Industrial temperature grade ");
 207                 break;
 208         case TEMP_EXTCOMMERCIAL:
 209                 puts("Extended Commercial temperature grade ");
 210                 break;
 211         default:
 212                 puts("Commercial temperature grade ");
 213                 break;
 214         }
 215         printf("(%dC to %dC)", minc, maxc);
 216         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 217         if (!ret) {
 218                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 219
 220                 if (!ret)
 221                         printf(" at %dC\n", cpu_tmp);
 222                 else
 223                         debug(" - invalid sensor data\n");
 224         } else {
 225                 debug(" - invalid sensor device\n");
 226         }
 227 #endif
 228
 229         printf("Reset cause: %s\n", get_reset_cause());
 230         return 0;
 231 }
 232 #endif
 233
 234 int cpu_eth_init(bd_t *bis)
 235 {
 236         int rc = -ENODEV;
 237
 238 #if defined(CONFIG_FEC_MXC)
 239         rc = fecmxc_initialize(bis);
 240 #endif
 241
 242         return rc;
 243 }
 244
 245 #ifdef CONFIG_FSL_ESDHC
 246 /*
 247  * Initializes on-chip MMC controllers.
 248  * to override, implement board_mmc_init()
 249  */
 250 int cpu_mmc_init(bd_t *bis)
 251 {
 252         return fsl_esdhc_mmc_init(bis);
 253 }
 254 #endif
 255
 256 #ifndef CONFIG_MX7
 257 u32 get_ahb_clk(void)
 258 {
 259         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 260         u32 reg, ahb_podf;
 261
 262         reg = __raw_readl(&imx_ccm->cbcdr);
 263         reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
 264         ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 265
 266         return get_periph_clk() / (ahb_podf + 1);
 267 }
 268 #endif
 269
 270 void arch_preboot_os(void)
 271 {
 272 #if defined(CONFIG_CMD_SATA)
 273         sata_stop();
 274 #if defined(CONFIG_MX6)
 275         disable_sata_clock();
 276 #endif
 277 #endif
 278 #if defined(CONFIG_VIDEO_IPUV3)
 279         /* disable video before launching O/S */
 280         ipuv3_fb_shutdown();
 281 #endif
 282 }
 283
 284 void set_chipselect_size(int const cs_size)
 285 {
 286         unsigned int reg;
 287         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 288         reg = readl(&iomuxc_regs->gpr[1]);
 289
 290         switch (cs_size) {
 291         case CS0_128:
 292                 reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
 293                 reg |= 0x5;
 294                 break;
 295         case CS0_64M_CS1_64M:
 296                 reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 297                 reg |= 0x1B;
 298                 break;
 299         case CS0_64M_CS1_32M_CS2_32M:
 300                 reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 301                 reg |= 0x4B;
 302                 break;
 303         case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 304                 reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 305                 reg |= 0x249;
 306                 break;
 307         default:
 308                 printf("Unknown chip select size: %d\n", cs_size);
 309                 break;
 310         }
 311
 312         writel(reg, &iomuxc_regs->gpr[1]);
 313 }