]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/imx-common/imx_bootaux.c
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Allow for arch specific config before we boot */
11 static int __arch_auxiliary_core_up(u32 core_id
, u32 boot_private_data
)
13 /* please define platform specific arch_auxiliary_core_up() */
14 return CMD_RET_FAILURE
;
17 int arch_auxiliary_core_up(u32 core_id
, u32 boot_private_data
)
18 __attribute__((weak
, alias("__arch_auxiliary_core_up")));
20 /* Allow for arch specific config before we boot */
21 static int __arch_auxiliary_core_check_up(u32 core_id
)
23 /* please define platform specific arch_auxiliary_core_check_up() */
27 int arch_auxiliary_core_check_up(u32 core_id
)
28 __attribute__((weak
, alias("__arch_auxiliary_core_check_up")));
31 * To i.MX6SX and i.MX7D, the image supported by bootaux needs
32 * the reset vector at the head for the image, with SP and PC
33 * as the first two words.
35 * Per the cortex-M reference manual, the reset vector of M4 needs
36 * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
37 * of that vector. So to boot M4, the A core must build the M4's reset
38 * vector with getting the PC and SP from image and filling them to
39 * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
40 * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
41 * accessing the M4 TCMUL.
43 int do_bootaux(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
51 up
= arch_auxiliary_core_check_up(0);
53 printf("## Auxiliary core is already up\n");
54 return CMD_RET_SUCCESS
;
57 addr
= simple_strtoul(argv
[1], NULL
, 16);
59 printf("## Starting auxiliary core at 0x%08lX ...\n", addr
);
61 ret
= arch_auxiliary_core_up(0, addr
);
63 return CMD_RET_FAILURE
;
65 return CMD_RET_SUCCESS
;
69 bootaux
, CONFIG_SYS_MAXARGS
, 1, do_bootaux
,
70 "Start auxiliary core",