arch/arm/include/asm/arch-am33xx/cpu.h

   1 /*
   2  * cpu.h
   3  *
   4  * AM33xx specific header file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _AM33XX_CPU_H
  12 #define _AM33XX_CPU_H
  13
  14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  15 #include <asm/types.h>
  16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  17
  18 #include <asm/arch/hardware.h>
  19
  20 #define CL_BIT(x)                       (0 << x)
  21
  22 /* Timer register bits */
  23 #define TCLR_ST                         BIT(0)  /* Start=1 Stop=0 */
  24 #define TCLR_AR                         BIT(1)  /* Auto reload */
  25 #define TCLR_PRE                        BIT(5)  /* Pre-scaler enable */
  26 #define TCLR_PTV_SHIFT                  (2)     /* Pre-scaler shift value */
  27 #define TCLR_PRE_DISABLE                CL_BIT(5) /* Pre-scalar disable */
  28 #define TCLR_CE                         BIT(6)  /* compare mode enable */
  29 #define TCLR_SCPWM                      BIT(7)  /* pwm outpin behaviour */
  30 #define TCLR_TCM                        BIT(8)  /* edge detection of input pin*/
  31 #define TCLR_TRG_SHIFT                  (10)    /* trigmode on pwm outpin */
  32 #define TCLR_PT                         BIT(12) /* pulse/toggle mode of outpin*/
  33 #define TCLR_CAPTMODE                   BIT(13) /* capture mode */
  34 #define TCLR_GPOCFG                     BIT(14) /* 0=output,1=input */
  35
  36 #define TCFG_RESET                      BIT(0)  /* software reset */
  37 #define TCFG_EMUFREE                    BIT(1)  /* behaviour of tmr on debug */
  38 #define TCFG_IDLEMOD_SHIFT              (2)     /* power management */
  39 /* device type */
  40 #define DEVICE_MASK                     (BIT(8) | BIT(9) | BIT(10))
  41 #define TST_DEVICE                      0x0
  42 #define EMU_DEVICE                      0x1
  43 #define HS_DEVICE                       0x2
  44 #define GP_DEVICE                       0x3
  45
  46 /* cpu-id for AM43XX AM33XX and TI81XX family */
  47 #define AM437X                          0xB98C
  48 #define AM335X                          0xB944
  49 #define TI81XX                          0xB81E
  50 #define DEVICE_ID                       (CTRL_BASE + 0x0600)
  51 #define DEVICE_ID_MASK                  0x1FFF
  52
  53 /* MPU max frequencies */
  54 #define AM335X_ZCZ_300                  0x1FEF
  55 #define AM335X_ZCZ_600                  0x1FAF
  56 #define AM335X_ZCZ_720                  0x1F2F
  57 #define AM335X_ZCZ_800                  0x1E2F
  58 #define AM335X_ZCZ_1000                 0x1C2F
  59 #define AM335X_ZCE_300                  0x1FDF
  60 #define AM335X_ZCE_600                  0x1F9F
  61
  62 /* This gives the status of the boot mode pins on the evm */
  63 #define SYSBOOT_MASK                    (BIT(0) | BIT(1) | BIT(2)\
  64                                         | BIT(3) | BIT(4))
  65
  66 #define PRM_RSTCTRL_RESET               0x01
  67 #define PRM_RSTST_WARM_RESET_MASK       0x232
  68
  69 #ifndef __KERNEL_STRICT_NAMES
  70 #ifndef __ASSEMBLY__
  71 #include <asm/ti-common/omap_wdt.h>
  72
  73 #ifndef CONFIG_AM43XX
  74 /* Encapsulating core pll registers */
  75 struct cm_wkuppll {
  76         unsigned int wkclkstctrl;       /* offset 0x00 */
  77         unsigned int wkctrlclkctrl;     /* offset 0x04 */
  78         unsigned int wkgpio0clkctrl;    /* offset 0x08 */
  79         unsigned int wkl4wkclkctrl;     /* offset 0x0c */
  80         unsigned int timer0clkctrl;     /* offset 0x10 */
  81         unsigned int resv2[3];
  82         unsigned int idlestdpllmpu;     /* offset 0x20 */
  83         unsigned int sscdeltamstepdllmpu; /* off  0x24 */
  84         unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
  85         unsigned int clkseldpllmpu;     /* offset 0x2c */
  86         unsigned int resv4[1];
  87         unsigned int idlestdpllddr;     /* offset 0x34 */
  88         unsigned int resv5[2];
  89         unsigned int clkseldpllddr;     /* offset 0x40 */
  90         unsigned int resv6[4];
  91         unsigned int clkseldplldisp;    /* offset 0x54 */
  92         unsigned int resv7[1];
  93         unsigned int idlestdpllcore;    /* offset 0x5c */
  94         unsigned int resv8[2];
  95         unsigned int clkseldpllcore;    /* offset 0x68 */
  96         unsigned int resv9[1];
  97         unsigned int idlestdpllper;     /* offset 0x70 */
  98         unsigned int resv10[2];
  99         unsigned int clkdcoldodpllper;  /* offset 0x7c */
 100         unsigned int divm4dpllcore;     /* offset 0x80 */
 101         unsigned int divm5dpllcore;     /* offset 0x84 */
 102         unsigned int clkmoddpllmpu;     /* offset 0x88 */
 103         unsigned int clkmoddpllper;     /* offset 0x8c */
 104         unsigned int clkmoddpllcore;    /* offset 0x90 */
 105         unsigned int clkmoddpllddr;     /* offset 0x94 */
 106         unsigned int clkmoddplldisp;    /* offset 0x98 */
 107         unsigned int clkseldpllper;     /* offset 0x9c */
 108         unsigned int divm2dpllddr;      /* offset 0xA0 */
 109         unsigned int divm2dplldisp;     /* offset 0xA4 */
 110         unsigned int divm2dpllmpu;      /* offset 0xA8 */
 111         unsigned int divm2dpllper;      /* offset 0xAC */
 112         unsigned int resv11[1];
 113         unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
 114         unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
 115         unsigned int wkup_adctscctrl;   /* offset 0xBC */
 116         unsigned int resv12;
 117         unsigned int timer1clkctrl;     /* offset 0xC4 */
 118         unsigned int resv13[4];
 119         unsigned int divm6dpllcore;     /* offset 0xD8 */
 120 };
 121
 122 /**
 123  * Encapsulating peripheral functional clocks
 124  * pll registers
 125  */
 126 struct cm_perpll {
 127         unsigned int l4lsclkstctrl;     /* offset 0x00 */
 128         unsigned int l3sclkstctrl;      /* offset 0x04 */
 129         unsigned int l4fwclkstctrl;     /* offset 0x08 */
 130         unsigned int l3clkstctrl;       /* offset 0x0c */
 131         unsigned int resv1;
 132         unsigned int cpgmac0clkctrl;    /* offset 0x14 */
 133         unsigned int lcdclkctrl;        /* offset 0x18 */
 134         unsigned int usb0clkctrl;       /* offset 0x1C */
 135         unsigned int resv2;
 136         unsigned int tptc0clkctrl;      /* offset 0x24 */
 137         unsigned int emifclkctrl;       /* offset 0x28 */
 138         unsigned int ocmcramclkctrl;    /* offset 0x2c */
 139         unsigned int gpmcclkctrl;       /* offset 0x30 */
 140         unsigned int mcasp0clkctrl;     /* offset 0x34 */
 141         unsigned int uart5clkctrl;      /* offset 0x38 */
 142         unsigned int mmc0clkctrl;       /* offset 0x3C */
 143         unsigned int elmclkctrl;        /* offset 0x40 */
 144         unsigned int i2c2clkctrl;       /* offset 0x44 */
 145         unsigned int i2c1clkctrl;       /* offset 0x48 */
 146         unsigned int spi0clkctrl;       /* offset 0x4C */
 147         unsigned int spi1clkctrl;       /* offset 0x50 */
 148         unsigned int resv3[3];
 149         unsigned int l4lsclkctrl;       /* offset 0x60 */
 150         unsigned int l4fwclkctrl;       /* offset 0x64 */
 151         unsigned int mcasp1clkctrl;     /* offset 0x68 */
 152         unsigned int uart1clkctrl;      /* offset 0x6C */
 153         unsigned int uart2clkctrl;      /* offset 0x70 */
 154         unsigned int uart3clkctrl;      /* offset 0x74 */
 155         unsigned int uart4clkctrl;      /* offset 0x78 */
 156         unsigned int timer7clkctrl;     /* offset 0x7C */
 157         unsigned int timer2clkctrl;     /* offset 0x80 */
 158         unsigned int timer3clkctrl;     /* offset 0x84 */
 159         unsigned int timer4clkctrl;     /* offset 0x88 */
 160         unsigned int resv4[8];
 161         unsigned int gpio1clkctrl;      /* offset 0xAC */
 162         unsigned int gpio2clkctrl;      /* offset 0xB0 */
 163         unsigned int gpio3clkctrl;      /* offset 0xB4 */
 164         unsigned int resv5;
 165         unsigned int tpccclkctrl;       /* offset 0xBC */
 166         unsigned int dcan0clkctrl;      /* offset 0xC0 */
 167         unsigned int dcan1clkctrl;      /* offset 0xC4 */
 168         unsigned int resv6;
 169         unsigned int epwmss1clkctrl;    /* offset 0xCC */
 170         unsigned int emiffwclkctrl;     /* offset 0xD0 */
 171         unsigned int epwmss0clkctrl;    /* offset 0xD4 */
 172         unsigned int epwmss2clkctrl;    /* offset 0xD8 */
 173         unsigned int l3instrclkctrl;    /* offset 0xDC */
 174         unsigned int l3clkctrl;         /* Offset 0xE0 */
 175         unsigned int resv8[2];
 176         unsigned int timer5clkctrl;     /* offset 0xEC */
 177         unsigned int timer6clkctrl;     /* offset 0xF0 */
 178         unsigned int mmc1clkctrl;       /* offset 0xF4 */
 179         unsigned int mmc2clkctrl;       /* offset 0xF8 */
 180         unsigned int resv9[8];
 181         unsigned int l4hsclkstctrl;     /* offset 0x11C */
 182         unsigned int l4hsclkctrl;       /* offset 0x120 */
 183         unsigned int resv10[8];
 184         unsigned int cpswclkstctrl;     /* offset 0x144 */
 185         unsigned int lcdcclkstctrl;     /* offset 0x148 */
 186 };
 187
 188 /* Encapsulating Display pll registers */
 189 struct cm_dpll {
 190         unsigned int resv1;
 191         unsigned int clktimer7clk;      /* offset 0x04 */
 192         unsigned int clktimer2clk;      /* offset 0x08 */
 193         unsigned int clktimer3clk;      /* offset 0x0C */
 194         unsigned int clktimer4clk;      /* offset 0x10 */
 195         unsigned int resv2;
 196         unsigned int clktimer5clk;      /* offset 0x18 */
 197         unsigned int clktimer6clk;      /* offset 0x1C */
 198         unsigned int resv3[2];
 199         unsigned int clktimer1clk;      /* offset 0x28 */
 200         unsigned int resv4[2];
 201         unsigned int clklcdcpixelclk;   /* offset 0x34 */
 202 };
 203
 204 struct prm_device_inst {
 205         unsigned int prm_rstctrl;
 206         unsigned int prm_rsttime;
 207         unsigned int prm_rstst;
 208 };
 209 #else
 210 /* Encapsulating core pll registers */
 211 struct cm_wkuppll {
 212         unsigned int resv0[136];
 213         unsigned int wkl4wkclkctrl;     /* offset 0x220 */
 214         unsigned int resv1[7];
 215         unsigned int usbphy0clkctrl;    /* offset 0x240 */
 216         unsigned int resv112;
 217         unsigned int usbphy1clkctrl;    /* offset 0x248 */
 218         unsigned int resv113[45];
 219         unsigned int wkclkstctrl;       /* offset 0x300 */
 220         unsigned int resv2[15];
 221         unsigned int wkup_i2c0ctrl;     /* offset 0x340 */
 222         unsigned int resv3;
 223         unsigned int wkup_uart0ctrl;    /* offset 0x348 */
 224         unsigned int resv4[5];
 225         unsigned int wkctrlclkctrl;     /* offset 0x360 */
 226         unsigned int resv5;
 227         unsigned int wkgpio0clkctrl;    /* offset 0x368 */
 228
 229         unsigned int resv6[109];
 230         unsigned int clkmoddpllcore;    /* offset 0x520 */
 231         unsigned int idlestdpllcore;    /* offset 0x524 */
 232         unsigned int resv61;
 233         unsigned int clkseldpllcore;    /* offset 0x52C */
 234         unsigned int resv7[2];
 235         unsigned int divm4dpllcore;     /* offset 0x538 */
 236         unsigned int divm5dpllcore;     /* offset 0x53C */
 237         unsigned int divm6dpllcore;     /* offset 0x540 */
 238
 239         unsigned int resv8[7];
 240         unsigned int clkmoddpllmpu;     /* offset 0x560 */
 241         unsigned int idlestdpllmpu;     /* offset 0x564 */
 242         unsigned int resv9;
 243         unsigned int clkseldpllmpu;     /* offset 0x56c */
 244         unsigned int divm2dpllmpu;      /* offset 0x570 */
 245
 246         unsigned int resv10[11];
 247         unsigned int clkmoddpllddr;     /* offset 0x5A0 */
 248         unsigned int idlestdpllddr;     /* offset 0x5A4 */
 249         unsigned int resv11;
 250         unsigned int clkseldpllddr;     /* offset 0x5AC */
 251         unsigned int divm2dpllddr;      /* offset 0x5B0 */
 252
 253         unsigned int resv12[11];
 254         unsigned int clkmoddpllper;     /* offset 0x5E0 */
 255         unsigned int idlestdpllper;     /* offset 0x5E4 */
 256         unsigned int resv13;
 257         unsigned int clkseldpllper;     /* offset 0x5EC */
 258         unsigned int divm2dpllper;      /* offset 0x5F0 */
 259         unsigned int resv14[8];
 260         unsigned int clkdcoldodpllper;  /* offset 0x614 */
 261
 262         unsigned int resv15[2];
 263         unsigned int clkmoddplldisp;    /* offset 0x620 */
 264         unsigned int resv16[2];
 265         unsigned int clkseldplldisp;    /* offset 0x62C */
 266         unsigned int divm2dplldisp;     /* offset 0x630 */
 267 };
 268
 269 /*
 270  * Encapsulating peripheral functional clocks
 271  * pll registers
 272  */
 273 struct cm_perpll {
 274         unsigned int l3clkstctrl;       /* offset 0x00 */
 275         unsigned int resv0[7];
 276         unsigned int l3clkctrl;         /* Offset 0x20 */
 277         unsigned int resv112[7];
 278         unsigned int l3instrclkctrl;    /* offset 0x40 */
 279         unsigned int resv2[3];
 280         unsigned int ocmcramclkctrl;    /* offset 0x50 */
 281         unsigned int resv3[9];
 282         unsigned int tpccclkctrl;       /* offset 0x78 */
 283         unsigned int resv4;
 284         unsigned int tptc0clkctrl;      /* offset 0x80 */
 285
 286         unsigned int resv5[7];
 287         unsigned int l4hsclkctrl;       /* offset 0x0A0 */
 288         unsigned int resv6;
 289         unsigned int l4fwclkctrl;       /* offset 0x0A8 */
 290         unsigned int resv7[85];
 291         unsigned int l3sclkstctrl;      /* offset 0x200 */
 292         unsigned int resv8[7];
 293         unsigned int gpmcclkctrl;       /* offset 0x220 */
 294         unsigned int resv9[5];
 295         unsigned int mcasp0clkctrl;     /* offset 0x238 */
 296         unsigned int resv10;
 297         unsigned int mcasp1clkctrl;     /* offset 0x240 */
 298         unsigned int resv11;
 299         unsigned int mmc2clkctrl;       /* offset 0x248 */
 300         unsigned int resv12[3];
 301         unsigned int qspiclkctrl;       /* offset 0x258 */
 302         unsigned int resv121;
 303         unsigned int usb0clkctrl;       /* offset 0x260 */
 304         unsigned int resv122;
 305         unsigned int usb1clkctrl;       /* offset 0x268 */
 306         unsigned int resv13[101];
 307         unsigned int l4lsclkstctrl;     /* offset 0x400 */
 308         unsigned int resv14[7];
 309         unsigned int l4lsclkctrl;       /* offset 0x420 */
 310         unsigned int resv15;
 311         unsigned int dcan0clkctrl;      /* offset 0x428 */
 312         unsigned int resv16;
 313         unsigned int dcan1clkctrl;      /* offset 0x430 */
 314         unsigned int resv17[13];
 315         unsigned int elmclkctrl;        /* offset 0x468 */
 316
 317         unsigned int resv18[3];
 318         unsigned int gpio1clkctrl;      /* offset 0x478 */
 319         unsigned int resv19;
 320         unsigned int gpio2clkctrl;      /* offset 0x480 */
 321         unsigned int resv20;
 322         unsigned int gpio3clkctrl;      /* offset 0x488 */
 323         unsigned int resv41;
 324         unsigned int gpio4clkctrl;      /* offset 0x490 */
 325         unsigned int resv42;
 326         unsigned int gpio5clkctrl;      /* offset 0x498 */
 327         unsigned int resv21[3];
 328
 329         unsigned int i2c1clkctrl;       /* offset 0x4A8 */
 330         unsigned int resv22;
 331         unsigned int i2c2clkctrl;       /* offset 0x4B0 */
 332         unsigned int resv23[3];
 333         unsigned int mmc0clkctrl;       /* offset 0x4C0 */
 334         unsigned int resv24;
 335         unsigned int mmc1clkctrl;       /* offset 0x4C8 */
 336
 337         unsigned int resv25[13];
 338         unsigned int spi0clkctrl;       /* offset 0x500 */
 339         unsigned int resv26;
 340         unsigned int spi1clkctrl;       /* offset 0x508 */
 341         unsigned int resv27[9];
 342         unsigned int timer2clkctrl;     /* offset 0x530 */
 343         unsigned int resv28;
 344         unsigned int timer3clkctrl;     /* offset 0x538 */
 345         unsigned int resv29;
 346         unsigned int timer4clkctrl;     /* offset 0x540 */
 347         unsigned int resv30[5];
 348         unsigned int timer7clkctrl;     /* offset 0x558 */
 349
 350         unsigned int resv31[9];
 351         unsigned int uart1clkctrl;      /* offset 0x580 */
 352         unsigned int resv32;
 353         unsigned int uart2clkctrl;      /* offset 0x588 */
 354         unsigned int resv33;
 355         unsigned int uart3clkctrl;      /* offset 0x590 */
 356         unsigned int resv34;
 357         unsigned int uart4clkctrl;      /* offset 0x598 */
 358         unsigned int resv35;
 359         unsigned int uart5clkctrl;      /* offset 0x5A0 */
 360         unsigned int resv36[5];
 361         unsigned int usbphyocp2scp0clkctrl;     /* offset 0x5B8 */
 362         unsigned int resv361;
 363         unsigned int usbphyocp2scp1clkctrl;     /* offset 0x5C0 */
 364         unsigned int resv3611[79];
 365
 366         unsigned int emifclkstctrl;     /* offset 0x700 */
 367         unsigned int resv362[7];
 368         unsigned int emifclkctrl;       /* offset 0x720 */
 369         unsigned int resv37[3];
 370         unsigned int emiffwclkctrl;     /* offset 0x730 */
 371         unsigned int resv371;
 372         unsigned int otfaemifclkctrl;   /* offset 0x738 */
 373         unsigned int resv38[57];
 374         unsigned int lcdclkctrl;        /* offset 0x820 */
 375         unsigned int resv39[183];
 376         unsigned int cpswclkstctrl;     /* offset 0xB00 */
 377         unsigned int resv40[7];
 378         unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 379 };
 380
 381 struct cm_device_inst {
 382         unsigned int cm_clkout1_ctrl;
 383         unsigned int cm_dll_ctrl;
 384 };
 385
 386 struct prm_device_inst {
 387         unsigned int prm_rstctrl;
 388         unsigned int prm_rstst;
 389 };
 390
 391 struct cm_dpll {
 392         unsigned int resv1;
 393         unsigned int clktimer2clk;      /* offset 0x04 */
 394         unsigned int resv2[11];
 395         unsigned int clkselmacclk;      /* offset 0x34 */
 396 };
 397 #endif /* CONFIG_AM43XX */
 398
 399 /* Control Module RTC registers */
 400 struct cm_rtc {
 401         unsigned int rtcclkctrl;        /* offset 0x0 */
 402         unsigned int clkstctrl;         /* offset 0x4 */
 403 };
 404
 405 /* Timer 32 bit registers */
 406 struct gptimer {
 407         unsigned int tidr;              /* offset 0x00 */
 408         unsigned char res1[12];
 409         unsigned int tiocp_cfg;         /* offset 0x10 */
 410         unsigned char res2[12];
 411         unsigned int tier;              /* offset 0x20 */
 412         unsigned int tistatr;           /* offset 0x24 */
 413         unsigned int tistat;            /* offset 0x28 */
 414         unsigned int tisr;              /* offset 0x2c */
 415         unsigned int tcicr;             /* offset 0x30 */
 416         unsigned int twer;              /* offset 0x34 */
 417         unsigned int tclr;              /* offset 0x38 */
 418         unsigned int tcrr;              /* offset 0x3c */
 419         unsigned int tldr;              /* offset 0x40 */
 420         unsigned int ttgr;              /* offset 0x44 */
 421         unsigned int twpc;              /* offset 0x48 */
 422         unsigned int tmar;              /* offset 0x4c */
 423         unsigned int tcar1;             /* offset 0x50 */
 424         unsigned int tscir;             /* offset 0x54 */
 425         unsigned int tcar2;             /* offset 0x58 */
 426 };
 427
 428 /* UART Registers */
 429 struct uart_sys {
 430         unsigned int resv1[21];
 431         unsigned int uartsyscfg;        /* offset 0x54 */
 432         unsigned int uartsyssts;        /* offset 0x58 */
 433 };
 434
 435 /* VTP Registers */
 436 struct vtp_reg {
 437         unsigned int vtp0ctrlreg;
 438 };
 439
 440 /* Control Status Register */
 441 struct ctrl_stat {
 442         unsigned int resv1[16];
 443         unsigned int statusreg;         /* ofset 0x40 */
 444         unsigned int resv2[51];
 445         unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
 446         unsigned int resv3[319];
 447         unsigned int dev_attr;
 448 };
 449
 450 /* AM33XX GPIO registers */
 451 #define OMAP_GPIO_REVISION              0x0000
 452 #define OMAP_GPIO_SYSCONFIG             0x0010
 453 #define OMAP_GPIO_SYSSTATUS             0x0114
 454 #define OMAP_GPIO_IRQSTATUS1            0x002c
 455 #define OMAP_GPIO_IRQSTATUS2            0x0030
 456 #define OMAP_GPIO_IRQSTATUS_SET_0       0x0034
 457 #define OMAP_GPIO_IRQSTATUS_SET_1       0x0038
 458 #define OMAP_GPIO_CTRL                  0x0130
 459 #define OMAP_GPIO_OE                    0x0134
 460 #define OMAP_GPIO_DATAIN                0x0138
 461 #define OMAP_GPIO_DATAOUT               0x013c
 462 #define OMAP_GPIO_LEVELDETECT0          0x0140
 463 #define OMAP_GPIO_LEVELDETECT1          0x0144
 464 #define OMAP_GPIO_RISINGDETECT          0x0148
 465 #define OMAP_GPIO_FALLINGDETECT         0x014c
 466 #define OMAP_GPIO_DEBOUNCE_EN           0x0150
 467 #define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 468 #define OMAP_GPIO_CLEARDATAOUT          0x0190
 469 #define OMAP_GPIO_SETDATAOUT            0x0194
 470
 471 /* Control Device Register */
 472
 473  /* Control Device Register */
 474 #define MREQPRIO_0_SAB_INIT1_MASK       0xFFFFFF8F
 475 #define MREQPRIO_0_SAB_INIT0_MASK       0xFFFFFFF8
 476 #define MREQPRIO_1_DSS_MASK             0xFFFFFF8F
 477
 478 struct ctrl_dev {
 479         unsigned int deviceid;          /* offset 0x00 */
 480         unsigned int resv1[7];
 481         unsigned int usb_ctrl0;         /* offset 0x20 */
 482         unsigned int resv2;
 483         unsigned int usb_ctrl1;         /* offset 0x28 */
 484         unsigned int resv3;
 485         unsigned int macid0l;           /* offset 0x30 */
 486         unsigned int macid0h;           /* offset 0x34 */
 487         unsigned int macid1l;           /* offset 0x38 */
 488         unsigned int macid1h;           /* offset 0x3c */
 489         unsigned int resv4[4];
 490         unsigned int miisel;            /* offset 0x50 */
 491         unsigned int resv5[7];
 492         unsigned int mreqprio_0;        /* offset 0x70 */
 493         unsigned int mreqprio_1;        /* offset 0x74 */
 494         unsigned int resv6[97];
 495         unsigned int efuse_sma;         /* offset 0x1FC */
 496 };
 497
 498 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
 499 #define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
 500 #define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
 501 #define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
 502
 503 struct l3f_cfg_bwlimiter {
 504         u32 padding0[2];
 505         u32 modena_init0_bw_fractional;
 506         u32 modena_init0_bw_integer;
 507         u32 modena_init0_watermark_0;
 508 };
 509
 510 /* gmii_sel register defines */
 511 #define GMII1_SEL_MII           0x0
 512 #define GMII1_SEL_RMII          0x1
 513 #define GMII1_SEL_RGMII         0x2
 514 #define GMII2_SEL_MII           0x0
 515 #define GMII2_SEL_RMII          0x4
 516 #define GMII2_SEL_RGMII         0x8
 517 #define RGMII1_IDMODE           BIT(4)
 518 #define RGMII2_IDMODE           BIT(5)
 519 #define RMII1_IO_CLK_EN         BIT(6)
 520 #define RMII2_IO_CLK_EN         BIT(7)
 521
 522 #define MII_MODE_ENABLE         (GMII1_SEL_MII | GMII2_SEL_MII)
 523 #define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
 524 #define RGMII_MODE_ENABLE       (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 525 #define RGMII_INT_DELAY         (RGMII1_IDMODE | RGMII2_IDMODE)
 526 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 527
 528 /* PWMSS */
 529 struct pwmss_regs {
 530         unsigned int idver;
 531         unsigned int sysconfig;
 532         unsigned int clkconfig;
 533         unsigned int clkstatus;
 534 };
 535 #define ECAP_CLK_EN             BIT(0)
 536 #define ECAP_CLK_STOP_REQ       BIT(1)
 537 #define EPWM_CLK_EN             BIT(8)
 538 #define EPWM_CLK_STOP_REQ       BIT(9)
 539
 540 struct pwmss_ecap_regs {
 541         unsigned int tsctr;
 542         unsigned int ctrphs;
 543         unsigned int cap1;
 544         unsigned int cap2;
 545         unsigned int cap3;
 546         unsigned int cap4;
 547         unsigned int resv1[4];
 548         unsigned short ecctl1;
 549         unsigned short ecctl2;
 550 };
 551
 552 struct pwmss_epwm_regs {
 553         unsigned short tbctl;
 554         unsigned short tbsts;
 555         unsigned short tbphshr;
 556         unsigned short tbphs;
 557         unsigned short tbcnt;
 558         unsigned short tbprd;
 559         unsigned short res1;
 560         unsigned short cmpctl;
 561         unsigned short cmpahr;
 562         unsigned short cmpa;
 563         unsigned short cmpb;
 564         unsigned short aqctla;
 565         unsigned short aqctlb;
 566         unsigned short aqsfrc;
 567         unsigned short aqcsfrc;
 568         unsigned short dbctl;
 569         unsigned short dbred;
 570         unsigned short dbfed;
 571         unsigned short tzsel;
 572         unsigned short tzctl;
 573         unsigned short tzflg;
 574         unsigned short tzclr;
 575         unsigned short tzfrc;
 576         unsigned short etsel;
 577         unsigned short etps;
 578         unsigned short etflg;
 579         unsigned short etclr;
 580         unsigned short etfrc;
 581         unsigned short pcctl;
 582         unsigned int res2[66];
 583         unsigned short hrcnfg;
 584 };
 585
 586 /* Capture Control register 2 */
 587 #define ECTRL2_SYNCOSEL_MASK    (0x03 << 6)
 588 #define ECTRL2_MDSL_ECAP        BIT(9)
 589 #define ECTRL2_CTRSTP_FREERUN   BIT(4)
 590 #define ECTRL2_PLSL_LOW         BIT(10)
 591 #define ECTRL2_SYNC_EN          BIT(5)
 592
 593 #endif /* __ASSEMBLY__ */
 594 #endif /* __KERNEL_STRICT_NAMES */
 595
 596 #endif /* _AM33XX_CPU_H */