arch/arm/include/asm/arch-am33xx/cpu.h

   1 /*
   2  * cpu.h
   3  *
   4  * AM33xx specific header file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _AM33XX_CPU_H
  12 #define _AM33XX_CPU_H
  13
  14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  15 #include <asm/types.h>
  16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  17
  18 #include <asm/arch/hardware.h>
  19
  20 #define BIT(x)                          (1 << x)
  21 #define CL_BIT(x)                       (0 << x)
  22
  23 /* Timer register bits */
  24 #define TCLR_ST                         BIT(0)  /* Start=1 Stop=0 */
  25 #define TCLR_AR                         BIT(1)  /* Auto reload */
  26 #define TCLR_PRE                        BIT(5)  /* Pre-scaler enable */
  27 #define TCLR_PTV_SHIFT                  (2)     /* Pre-scaler shift value */
  28 #define TCLR_PRE_DISABLE                CL_BIT(5) /* Pre-scalar disable */
  29
  30 /* device type */
  31 #define DEVICE_MASK                     (BIT(8) | BIT(9) | BIT(10))
  32 #define TST_DEVICE                      0x0
  33 #define EMU_DEVICE                      0x1
  34 #define HS_DEVICE                       0x2
  35 #define GP_DEVICE                       0x3
  36
  37 /* cpu-id for AM33XX and TI81XX family */
  38 #define AM335X                          0xB944
  39 #define TI81XX                          0xB81E
  40 #define DEVICE_ID                       (CTRL_BASE + 0x0600)
  41 #define DEVICE_ID_MASK                  0x1FFF
  42
  43 /* MPU max frequencies */
  44 #define AM335X_ZCZ_300                  0x1FEF
  45 #define AM335X_ZCZ_600                  0x1FAF
  46 #define AM335X_ZCZ_720                  0x1F2F
  47 #define AM335X_ZCZ_800                  0x1E2F
  48 #define AM335X_ZCZ_1000                 0x1C2F
  49 #define AM335X_ZCE_300                  0x1FDF
  50 #define AM335X_ZCE_600                  0x1F9F
  51
  52 /* This gives the status of the boot mode pins on the evm */
  53 #define SYSBOOT_MASK                    (BIT(0) | BIT(1) | BIT(2)\
  54                                         | BIT(3) | BIT(4))
  55
  56 #define PRM_RSTCTRL_RESET               0x01
  57 #define PRM_RSTST_WARM_RESET_MASK       0x232
  58
  59 /*
  60  * Watchdog:
  61  * Using the prescaler, the OMAP watchdog could go for many
  62  * months before firing.  These limits work without scaling,
  63  * with the 60 second default assumed by most tools and docs.
  64  */
  65 #define TIMER_MARGIN_MAX        (24 * 60 * 60)  /* 1 day */
  66 #define TIMER_MARGIN_DEFAULT    60      /* 60 secs */
  67 #define TIMER_MARGIN_MIN        1
  68
  69 #define PTV                     0       /* prescale */
  70 #define GET_WLDR_VAL(secs)      (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
  71 #define WDT_WWPS_PEND_WCLR      BIT(0)
  72 #define WDT_WWPS_PEND_WLDR      BIT(2)
  73 #define WDT_WWPS_PEND_WTGR      BIT(3)
  74 #define WDT_WWPS_PEND_WSPR      BIT(4)
  75
  76 #define WDT_WCLR_PRE            BIT(5)
  77 #define WDT_WCLR_PTV_OFF        2
  78
  79 #ifndef __KERNEL_STRICT_NAMES
  80 #ifndef __ASSEMBLY__
  81 struct gpmc_cs {
  82         u32 config1;            /* 0x00 */
  83         u32 config2;            /* 0x04 */
  84         u32 config3;            /* 0x08 */
  85         u32 config4;            /* 0x0C */
  86         u32 config5;            /* 0x10 */
  87         u32 config6;            /* 0x14 */
  88         u32 config7;            /* 0x18 */
  89         u32 nand_cmd;           /* 0x1C */
  90         u32 nand_adr;           /* 0x20 */
  91         u32 nand_dat;           /* 0x24 */
  92         u8 res[8];              /* blow up to 0x30 byte */
  93 };
  94
  95 struct bch_res_0_3 {
  96         u32 bch_result_x[4];
  97 };
  98
  99 struct gpmc {
 100         u8 res1[0x10];
 101         u32 sysconfig;          /* 0x10 */
 102         u8 res2[0x4];
 103         u32 irqstatus;          /* 0x18 */
 104         u32 irqenable;          /* 0x1C */
 105         u8 res3[0x20];
 106         u32 timeout_control;    /* 0x40 */
 107         u8 res4[0xC];
 108         u32 config;             /* 0x50 */
 109         u32 status;             /* 0x54 */
 110         u8 res5[0x8];           /* 0x58 */
 111         struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
 112         u8 res6[0x14];          /* 0x1E0 */
 113         u32 ecc_config;         /* 0x1F4 */
 114         u32 ecc_control;        /* 0x1F8 */
 115         u32 ecc_size_config;    /* 0x1FC */
 116         u32 ecc1_result;        /* 0x200 */
 117         u32 ecc2_result;        /* 0x204 */
 118         u32 ecc3_result;        /* 0x208 */
 119         u32 ecc4_result;        /* 0x20C */
 120         u32 ecc5_result;        /* 0x210 */
 121         u32 ecc6_result;        /* 0x214 */
 122         u32 ecc7_result;        /* 0x218 */
 123         u32 ecc8_result;        /* 0x21C */
 124         u32 ecc9_result;        /* 0x220 */
 125         u8 res7[12];            /* 0x224 */
 126         u32 testmomde_ctrl;     /* 0x230 */
 127         u8 res8[12];            /* 0x234 */
 128         struct bch_res_0_3 bch_result_0_3[2];   /* 0x240 */
 129 };
 130
 131 /* Used for board specific gpmc initialization */
 132 extern struct gpmc *gpmc_cfg;
 133
 134 #ifndef CONFIG_AM43XX
 135 /* Encapsulating core pll registers */
 136 struct cm_wkuppll {
 137         unsigned int wkclkstctrl;       /* offset 0x00 */
 138         unsigned int wkctrlclkctrl;     /* offset 0x04 */
 139         unsigned int wkgpio0clkctrl;    /* offset 0x08 */
 140         unsigned int wkl4wkclkctrl;     /* offset 0x0c */
 141         unsigned int resv2[4];
 142         unsigned int idlestdpllmpu;     /* offset 0x20 */
 143         unsigned int resv3[2];
 144         unsigned int clkseldpllmpu;     /* offset 0x2c */
 145         unsigned int resv4[1];
 146         unsigned int idlestdpllddr;     /* offset 0x34 */
 147         unsigned int resv5[2];
 148         unsigned int clkseldpllddr;     /* offset 0x40 */
 149         unsigned int resv6[4];
 150         unsigned int clkseldplldisp;    /* offset 0x54 */
 151         unsigned int resv7[1];
 152         unsigned int idlestdpllcore;    /* offset 0x5c */
 153         unsigned int resv8[2];
 154         unsigned int clkseldpllcore;    /* offset 0x68 */
 155         unsigned int resv9[1];
 156         unsigned int idlestdpllper;     /* offset 0x70 */
 157         unsigned int resv10[2];
 158         unsigned int clkdcoldodpllper;  /* offset 0x7c */
 159         unsigned int divm4dpllcore;     /* offset 0x80 */
 160         unsigned int divm5dpllcore;     /* offset 0x84 */
 161         unsigned int clkmoddpllmpu;     /* offset 0x88 */
 162         unsigned int clkmoddpllper;     /* offset 0x8c */
 163         unsigned int clkmoddpllcore;    /* offset 0x90 */
 164         unsigned int clkmoddpllddr;     /* offset 0x94 */
 165         unsigned int clkmoddplldisp;    /* offset 0x98 */
 166         unsigned int clkseldpllper;     /* offset 0x9c */
 167         unsigned int divm2dpllddr;      /* offset 0xA0 */
 168         unsigned int divm2dplldisp;     /* offset 0xA4 */
 169         unsigned int divm2dpllmpu;      /* offset 0xA8 */
 170         unsigned int divm2dpllper;      /* offset 0xAC */
 171         unsigned int resv11[1];
 172         unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
 173         unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
 174         unsigned int wkup_adctscctrl;   /* offset 0xBC */
 175         unsigned int resv12[6];
 176         unsigned int divm6dpllcore;     /* offset 0xD8 */
 177 };
 178
 179 /**
 180  * Encapsulating peripheral functional clocks
 181  * pll registers
 182  */
 183 struct cm_perpll {
 184         unsigned int l4lsclkstctrl;     /* offset 0x00 */
 185         unsigned int l3sclkstctrl;      /* offset 0x04 */
 186         unsigned int l4fwclkstctrl;     /* offset 0x08 */
 187         unsigned int l3clkstctrl;       /* offset 0x0c */
 188         unsigned int resv1;
 189         unsigned int cpgmac0clkctrl;    /* offset 0x14 */
 190         unsigned int lcdclkctrl;        /* offset 0x18 */
 191         unsigned int usb0clkctrl;       /* offset 0x1C */
 192         unsigned int resv2;
 193         unsigned int tptc0clkctrl;      /* offset 0x24 */
 194         unsigned int emifclkctrl;       /* offset 0x28 */
 195         unsigned int ocmcramclkctrl;    /* offset 0x2c */
 196         unsigned int gpmcclkctrl;       /* offset 0x30 */
 197         unsigned int mcasp0clkctrl;     /* offset 0x34 */
 198         unsigned int uart5clkctrl;      /* offset 0x38 */
 199         unsigned int mmc0clkctrl;       /* offset 0x3C */
 200         unsigned int elmclkctrl;        /* offset 0x40 */
 201         unsigned int i2c2clkctrl;       /* offset 0x44 */
 202         unsigned int i2c1clkctrl;       /* offset 0x48 */
 203         unsigned int spi0clkctrl;       /* offset 0x4C */
 204         unsigned int spi1clkctrl;       /* offset 0x50 */
 205         unsigned int resv3[3];
 206         unsigned int l4lsclkctrl;       /* offset 0x60 */
 207         unsigned int l4fwclkctrl;       /* offset 0x64 */
 208         unsigned int mcasp1clkctrl;     /* offset 0x68 */
 209         unsigned int uart1clkctrl;      /* offset 0x6C */
 210         unsigned int uart2clkctrl;      /* offset 0x70 */
 211         unsigned int uart3clkctrl;      /* offset 0x74 */
 212         unsigned int uart4clkctrl;      /* offset 0x78 */
 213         unsigned int timer7clkctrl;     /* offset 0x7C */
 214         unsigned int timer2clkctrl;     /* offset 0x80 */
 215         unsigned int timer3clkctrl;     /* offset 0x84 */
 216         unsigned int timer4clkctrl;     /* offset 0x88 */
 217         unsigned int resv4[8];
 218         unsigned int gpio1clkctrl;      /* offset 0xAC */
 219         unsigned int gpio2clkctrl;      /* offset 0xB0 */
 220         unsigned int gpio3clkctrl;      /* offset 0xB4 */
 221         unsigned int resv5;
 222         unsigned int tpccclkctrl;       /* offset 0xBC */
 223         unsigned int dcan0clkctrl;      /* offset 0xC0 */
 224         unsigned int dcan1clkctrl;      /* offset 0xC4 */
 225         unsigned int resv6;
 226         unsigned int epwmss1clkctrl;    /* offset 0xCC */
 227         unsigned int emiffwclkctrl;     /* offset 0xD0 */
 228         unsigned int epwmss0clkctrl;    /* offset 0xD4 */
 229         unsigned int epwmss2clkctrl;    /* offset 0xD8 */
 230         unsigned int l3instrclkctrl;    /* offset 0xDC */
 231         unsigned int l3clkctrl;         /* Offset 0xE0 */
 232         unsigned int resv8[4];
 233         unsigned int mmc1clkctrl;       /* offset 0xF4 */
 234         unsigned int mmc2clkctrl;       /* offset 0xF8 */
 235         unsigned int resv9[8];
 236         unsigned int l4hsclkstctrl;     /* offset 0x11C */
 237         unsigned int l4hsclkctrl;       /* offset 0x120 */
 238         unsigned int resv10[8];
 239         unsigned int cpswclkstctrl;     /* offset 0x144 */
 240         unsigned int lcdcclkstctrl;     /* offset 0x148 */
 241 };
 242
 243 /* Encapsulating Display pll registers */
 244 struct cm_dpll {
 245         unsigned int resv1[2];
 246         unsigned int clktimer2clk;      /* offset 0x08 */
 247         unsigned int resv2[10];
 248         unsigned int clklcdcpixelclk;   /* offset 0x34 */
 249 };
 250 #else
 251 /* Encapsulating core pll registers */
 252 struct cm_wkuppll {
 253         unsigned int resv0[136];
 254         unsigned int wkl4wkclkctrl;     /* offset 0x220 */
 255         unsigned int resv1[55];
 256         unsigned int wkclkstctrl;       /* offset 0x300 */
 257         unsigned int resv2[15];
 258         unsigned int wkup_i2c0ctrl;     /* offset 0x340 */
 259         unsigned int resv3;
 260         unsigned int wkup_uart0ctrl;    /* offset 0x348 */
 261         unsigned int resv4[5];
 262         unsigned int wkctrlclkctrl;     /* offset 0x360 */
 263         unsigned int resv5;
 264         unsigned int wkgpio0clkctrl;    /* offset 0x368 */
 265
 266         unsigned int resv6[109];
 267         unsigned int clkmoddpllcore;    /* offset 0x520 */
 268         unsigned int idlestdpllcore;    /* offset 0x524 */
 269         unsigned int resv61;
 270         unsigned int clkseldpllcore;    /* offset 0x52C */
 271         unsigned int resv7[2];
 272         unsigned int divm4dpllcore;     /* offset 0x538 */
 273         unsigned int divm5dpllcore;     /* offset 0x53C */
 274         unsigned int divm6dpllcore;     /* offset 0x540 */
 275
 276         unsigned int resv8[7];
 277         unsigned int clkmoddpllmpu;     /* offset 0x560 */
 278         unsigned int idlestdpllmpu;     /* offset 0x564 */
 279         unsigned int resv9;
 280         unsigned int clkseldpllmpu;     /* offset 0x56c */
 281         unsigned int divm2dpllmpu;      /* offset 0x570 */
 282
 283         unsigned int resv10[11];
 284         unsigned int clkmoddpllddr;     /* offset 0x5A0 */
 285         unsigned int idlestdpllddr;     /* offset 0x5A4 */
 286         unsigned int resv11;
 287         unsigned int clkseldpllddr;     /* offset 0x5AC */
 288         unsigned int divm2dpllddr;      /* offset 0x5B0 */
 289
 290         unsigned int resv12[11];
 291         unsigned int clkmoddpllper;     /* offset 0x5E0 */
 292         unsigned int idlestdpllper;     /* offset 0x5E4 */
 293         unsigned int resv13;
 294         unsigned int clkseldpllper;     /* offset 0x5EC */
 295         unsigned int divm2dpllper;      /* offset 0x5F0 */
 296         unsigned int resv14[8];
 297         unsigned int clkdcoldodpllper;  /* offset 0x614 */
 298
 299         unsigned int resv15[2];
 300         unsigned int clkmoddplldisp;    /* offset 0x620 */
 301         unsigned int resv16[2];
 302         unsigned int clkseldplldisp;    /* offset 0x62C */
 303         unsigned int divm2dplldisp;     /* offset 0x630 */
 304 };
 305
 306 /*
 307  * Encapsulating peripheral functional clocks
 308  * pll registers
 309  */
 310 struct cm_perpll {
 311         unsigned int l3clkstctrl;       /* offset 0x00 */
 312         unsigned int resv0[7];
 313         unsigned int l3clkctrl;         /* Offset 0x20 */
 314         unsigned int resv1[7];
 315         unsigned int l3instrclkctrl;    /* offset 0x40 */
 316         unsigned int resv2[3];
 317         unsigned int ocmcramclkctrl;    /* offset 0x50 */
 318         unsigned int resv3[9];
 319         unsigned int tpccclkctrl;       /* offset 0x78 */
 320         unsigned int resv4;
 321         unsigned int tptc0clkctrl;      /* offset 0x80 */
 322
 323         unsigned int resv5[7];
 324         unsigned int l4hsclkctrl;       /* offset 0x0A0 */
 325         unsigned int resv6;
 326         unsigned int l4fwclkctrl;       /* offset 0x0A8 */
 327         unsigned int resv7[85];
 328         unsigned int l3sclkstctrl;      /* offset 0x200 */
 329         unsigned int resv8[7];
 330         unsigned int gpmcclkctrl;       /* offset 0x220 */
 331         unsigned int resv9[5];
 332         unsigned int mcasp0clkctrl;     /* offset 0x238 */
 333         unsigned int resv10;
 334         unsigned int mcasp1clkctrl;     /* offset 0x240 */
 335         unsigned int resv11;
 336         unsigned int mmc2clkctrl;       /* offset 0x248 */
 337         unsigned int resv12[3];
 338         unsigned int qspiclkctrl;       /* offset 0x258 */
 339         unsigned int resv121;
 340         unsigned int usb0clkctrl;       /* offset 0x260 */
 341         unsigned int resv13[103];
 342         unsigned int l4lsclkstctrl;     /* offset 0x400 */
 343         unsigned int resv14[7];
 344         unsigned int l4lsclkctrl;       /* offset 0x420 */
 345         unsigned int resv15;
 346         unsigned int dcan0clkctrl;      /* offset 0x428 */
 347         unsigned int resv16;
 348         unsigned int dcan1clkctrl;      /* offset 0x430 */
 349         unsigned int resv17[13];
 350         unsigned int elmclkctrl;        /* offset 0x468 */
 351
 352         unsigned int resv18[3];
 353         unsigned int gpio1clkctrl;      /* offset 0x478 */
 354         unsigned int resv19;
 355         unsigned int gpio2clkctrl;      /* offset 0x480 */
 356         unsigned int resv20;
 357         unsigned int gpio3clkctrl;      /* offset 0x488 */
 358         unsigned int resv41;
 359         unsigned int gpio4clkctrl;      /* offset 0x490 */
 360         unsigned int resv42;
 361         unsigned int gpio5clkctrl;      /* offset 0x498 */
 362         unsigned int resv21[3];
 363
 364         unsigned int i2c1clkctrl;       /* offset 0x4A8 */
 365         unsigned int resv22;
 366         unsigned int i2c2clkctrl;       /* offset 0x4B0 */
 367         unsigned int resv23[3];
 368         unsigned int mmc0clkctrl;       /* offset 0x4C0 */
 369         unsigned int resv24;
 370         unsigned int mmc1clkctrl;       /* offset 0x4C8 */
 371
 372         unsigned int resv25[13];
 373         unsigned int spi0clkctrl;       /* offset 0x500 */
 374         unsigned int resv26;
 375         unsigned int spi1clkctrl;       /* offset 0x508 */
 376         unsigned int resv27[9];
 377         unsigned int timer2clkctrl;     /* offset 0x530 */
 378         unsigned int resv28;
 379         unsigned int timer3clkctrl;     /* offset 0x538 */
 380         unsigned int resv29;
 381         unsigned int timer4clkctrl;     /* offset 0x540 */
 382         unsigned int resv30[5];
 383         unsigned int timer7clkctrl;     /* offset 0x558 */
 384
 385         unsigned int resv31[9];
 386         unsigned int uart1clkctrl;      /* offset 0x580 */
 387         unsigned int resv32;
 388         unsigned int uart2clkctrl;      /* offset 0x588 */
 389         unsigned int resv33;
 390         unsigned int uart3clkctrl;      /* offset 0x590 */
 391         unsigned int resv34;
 392         unsigned int uart4clkctrl;      /* offset 0x598 */
 393         unsigned int resv35;
 394         unsigned int uart5clkctrl;      /* offset 0x5A0 */
 395         unsigned int resv36[87];
 396
 397         unsigned int emifclkstctrl;     /* offset 0x700 */
 398         unsigned int resv361[7];
 399         unsigned int emifclkctrl;       /* offset 0x720 */
 400         unsigned int resv37[3];
 401         unsigned int emiffwclkctrl;     /* offset 0x730 */
 402         unsigned int resv371;
 403         unsigned int otfaemifclkctrl;   /* offset 0x738 */
 404         unsigned int resv38[57];
 405         unsigned int lcdclkctrl;        /* offset 0x820 */
 406         unsigned int resv39[183];
 407         unsigned int cpswclkstctrl;     /* offset 0xB00 */
 408         unsigned int resv40[7];
 409         unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 410 };
 411
 412 struct cm_device_inst {
 413         unsigned int cm_clkout1_ctrl;
 414         unsigned int cm_dll_ctrl;
 415 };
 416
 417 struct cm_dpll {
 418         unsigned int resv1;
 419         unsigned int clktimer2clk;      /* offset 0x04 */
 420 };
 421 #endif /* CONFIG_AM43XX */
 422
 423 /* Control Module RTC registers */
 424 struct cm_rtc {
 425         unsigned int rtcclkctrl;        /* offset 0x0 */
 426         unsigned int clkstctrl;         /* offset 0x4 */
 427 };
 428
 429 /* Watchdog timer registers */
 430 struct wd_timer {
 431         unsigned int resv1[4];
 432         unsigned int wdtwdsc;   /* offset 0x010 */
 433         unsigned int wdtwdst;   /* offset 0x014 */
 434         unsigned int wdtwisr;   /* offset 0x018 */
 435         unsigned int wdtwier;   /* offset 0x01C */
 436         unsigned int wdtwwer;   /* offset 0x020 */
 437         unsigned int wdtwclr;   /* offset 0x024 */
 438         unsigned int wdtwcrr;   /* offset 0x028 */
 439         unsigned int wdtwldr;   /* offset 0x02C */
 440         unsigned int wdtwtgr;   /* offset 0x030 */
 441         unsigned int wdtwwps;   /* offset 0x034 */
 442         unsigned int resv2[3];
 443         unsigned int wdtwdly;   /* offset 0x044 */
 444         unsigned int wdtwspr;   /* offset 0x048 */
 445         unsigned int resv3[1];
 446         unsigned int wdtwqeoi;  /* offset 0x050 */
 447         unsigned int wdtwqstar; /* offset 0x054 */
 448         unsigned int wdtwqsta;  /* offset 0x058 */
 449         unsigned int wdtwqens;  /* offset 0x05C */
 450         unsigned int wdtwqenc;  /* offset 0x060 */
 451         unsigned int resv4[39];
 452         unsigned int wdt_unfr;  /* offset 0x100 */
 453 };
 454
 455 /* Timer 32 bit registers */
 456 struct gptimer {
 457         unsigned int tidr;              /* offset 0x00 */
 458         unsigned char res1[12];
 459         unsigned int tiocp_cfg;         /* offset 0x10 */
 460         unsigned char res2[12];
 461         unsigned int tier;              /* offset 0x20 */
 462         unsigned int tistatr;           /* offset 0x24 */
 463         unsigned int tistat;            /* offset 0x28 */
 464         unsigned int tisr;              /* offset 0x2c */
 465         unsigned int tcicr;             /* offset 0x30 */
 466         unsigned int twer;              /* offset 0x34 */
 467         unsigned int tclr;              /* offset 0x38 */
 468         unsigned int tcrr;              /* offset 0x3c */
 469         unsigned int tldr;              /* offset 0x40 */
 470         unsigned int ttgr;              /* offset 0x44 */
 471         unsigned int twpc;              /* offset 0x48 */
 472         unsigned int tmar;              /* offset 0x4c */
 473         unsigned int tcar1;             /* offset 0x50 */
 474         unsigned int tscir;             /* offset 0x54 */
 475         unsigned int tcar2;             /* offset 0x58 */
 476 };
 477
 478 /* UART Registers */
 479 struct uart_sys {
 480         unsigned int resv1[21];
 481         unsigned int uartsyscfg;        /* offset 0x54 */
 482         unsigned int uartsyssts;        /* offset 0x58 */
 483 };
 484
 485 /* VTP Registers */
 486 struct vtp_reg {
 487         unsigned int vtp0ctrlreg;
 488 };
 489
 490 /* Control Status Register */
 491 struct ctrl_stat {
 492         unsigned int resv1[16];
 493         unsigned int statusreg;         /* ofset 0x40 */
 494         unsigned int resv2[51];
 495         unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
 496         unsigned int resv3[319];
 497         unsigned int dev_attr;
 498 };
 499
 500 /* AM33XX GPIO registers */
 501 #define OMAP_GPIO_REVISION              0x0000
 502 #define OMAP_GPIO_SYSCONFIG             0x0010
 503 #define OMAP_GPIO_SYSSTATUS             0x0114
 504 #define OMAP_GPIO_IRQSTATUS1            0x002c
 505 #define OMAP_GPIO_IRQSTATUS2            0x0030
 506 #define OMAP_GPIO_CTRL                  0x0130
 507 #define OMAP_GPIO_OE                    0x0134
 508 #define OMAP_GPIO_DATAIN                0x0138
 509 #define OMAP_GPIO_DATAOUT               0x013c
 510 #define OMAP_GPIO_LEVELDETECT0          0x0140
 511 #define OMAP_GPIO_LEVELDETECT1          0x0144
 512 #define OMAP_GPIO_RISINGDETECT          0x0148
 513 #define OMAP_GPIO_FALLINGDETECT         0x014c
 514 #define OMAP_GPIO_DEBOUNCE_EN           0x0150
 515 #define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 516 #define OMAP_GPIO_CLEARDATAOUT          0x0190
 517 #define OMAP_GPIO_SETDATAOUT            0x0194
 518
 519 /* Control Device Register */
 520 struct ctrl_dev {
 521         unsigned int deviceid;          /* offset 0x00 */
 522         unsigned int resv1[7];
 523         unsigned int usb_ctrl0;         /* offset 0x20 */
 524         unsigned int resv2;
 525         unsigned int usb_ctrl1;         /* offset 0x28 */
 526         unsigned int resv3;
 527         unsigned int macid0l;           /* offset 0x30 */
 528         unsigned int macid0h;           /* offset 0x34 */
 529         unsigned int macid1l;           /* offset 0x38 */
 530         unsigned int macid1h;           /* offset 0x3c */
 531         unsigned int resv4[4];
 532         unsigned int miisel;            /* offset 0x50 */
 533         unsigned int resv5[106];
 534         unsigned int efuse_sma;         /* offset 0x1FC */
 535 };
 536
 537 /* gmii_sel register defines */
 538 #define GMII1_SEL_MII           0x0
 539 #define GMII1_SEL_RMII          0x1
 540 #define GMII1_SEL_RGMII         0x2
 541 #define GMII2_SEL_MII           0x0
 542 #define GMII2_SEL_RMII          0x4
 543 #define GMII2_SEL_RGMII         0x8
 544 #define RGMII1_IDMODE           BIT(4)
 545 #define RGMII2_IDMODE           BIT(5)
 546 #define RMII1_IO_CLK_EN         BIT(6)
 547 #define RMII2_IO_CLK_EN         BIT(7)
 548
 549 #define MII_MODE_ENABLE         (GMII1_SEL_MII | GMII2_SEL_MII)
 550 #define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
 551 #define RGMII_MODE_ENABLE       (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 552 #define RGMII_INT_DELAY         (RGMII1_IDMODE | RGMII2_IDMODE)
 553 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 554
 555 /* PWMSS */
 556 struct pwmss_regs {
 557         unsigned int idver;
 558         unsigned int sysconfig;
 559         unsigned int clkconfig;
 560         unsigned int clkstatus;
 561 };
 562 #define ECAP_CLK_EN             BIT(0)
 563 #define ECAP_CLK_STOP_REQ       BIT(1)
 564
 565 struct pwmss_ecap_regs {
 566         unsigned int tsctr;
 567         unsigned int ctrphs;
 568         unsigned int cap1;
 569         unsigned int cap2;
 570         unsigned int cap3;
 571         unsigned int cap4;
 572         unsigned int resv1[4];
 573         unsigned short ecctl1;
 574         unsigned short ecctl2;
 575 };
 576
 577 /* Capture Control register 2 */
 578 #define ECTRL2_SYNCOSEL_MASK    (0x03 << 6)
 579 #define ECTRL2_MDSL_ECAP        BIT(9)
 580 #define ECTRL2_CTRSTP_FREERUN   BIT(4)
 581 #define ECTRL2_PLSL_LOW         BIT(10)
 582 #define ECTRL2_SYNC_EN          BIT(5)
 583
 584 #endif /* __ASSEMBLY__ */
 585 #endif /* __KERNEL_STRICT_NAMES */
 586
 587 #endif /* _AM33XX_CPU_H */