4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 #include <asm/arch/hardware.h>
20 #define CL_BIT(x) (0 << x)
22 /* Timer register bits */
23 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
24 #define TCLR_AR BIT(1) /* Auto reload */
25 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
26 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
27 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
28 #define TCLR_CE BIT(6) /* compare mode enable */
29 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
30 #define TCLR_TCM BIT(8) /* edge detection of input pin*/
31 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
32 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
33 #define TCLR_CAPTMODE BIT(13) /* capture mode */
34 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
36 #define TCFG_RESET BIT(0) /* software reset */
37 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
38 #define TCFG_IDLEMOD_SHIFT (2) /* power management */
40 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
41 #define TST_DEVICE 0x0
42 #define EMU_DEVICE 0x1
46 /* cpu-id for AM43XX AM33XX and TI81XX family */
50 #define DEVICE_ID (CTRL_BASE + 0x0600)
51 #define DEVICE_ID_MASK 0x1FFF
53 /* MPU max frequencies */
54 #define AM335X_ZCZ_300 0x1FEF
55 #define AM335X_ZCZ_600 0x1FAF
56 #define AM335X_ZCZ_720 0x1F2F
57 #define AM335X_ZCZ_800 0x1E2F
58 #define AM335X_ZCZ_1000 0x1C2F
59 #define AM335X_ZCE_300 0x1FDF
60 #define AM335X_ZCE_600 0x1F9F
62 /* This gives the status of the boot mode pins on the evm */
63 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
66 #define PRM_RSTCTRL_RESET 0x01
67 #define PRM_RSTST_WARM_RESET_MASK 0x232
71 * Using the prescaler, the OMAP watchdog could go for many
72 * months before firing. These limits work without scaling,
73 * with the 60 second default assumed by most tools and docs.
75 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
76 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
77 #define TIMER_MARGIN_MIN 1
79 #define PTV 0 /* prescale */
80 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
81 #define WDT_WWPS_PEND_WCLR BIT(0)
82 #define WDT_WWPS_PEND_WLDR BIT(2)
83 #define WDT_WWPS_PEND_WTGR BIT(3)
84 #define WDT_WWPS_PEND_WSPR BIT(4)
86 #define WDT_WCLR_PRE BIT(5)
87 #define WDT_WCLR_PTV_OFF 2
89 #ifndef __KERNEL_STRICT_NAMES
94 /* Encapsulating core pll registers */
96 unsigned int wkclkstctrl
; /* offset 0x00 */
97 unsigned int wkctrlclkctrl
; /* offset 0x04 */
98 unsigned int wkgpio0clkctrl
; /* offset 0x08 */
99 unsigned int wkl4wkclkctrl
; /* offset 0x0c */
100 unsigned int timer0clkctrl
; /* offset 0x10 */
101 unsigned int resv2
[3];
102 unsigned int idlestdpllmpu
; /* offset 0x20 */
103 unsigned int sscdeltamstepdllmpu
; /* off 0x24 */
104 unsigned int sscmodfreqdivdpllmpu
; /* off 0x28 */
105 unsigned int clkseldpllmpu
; /* offset 0x2c */
106 unsigned int resv4
[1];
107 unsigned int idlestdpllddr
; /* offset 0x34 */
108 unsigned int resv5
[2];
109 unsigned int clkseldpllddr
; /* offset 0x40 */
110 unsigned int resv6
[4];
111 unsigned int clkseldplldisp
; /* offset 0x54 */
112 unsigned int resv7
[1];
113 unsigned int idlestdpllcore
; /* offset 0x5c */
114 unsigned int resv8
[2];
115 unsigned int clkseldpllcore
; /* offset 0x68 */
116 unsigned int resv9
[1];
117 unsigned int idlestdpllper
; /* offset 0x70 */
118 unsigned int resv10
[2];
119 unsigned int clkdcoldodpllper
; /* offset 0x7c */
120 unsigned int divm4dpllcore
; /* offset 0x80 */
121 unsigned int divm5dpllcore
; /* offset 0x84 */
122 unsigned int clkmoddpllmpu
; /* offset 0x88 */
123 unsigned int clkmoddpllper
; /* offset 0x8c */
124 unsigned int clkmoddpllcore
; /* offset 0x90 */
125 unsigned int clkmoddpllddr
; /* offset 0x94 */
126 unsigned int clkmoddplldisp
; /* offset 0x98 */
127 unsigned int clkseldpllper
; /* offset 0x9c */
128 unsigned int divm2dpllddr
; /* offset 0xA0 */
129 unsigned int divm2dplldisp
; /* offset 0xA4 */
130 unsigned int divm2dpllmpu
; /* offset 0xA8 */
131 unsigned int divm2dpllper
; /* offset 0xAC */
132 unsigned int resv11
[1];
133 unsigned int wkup_uart0ctrl
; /* offset 0xB4 */
134 unsigned int wkup_i2c0ctrl
; /* offset 0xB8 */
135 unsigned int wkup_adctscctrl
; /* offset 0xBC */
137 unsigned int timer1clkctrl
; /* offset 0xC4 */
138 unsigned int resv13
[4];
139 unsigned int divm6dpllcore
; /* offset 0xD8 */
143 * Encapsulating peripheral functional clocks
147 unsigned int l4lsclkstctrl
; /* offset 0x00 */
148 unsigned int l3sclkstctrl
; /* offset 0x04 */
149 unsigned int l4fwclkstctrl
; /* offset 0x08 */
150 unsigned int l3clkstctrl
; /* offset 0x0c */
152 unsigned int cpgmac0clkctrl
; /* offset 0x14 */
153 unsigned int lcdclkctrl
; /* offset 0x18 */
154 unsigned int usb0clkctrl
; /* offset 0x1C */
156 unsigned int tptc0clkctrl
; /* offset 0x24 */
157 unsigned int emifclkctrl
; /* offset 0x28 */
158 unsigned int ocmcramclkctrl
; /* offset 0x2c */
159 unsigned int gpmcclkctrl
; /* offset 0x30 */
160 unsigned int mcasp0clkctrl
; /* offset 0x34 */
161 unsigned int uart5clkctrl
; /* offset 0x38 */
162 unsigned int mmc0clkctrl
; /* offset 0x3C */
163 unsigned int elmclkctrl
; /* offset 0x40 */
164 unsigned int i2c2clkctrl
; /* offset 0x44 */
165 unsigned int i2c1clkctrl
; /* offset 0x48 */
166 unsigned int spi0clkctrl
; /* offset 0x4C */
167 unsigned int spi1clkctrl
; /* offset 0x50 */
168 unsigned int resv3
[3];
169 unsigned int l4lsclkctrl
; /* offset 0x60 */
170 unsigned int l4fwclkctrl
; /* offset 0x64 */
171 unsigned int mcasp1clkctrl
; /* offset 0x68 */
172 unsigned int uart1clkctrl
; /* offset 0x6C */
173 unsigned int uart2clkctrl
; /* offset 0x70 */
174 unsigned int uart3clkctrl
; /* offset 0x74 */
175 unsigned int uart4clkctrl
; /* offset 0x78 */
176 unsigned int timer7clkctrl
; /* offset 0x7C */
177 unsigned int timer2clkctrl
; /* offset 0x80 */
178 unsigned int timer3clkctrl
; /* offset 0x84 */
179 unsigned int timer4clkctrl
; /* offset 0x88 */
180 unsigned int resv4
[8];
181 unsigned int gpio1clkctrl
; /* offset 0xAC */
182 unsigned int gpio2clkctrl
; /* offset 0xB0 */
183 unsigned int gpio3clkctrl
; /* offset 0xB4 */
185 unsigned int tpccclkctrl
; /* offset 0xBC */
186 unsigned int dcan0clkctrl
; /* offset 0xC0 */
187 unsigned int dcan1clkctrl
; /* offset 0xC4 */
189 unsigned int epwmss1clkctrl
; /* offset 0xCC */
190 unsigned int emiffwclkctrl
; /* offset 0xD0 */
191 unsigned int epwmss0clkctrl
; /* offset 0xD4 */
192 unsigned int epwmss2clkctrl
; /* offset 0xD8 */
193 unsigned int l3instrclkctrl
; /* offset 0xDC */
194 unsigned int l3clkctrl
; /* Offset 0xE0 */
195 unsigned int resv8
[2];
196 unsigned int timer5clkctrl
; /* offset 0xEC */
197 unsigned int timer6clkctrl
; /* offset 0xF0 */
198 unsigned int mmc1clkctrl
; /* offset 0xF4 */
199 unsigned int mmc2clkctrl
; /* offset 0xF8 */
200 unsigned int resv9
[8];
201 unsigned int l4hsclkstctrl
; /* offset 0x11C */
202 unsigned int l4hsclkctrl
; /* offset 0x120 */
203 unsigned int resv10
[8];
204 unsigned int cpswclkstctrl
; /* offset 0x144 */
205 unsigned int lcdcclkstctrl
; /* offset 0x148 */
208 /* Encapsulating Display pll registers */
211 unsigned int clktimer7clk
; /* offset 0x04 */
212 unsigned int clktimer2clk
; /* offset 0x08 */
213 unsigned int clktimer3clk
; /* offset 0x0C */
214 unsigned int clktimer4clk
; /* offset 0x10 */
216 unsigned int clktimer5clk
; /* offset 0x18 */
217 unsigned int clktimer6clk
; /* offset 0x1C */
218 unsigned int resv3
[2];
219 unsigned int clktimer1clk
; /* offset 0x28 */
220 unsigned int resv4
[2];
221 unsigned int clklcdcpixelclk
; /* offset 0x34 */
224 struct prm_device_inst
{
225 unsigned int prm_rstctrl
;
226 unsigned int prm_rsttime
;
227 unsigned int prm_rstst
;
230 /* Encapsulating core pll registers */
232 unsigned int resv0
[136];
233 unsigned int wkl4wkclkctrl
; /* offset 0x220 */
234 unsigned int resv1
[7];
235 unsigned int usbphy0clkctrl
; /* offset 0x240 */
236 unsigned int resv112
;
237 unsigned int usbphy1clkctrl
; /* offset 0x248 */
238 unsigned int resv113
[45];
239 unsigned int wkclkstctrl
; /* offset 0x300 */
240 unsigned int resv2
[15];
241 unsigned int wkup_i2c0ctrl
; /* offset 0x340 */
243 unsigned int wkup_uart0ctrl
; /* offset 0x348 */
244 unsigned int resv4
[5];
245 unsigned int wkctrlclkctrl
; /* offset 0x360 */
247 unsigned int wkgpio0clkctrl
; /* offset 0x368 */
249 unsigned int resv6
[109];
250 unsigned int clkmoddpllcore
; /* offset 0x520 */
251 unsigned int idlestdpllcore
; /* offset 0x524 */
253 unsigned int clkseldpllcore
; /* offset 0x52C */
254 unsigned int resv7
[2];
255 unsigned int divm4dpllcore
; /* offset 0x538 */
256 unsigned int divm5dpllcore
; /* offset 0x53C */
257 unsigned int divm6dpllcore
; /* offset 0x540 */
259 unsigned int resv8
[7];
260 unsigned int clkmoddpllmpu
; /* offset 0x560 */
261 unsigned int idlestdpllmpu
; /* offset 0x564 */
263 unsigned int clkseldpllmpu
; /* offset 0x56c */
264 unsigned int divm2dpllmpu
; /* offset 0x570 */
266 unsigned int resv10
[11];
267 unsigned int clkmoddpllddr
; /* offset 0x5A0 */
268 unsigned int idlestdpllddr
; /* offset 0x5A4 */
270 unsigned int clkseldpllddr
; /* offset 0x5AC */
271 unsigned int divm2dpllddr
; /* offset 0x5B0 */
273 unsigned int resv12
[11];
274 unsigned int clkmoddpllper
; /* offset 0x5E0 */
275 unsigned int idlestdpllper
; /* offset 0x5E4 */
277 unsigned int clkseldpllper
; /* offset 0x5EC */
278 unsigned int divm2dpllper
; /* offset 0x5F0 */
279 unsigned int resv14
[8];
280 unsigned int clkdcoldodpllper
; /* offset 0x614 */
282 unsigned int resv15
[2];
283 unsigned int clkmoddplldisp
; /* offset 0x620 */
284 unsigned int resv16
[2];
285 unsigned int clkseldplldisp
; /* offset 0x62C */
286 unsigned int divm2dplldisp
; /* offset 0x630 */
290 * Encapsulating peripheral functional clocks
294 unsigned int l3clkstctrl
; /* offset 0x00 */
295 unsigned int resv0
[7];
296 unsigned int l3clkctrl
; /* Offset 0x20 */
297 unsigned int resv112
[7];
298 unsigned int l3instrclkctrl
; /* offset 0x40 */
299 unsigned int resv2
[3];
300 unsigned int ocmcramclkctrl
; /* offset 0x50 */
301 unsigned int resv3
[9];
302 unsigned int tpccclkctrl
; /* offset 0x78 */
304 unsigned int tptc0clkctrl
; /* offset 0x80 */
306 unsigned int resv5
[7];
307 unsigned int l4hsclkctrl
; /* offset 0x0A0 */
309 unsigned int l4fwclkctrl
; /* offset 0x0A8 */
310 unsigned int resv7
[85];
311 unsigned int l3sclkstctrl
; /* offset 0x200 */
312 unsigned int resv8
[7];
313 unsigned int gpmcclkctrl
; /* offset 0x220 */
314 unsigned int resv9
[5];
315 unsigned int mcasp0clkctrl
; /* offset 0x238 */
317 unsigned int mcasp1clkctrl
; /* offset 0x240 */
319 unsigned int mmc2clkctrl
; /* offset 0x248 */
320 unsigned int resv12
[3];
321 unsigned int qspiclkctrl
; /* offset 0x258 */
322 unsigned int resv121
;
323 unsigned int usb0clkctrl
; /* offset 0x260 */
324 unsigned int resv122
;
325 unsigned int usb1clkctrl
; /* offset 0x268 */
326 unsigned int resv13
[101];
327 unsigned int l4lsclkstctrl
; /* offset 0x400 */
328 unsigned int resv14
[7];
329 unsigned int l4lsclkctrl
; /* offset 0x420 */
331 unsigned int dcan0clkctrl
; /* offset 0x428 */
333 unsigned int dcan1clkctrl
; /* offset 0x430 */
334 unsigned int resv17
[13];
335 unsigned int elmclkctrl
; /* offset 0x468 */
337 unsigned int resv18
[3];
338 unsigned int gpio1clkctrl
; /* offset 0x478 */
340 unsigned int gpio2clkctrl
; /* offset 0x480 */
342 unsigned int gpio3clkctrl
; /* offset 0x488 */
344 unsigned int gpio4clkctrl
; /* offset 0x490 */
346 unsigned int gpio5clkctrl
; /* offset 0x498 */
347 unsigned int resv21
[3];
349 unsigned int i2c1clkctrl
; /* offset 0x4A8 */
351 unsigned int i2c2clkctrl
; /* offset 0x4B0 */
352 unsigned int resv23
[3];
353 unsigned int mmc0clkctrl
; /* offset 0x4C0 */
355 unsigned int mmc1clkctrl
; /* offset 0x4C8 */
357 unsigned int resv25
[13];
358 unsigned int spi0clkctrl
; /* offset 0x500 */
360 unsigned int spi1clkctrl
; /* offset 0x508 */
361 unsigned int resv27
[9];
362 unsigned int timer2clkctrl
; /* offset 0x530 */
364 unsigned int timer3clkctrl
; /* offset 0x538 */
366 unsigned int timer4clkctrl
; /* offset 0x540 */
367 unsigned int resv30
[5];
368 unsigned int timer7clkctrl
; /* offset 0x558 */
370 unsigned int resv31
[9];
371 unsigned int uart1clkctrl
; /* offset 0x580 */
373 unsigned int uart2clkctrl
; /* offset 0x588 */
375 unsigned int uart3clkctrl
; /* offset 0x590 */
377 unsigned int uart4clkctrl
; /* offset 0x598 */
379 unsigned int uart5clkctrl
; /* offset 0x5A0 */
380 unsigned int resv36
[5];
381 unsigned int usbphyocp2scp0clkctrl
; /* offset 0x5B8 */
382 unsigned int resv361
;
383 unsigned int usbphyocp2scp1clkctrl
; /* offset 0x5C0 */
384 unsigned int resv3611
[79];
386 unsigned int emifclkstctrl
; /* offset 0x700 */
387 unsigned int resv362
[7];
388 unsigned int emifclkctrl
; /* offset 0x720 */
389 unsigned int resv37
[3];
390 unsigned int emiffwclkctrl
; /* offset 0x730 */
391 unsigned int resv371
;
392 unsigned int otfaemifclkctrl
; /* offset 0x738 */
393 unsigned int resv38
[57];
394 unsigned int lcdclkctrl
; /* offset 0x820 */
395 unsigned int resv39
[183];
396 unsigned int cpswclkstctrl
; /* offset 0xB00 */
397 unsigned int resv40
[7];
398 unsigned int cpgmac0clkctrl
; /* offset 0xB20 */
401 struct cm_device_inst
{
402 unsigned int cm_clkout1_ctrl
;
403 unsigned int cm_dll_ctrl
;
406 struct prm_device_inst
{
407 unsigned int prm_rstctrl
;
408 unsigned int prm_rstst
;
413 unsigned int clktimer2clk
; /* offset 0x04 */
414 unsigned int resv2
[11];
415 unsigned int clkselmacclk
; /* offset 0x34 */
417 #endif /* CONFIG_AM43XX */
419 /* Control Module RTC registers */
421 unsigned int rtcclkctrl
; /* offset 0x0 */
422 unsigned int clkstctrl
; /* offset 0x4 */
425 /* Watchdog timer registers */
427 unsigned int resv1
[4];
428 unsigned int wdtwdsc
; /* offset 0x010 */
429 unsigned int wdtwdst
; /* offset 0x014 */
430 unsigned int wdtwisr
; /* offset 0x018 */
431 unsigned int wdtwier
; /* offset 0x01C */
432 unsigned int wdtwwer
; /* offset 0x020 */
433 unsigned int wdtwclr
; /* offset 0x024 */
434 unsigned int wdtwcrr
; /* offset 0x028 */
435 unsigned int wdtwldr
; /* offset 0x02C */
436 unsigned int wdtwtgr
; /* offset 0x030 */
437 unsigned int wdtwwps
; /* offset 0x034 */
438 unsigned int resv2
[3];
439 unsigned int wdtwdly
; /* offset 0x044 */
440 unsigned int wdtwspr
; /* offset 0x048 */
441 unsigned int resv3
[1];
442 unsigned int wdtwqeoi
; /* offset 0x050 */
443 unsigned int wdtwqstar
; /* offset 0x054 */
444 unsigned int wdtwqsta
; /* offset 0x058 */
445 unsigned int wdtwqens
; /* offset 0x05C */
446 unsigned int wdtwqenc
; /* offset 0x060 */
447 unsigned int resv4
[39];
448 unsigned int wdt_unfr
; /* offset 0x100 */
451 /* Timer 32 bit registers */
453 unsigned int tidr
; /* offset 0x00 */
454 unsigned char res1
[12];
455 unsigned int tiocp_cfg
; /* offset 0x10 */
456 unsigned char res2
[12];
457 unsigned int tier
; /* offset 0x20 */
458 unsigned int tistatr
; /* offset 0x24 */
459 unsigned int tistat
; /* offset 0x28 */
460 unsigned int tisr
; /* offset 0x2c */
461 unsigned int tcicr
; /* offset 0x30 */
462 unsigned int twer
; /* offset 0x34 */
463 unsigned int tclr
; /* offset 0x38 */
464 unsigned int tcrr
; /* offset 0x3c */
465 unsigned int tldr
; /* offset 0x40 */
466 unsigned int ttgr
; /* offset 0x44 */
467 unsigned int twpc
; /* offset 0x48 */
468 unsigned int tmar
; /* offset 0x4c */
469 unsigned int tcar1
; /* offset 0x50 */
470 unsigned int tscir
; /* offset 0x54 */
471 unsigned int tcar2
; /* offset 0x58 */
476 unsigned int resv1
[21];
477 unsigned int uartsyscfg
; /* offset 0x54 */
478 unsigned int uartsyssts
; /* offset 0x58 */
483 unsigned int vtp0ctrlreg
;
486 /* Control Status Register */
488 unsigned int resv1
[16];
489 unsigned int statusreg
; /* ofset 0x40 */
490 unsigned int resv2
[51];
491 unsigned int secure_emif_sdram_config
; /* offset 0x0110 */
492 unsigned int resv3
[319];
493 unsigned int dev_attr
;
496 /* AM33XX GPIO registers */
497 #define OMAP_GPIO_REVISION 0x0000
498 #define OMAP_GPIO_SYSCONFIG 0x0010
499 #define OMAP_GPIO_SYSSTATUS 0x0114
500 #define OMAP_GPIO_IRQSTATUS1 0x002c
501 #define OMAP_GPIO_IRQSTATUS2 0x0030
502 #define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
503 #define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
504 #define OMAP_GPIO_CTRL 0x0130
505 #define OMAP_GPIO_OE 0x0134
506 #define OMAP_GPIO_DATAIN 0x0138
507 #define OMAP_GPIO_DATAOUT 0x013c
508 #define OMAP_GPIO_LEVELDETECT0 0x0140
509 #define OMAP_GPIO_LEVELDETECT1 0x0144
510 #define OMAP_GPIO_RISINGDETECT 0x0148
511 #define OMAP_GPIO_FALLINGDETECT 0x014c
512 #define OMAP_GPIO_DEBOUNCE_EN 0x0150
513 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
514 #define OMAP_GPIO_CLEARDATAOUT 0x0190
515 #define OMAP_GPIO_SETDATAOUT 0x0194
517 /* Control Device Register */
519 /* Control Device Register */
520 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
521 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
522 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
525 unsigned int deviceid
; /* offset 0x00 */
526 unsigned int resv1
[7];
527 unsigned int usb_ctrl0
; /* offset 0x20 */
529 unsigned int usb_ctrl1
; /* offset 0x28 */
531 unsigned int macid0l
; /* offset 0x30 */
532 unsigned int macid0h
; /* offset 0x34 */
533 unsigned int macid1l
; /* offset 0x38 */
534 unsigned int macid1h
; /* offset 0x3c */
535 unsigned int resv4
[4];
536 unsigned int miisel
; /* offset 0x50 */
537 unsigned int resv5
[7];
538 unsigned int mreqprio_0
; /* offset 0x70 */
539 unsigned int mreqprio_1
; /* offset 0x74 */
540 unsigned int resv6
[97];
541 unsigned int efuse_sma
; /* offset 0x1FC */
544 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
545 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
546 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
547 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
549 struct l3f_cfg_bwlimiter
{
551 u32 modena_init0_bw_fractional
;
552 u32 modena_init0_bw_integer
;
553 u32 modena_init0_watermark_0
;
556 /* gmii_sel register defines */
557 #define GMII1_SEL_MII 0x0
558 #define GMII1_SEL_RMII 0x1
559 #define GMII1_SEL_RGMII 0x2
560 #define GMII2_SEL_MII 0x0
561 #define GMII2_SEL_RMII 0x4
562 #define GMII2_SEL_RGMII 0x8
563 #define RGMII1_IDMODE BIT(4)
564 #define RGMII2_IDMODE BIT(5)
565 #define RMII1_IO_CLK_EN BIT(6)
566 #define RMII2_IO_CLK_EN BIT(7)
568 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
569 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
570 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
571 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
572 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
577 unsigned int sysconfig
;
578 unsigned int clkconfig
;
579 unsigned int clkstatus
;
581 #define ECAP_CLK_EN BIT(0)
582 #define ECAP_CLK_STOP_REQ BIT(1)
583 #define EPWM_CLK_EN BIT(8)
584 #define EPWM_CLK_STOP_REQ BIT(9)
586 struct pwmss_ecap_regs
{
593 unsigned int resv1
[4];
594 unsigned short ecctl1
;
595 unsigned short ecctl2
;
598 struct pwmss_epwm_regs
{
599 unsigned short tbctl
;
600 unsigned short tbsts
;
601 unsigned short tbphshr
;
602 unsigned short tbphs
;
603 unsigned short tbcnt
;
604 unsigned short tbprd
;
606 unsigned short cmpctl
;
607 unsigned short cmpahr
;
610 unsigned short aqctla
;
611 unsigned short aqctlb
;
612 unsigned short aqsfrc
;
613 unsigned short aqcsfrc
;
614 unsigned short dbctl
;
615 unsigned short dbred
;
616 unsigned short dbfed
;
617 unsigned short tzsel
;
618 unsigned short tzctl
;
619 unsigned short tzflg
;
620 unsigned short tzclr
;
621 unsigned short tzfrc
;
622 unsigned short etsel
;
624 unsigned short etflg
;
625 unsigned short etclr
;
626 unsigned short etfrc
;
627 unsigned short pcctl
;
628 unsigned int res2
[66];
629 unsigned short hrcnfg
;
632 /* Capture Control register 2 */
633 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
634 #define ECTRL2_MDSL_ECAP BIT(9)
635 #define ECTRL2_CTRSTP_FREERUN BIT(4)
636 #define ECTRL2_PLSL_LOW BIT(10)
637 #define ECTRL2_SYNC_EN BIT(5)
639 #endif /* __ASSEMBLY__ */
640 #endif /* __KERNEL_STRICT_NAMES */
642 #endif /* _AM33XX_CPU_H */