arch/arm/include/asm/arch-am33xx/cpu.h

   1 /*
   2  * cpu.h
   3  *
   4  * AM33xx specific header file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _AM33XX_CPU_H
  12 #define _AM33XX_CPU_H
  13
  14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  15 #include <asm/types.h>
  16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  17
  18 #include <asm/arch/hardware.h>
  19
  20 #define BIT(x)                          (1 << x)
  21 #define CL_BIT(x)                       (0 << x)
  22
  23 /* Timer register bits */
  24 #define TCLR_ST                         BIT(0)  /* Start=1 Stop=0 */
  25 #define TCLR_AR                         BIT(1)  /* Auto reload */
  26 #define TCLR_PRE                        BIT(5)  /* Pre-scaler enable */
  27 #define TCLR_PTV_SHIFT                  (2)     /* Pre-scaler shift value */
  28 #define TCLR_PRE_DISABLE                CL_BIT(5) /* Pre-scalar disable */
  29 #define TCLR_CE                         BIT(6)  /* compare mode enable */
  30 #define TCLR_SCPWM                      BIT(7)  /* pwm outpin behaviour */
  31 #define TCLR_TCM                        BIT(8)  /* edge detection of input pin*/
  32 #define TCLR_TRG_SHIFT                  (10)    /* trigmode on pwm outpin */
  33 #define TCLR_PT                         BIT(12) /* pulse/toggle mode of outpin*/
  34 #define TCLR_CAPTMODE                   BIT(13) /* capture mode */
  35 #define TCLR_GPOCFG                     BIT(14) /* 0=output,1=input */
  36
  37 #define TCFG_RESET                      BIT(0)  /* software reset */
  38 #define TCFG_EMUFREE                    BIT(1)  /* behaviour of tmr on debug */
  39 #define TCFG_IDLEMOD_SHIFT              (2)     /* power management */
  40 /* device type */
  41 #define DEVICE_MASK                     (BIT(8) | BIT(9) | BIT(10))
  42 #define TST_DEVICE                      0x0
  43 #define EMU_DEVICE                      0x1
  44 #define HS_DEVICE                       0x2
  45 #define GP_DEVICE                       0x3
  46
  47 /* cpu-id for AM33XX and TI81XX family */
  48 #define AM335X                          0xB944
  49 #define TI81XX                          0xB81E
  50 #define DEVICE_ID                       (CTRL_BASE + 0x0600)
  51 #define DEVICE_ID_MASK                  0x1FFF
  52
  53 /* MPU max frequencies */
  54 #define AM335X_ZCZ_300                  0x1FEF
  55 #define AM335X_ZCZ_600                  0x1FAF
  56 #define AM335X_ZCZ_720                  0x1F2F
  57 #define AM335X_ZCZ_800                  0x1E2F
  58 #define AM335X_ZCZ_1000                 0x1C2F
  59 #define AM335X_ZCE_300                  0x1FDF
  60 #define AM335X_ZCE_600                  0x1F9F
  61
  62 /* This gives the status of the boot mode pins on the evm */
  63 #define SYSBOOT_MASK                    (BIT(0) | BIT(1) | BIT(2)\
  64                                         | BIT(3) | BIT(4))
  65
  66 #define PRM_RSTCTRL_RESET               0x01
  67 #define PRM_RSTST_WARM_RESET_MASK       0x232
  68
  69 /*
  70  * Watchdog:
  71  * Using the prescaler, the OMAP watchdog could go for many
  72  * months before firing.  These limits work without scaling,
  73  * with the 60 second default assumed by most tools and docs.
  74  */
  75 #define TIMER_MARGIN_MAX        (24 * 60 * 60)  /* 1 day */
  76 #define TIMER_MARGIN_DEFAULT    60      /* 60 secs */
  77 #define TIMER_MARGIN_MIN        1
  78
  79 #define PTV                     0       /* prescale */
  80 #define GET_WLDR_VAL(secs)      (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
  81 #define WDT_WWPS_PEND_WCLR      BIT(0)
  82 #define WDT_WWPS_PEND_WLDR      BIT(2)
  83 #define WDT_WWPS_PEND_WTGR      BIT(3)
  84 #define WDT_WWPS_PEND_WSPR      BIT(4)
  85
  86 #define WDT_WCLR_PRE            BIT(5)
  87 #define WDT_WCLR_PTV_OFF        2
  88
  89 #ifndef __KERNEL_STRICT_NAMES
  90 #ifndef __ASSEMBLY__
  91
  92
  93 #ifndef CONFIG_AM43XX
  94 /* Encapsulating core pll registers */
  95 struct cm_wkuppll {
  96         unsigned int wkclkstctrl;       /* offset 0x00 */
  97         unsigned int wkctrlclkctrl;     /* offset 0x04 */
  98         unsigned int wkgpio0clkctrl;    /* offset 0x08 */
  99         unsigned int wkl4wkclkctrl;     /* offset 0x0c */
 100         unsigned int timer0clkctrl;     /* offset 0x10 */
 101         unsigned int resv2[3];
 102         unsigned int idlestdpllmpu;     /* offset 0x20 */
 103         unsigned int resv3[2];
 104         unsigned int clkseldpllmpu;     /* offset 0x2c */
 105         unsigned int resv4[1];
 106         unsigned int idlestdpllddr;     /* offset 0x34 */
 107         unsigned int resv5[2];
 108         unsigned int clkseldpllddr;     /* offset 0x40 */
 109         unsigned int resv6[4];
 110         unsigned int clkseldplldisp;    /* offset 0x54 */
 111         unsigned int resv7[1];
 112         unsigned int idlestdpllcore;    /* offset 0x5c */
 113         unsigned int resv8[2];
 114         unsigned int clkseldpllcore;    /* offset 0x68 */
 115         unsigned int resv9[1];
 116         unsigned int idlestdpllper;     /* offset 0x70 */
 117         unsigned int resv10[2];
 118         unsigned int clkdcoldodpllper;  /* offset 0x7c */
 119         unsigned int divm4dpllcore;     /* offset 0x80 */
 120         unsigned int divm5dpllcore;     /* offset 0x84 */
 121         unsigned int clkmoddpllmpu;     /* offset 0x88 */
 122         unsigned int clkmoddpllper;     /* offset 0x8c */
 123         unsigned int clkmoddpllcore;    /* offset 0x90 */
 124         unsigned int clkmoddpllddr;     /* offset 0x94 */
 125         unsigned int clkmoddplldisp;    /* offset 0x98 */
 126         unsigned int clkseldpllper;     /* offset 0x9c */
 127         unsigned int divm2dpllddr;      /* offset 0xA0 */
 128         unsigned int divm2dplldisp;     /* offset 0xA4 */
 129         unsigned int divm2dpllmpu;      /* offset 0xA8 */
 130         unsigned int divm2dpllper;      /* offset 0xAC */
 131         unsigned int resv11[1];
 132         unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
 133         unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
 134         unsigned int wkup_adctscctrl;   /* offset 0xBC */
 135         unsigned int resv12;
 136         unsigned int timer1clkctrl;     /* offset 0xC4 */
 137         unsigned int resv13[4];
 138         unsigned int divm6dpllcore;     /* offset 0xD8 */
 139 };
 140
 141 /**
 142  * Encapsulating peripheral functional clocks
 143  * pll registers
 144  */
 145 struct cm_perpll {
 146         unsigned int l4lsclkstctrl;     /* offset 0x00 */
 147         unsigned int l3sclkstctrl;      /* offset 0x04 */
 148         unsigned int l4fwclkstctrl;     /* offset 0x08 */
 149         unsigned int l3clkstctrl;       /* offset 0x0c */
 150         unsigned int resv1;
 151         unsigned int cpgmac0clkctrl;    /* offset 0x14 */
 152         unsigned int lcdclkctrl;        /* offset 0x18 */
 153         unsigned int usb0clkctrl;       /* offset 0x1C */
 154         unsigned int resv2;
 155         unsigned int tptc0clkctrl;      /* offset 0x24 */
 156         unsigned int emifclkctrl;       /* offset 0x28 */
 157         unsigned int ocmcramclkctrl;    /* offset 0x2c */
 158         unsigned int gpmcclkctrl;       /* offset 0x30 */
 159         unsigned int mcasp0clkctrl;     /* offset 0x34 */
 160         unsigned int uart5clkctrl;      /* offset 0x38 */
 161         unsigned int mmc0clkctrl;       /* offset 0x3C */
 162         unsigned int elmclkctrl;        /* offset 0x40 */
 163         unsigned int i2c2clkctrl;       /* offset 0x44 */
 164         unsigned int i2c1clkctrl;       /* offset 0x48 */
 165         unsigned int spi0clkctrl;       /* offset 0x4C */
 166         unsigned int spi1clkctrl;       /* offset 0x50 */
 167         unsigned int resv3[3];
 168         unsigned int l4lsclkctrl;       /* offset 0x60 */
 169         unsigned int l4fwclkctrl;       /* offset 0x64 */
 170         unsigned int mcasp1clkctrl;     /* offset 0x68 */
 171         unsigned int uart1clkctrl;      /* offset 0x6C */
 172         unsigned int uart2clkctrl;      /* offset 0x70 */
 173         unsigned int uart3clkctrl;      /* offset 0x74 */
 174         unsigned int uart4clkctrl;      /* offset 0x78 */
 175         unsigned int timer7clkctrl;     /* offset 0x7C */
 176         unsigned int timer2clkctrl;     /* offset 0x80 */
 177         unsigned int timer3clkctrl;     /* offset 0x84 */
 178         unsigned int timer4clkctrl;     /* offset 0x88 */
 179         unsigned int resv4[8];
 180         unsigned int gpio1clkctrl;      /* offset 0xAC */
 181         unsigned int gpio2clkctrl;      /* offset 0xB0 */
 182         unsigned int gpio3clkctrl;      /* offset 0xB4 */
 183         unsigned int resv5;
 184         unsigned int tpccclkctrl;       /* offset 0xBC */
 185         unsigned int dcan0clkctrl;      /* offset 0xC0 */
 186         unsigned int dcan1clkctrl;      /* offset 0xC4 */
 187         unsigned int resv6;
 188         unsigned int epwmss1clkctrl;    /* offset 0xCC */
 189         unsigned int emiffwclkctrl;     /* offset 0xD0 */
 190         unsigned int epwmss0clkctrl;    /* offset 0xD4 */
 191         unsigned int epwmss2clkctrl;    /* offset 0xD8 */
 192         unsigned int l3instrclkctrl;    /* offset 0xDC */
 193         unsigned int l3clkctrl;         /* Offset 0xE0 */
 194         unsigned int resv8[2];
 195         unsigned int timer5clkctrl;     /* offset 0xEC */
 196         unsigned int timer6clkctrl;     /* offset 0xF0 */
 197         unsigned int mmc1clkctrl;       /* offset 0xF4 */
 198         unsigned int mmc2clkctrl;       /* offset 0xF8 */
 199         unsigned int resv9[8];
 200         unsigned int l4hsclkstctrl;     /* offset 0x11C */
 201         unsigned int l4hsclkctrl;       /* offset 0x120 */
 202         unsigned int resv10[8];
 203         unsigned int cpswclkstctrl;     /* offset 0x144 */
 204         unsigned int lcdcclkstctrl;     /* offset 0x148 */
 205 };
 206
 207 /* Encapsulating Display pll registers */
 208 struct cm_dpll {
 209         unsigned int resv1;
 210         unsigned int clktimer7clk;      /* offset 0x04 */
 211         unsigned int clktimer2clk;      /* offset 0x08 */
 212         unsigned int clktimer3clk;      /* offset 0x0C */
 213         unsigned int clktimer4clk;      /* offset 0x10 */
 214         unsigned int resv2;
 215         unsigned int clktimer5clk;      /* offset 0x18 */
 216         unsigned int clktimer6clk;      /* offset 0x1C */
 217         unsigned int resv3[2];
 218         unsigned int clktimer1clk;      /* offset 0x28 */
 219         unsigned int resv4[2];
 220         unsigned int clklcdcpixelclk;   /* offset 0x34 */
 221 };
 222
 223 struct prm_device_inst {
 224         unsigned int prm_rstctrl;
 225         unsigned int prm_rsttime;
 226         unsigned int prm_rstst;
 227 };
 228 #else
 229 /* Encapsulating core pll registers */
 230 struct cm_wkuppll {
 231         unsigned int resv0[136];
 232         unsigned int wkl4wkclkctrl;     /* offset 0x220 */
 233         unsigned int resv1[55];
 234         unsigned int wkclkstctrl;       /* offset 0x300 */
 235         unsigned int resv2[15];
 236         unsigned int wkup_i2c0ctrl;     /* offset 0x340 */
 237         unsigned int resv3;
 238         unsigned int wkup_uart0ctrl;    /* offset 0x348 */
 239         unsigned int resv4[5];
 240         unsigned int wkctrlclkctrl;     /* offset 0x360 */
 241         unsigned int resv5;
 242         unsigned int wkgpio0clkctrl;    /* offset 0x368 */
 243
 244         unsigned int resv6[109];
 245         unsigned int clkmoddpllcore;    /* offset 0x520 */
 246         unsigned int idlestdpllcore;    /* offset 0x524 */
 247         unsigned int resv61;
 248         unsigned int clkseldpllcore;    /* offset 0x52C */
 249         unsigned int resv7[2];
 250         unsigned int divm4dpllcore;     /* offset 0x538 */
 251         unsigned int divm5dpllcore;     /* offset 0x53C */
 252         unsigned int divm6dpllcore;     /* offset 0x540 */
 253
 254         unsigned int resv8[7];
 255         unsigned int clkmoddpllmpu;     /* offset 0x560 */
 256         unsigned int idlestdpllmpu;     /* offset 0x564 */
 257         unsigned int resv9;
 258         unsigned int clkseldpllmpu;     /* offset 0x56c */
 259         unsigned int divm2dpllmpu;      /* offset 0x570 */
 260
 261         unsigned int resv10[11];
 262         unsigned int clkmoddpllddr;     /* offset 0x5A0 */
 263         unsigned int idlestdpllddr;     /* offset 0x5A4 */
 264         unsigned int resv11;
 265         unsigned int clkseldpllddr;     /* offset 0x5AC */
 266         unsigned int divm2dpllddr;      /* offset 0x5B0 */
 267
 268         unsigned int resv12[11];
 269         unsigned int clkmoddpllper;     /* offset 0x5E0 */
 270         unsigned int idlestdpllper;     /* offset 0x5E4 */
 271         unsigned int resv13;
 272         unsigned int clkseldpllper;     /* offset 0x5EC */
 273         unsigned int divm2dpllper;      /* offset 0x5F0 */
 274         unsigned int resv14[8];
 275         unsigned int clkdcoldodpllper;  /* offset 0x614 */
 276
 277         unsigned int resv15[2];
 278         unsigned int clkmoddplldisp;    /* offset 0x620 */
 279         unsigned int resv16[2];
 280         unsigned int clkseldplldisp;    /* offset 0x62C */
 281         unsigned int divm2dplldisp;     /* offset 0x630 */
 282 };
 283
 284 /*
 285  * Encapsulating peripheral functional clocks
 286  * pll registers
 287  */
 288 struct cm_perpll {
 289         unsigned int l3clkstctrl;       /* offset 0x00 */
 290         unsigned int resv0[7];
 291         unsigned int l3clkctrl;         /* Offset 0x20 */
 292         unsigned int resv1[7];
 293         unsigned int l3instrclkctrl;    /* offset 0x40 */
 294         unsigned int resv2[3];
 295         unsigned int ocmcramclkctrl;    /* offset 0x50 */
 296         unsigned int resv3[9];
 297         unsigned int tpccclkctrl;       /* offset 0x78 */
 298         unsigned int resv4;
 299         unsigned int tptc0clkctrl;      /* offset 0x80 */
 300
 301         unsigned int resv5[7];
 302         unsigned int l4hsclkctrl;       /* offset 0x0A0 */
 303         unsigned int resv6;
 304         unsigned int l4fwclkctrl;       /* offset 0x0A8 */
 305         unsigned int resv7[85];
 306         unsigned int l3sclkstctrl;      /* offset 0x200 */
 307         unsigned int resv8[7];
 308         unsigned int gpmcclkctrl;       /* offset 0x220 */
 309         unsigned int resv9[5];
 310         unsigned int mcasp0clkctrl;     /* offset 0x238 */
 311         unsigned int resv10;
 312         unsigned int mcasp1clkctrl;     /* offset 0x240 */
 313         unsigned int resv11;
 314         unsigned int mmc2clkctrl;       /* offset 0x248 */
 315         unsigned int resv12[3];
 316         unsigned int qspiclkctrl;       /* offset 0x258 */
 317         unsigned int resv121;
 318         unsigned int usb0clkctrl;       /* offset 0x260 */
 319         unsigned int resv13[103];
 320         unsigned int l4lsclkstctrl;     /* offset 0x400 */
 321         unsigned int resv14[7];
 322         unsigned int l4lsclkctrl;       /* offset 0x420 */
 323         unsigned int resv15;
 324         unsigned int dcan0clkctrl;      /* offset 0x428 */
 325         unsigned int resv16;
 326         unsigned int dcan1clkctrl;      /* offset 0x430 */
 327         unsigned int resv17[13];
 328         unsigned int elmclkctrl;        /* offset 0x468 */
 329
 330         unsigned int resv18[3];
 331         unsigned int gpio1clkctrl;      /* offset 0x478 */
 332         unsigned int resv19;
 333         unsigned int gpio2clkctrl;      /* offset 0x480 */
 334         unsigned int resv20;
 335         unsigned int gpio3clkctrl;      /* offset 0x488 */
 336         unsigned int resv41;
 337         unsigned int gpio4clkctrl;      /* offset 0x490 */
 338         unsigned int resv42;
 339         unsigned int gpio5clkctrl;      /* offset 0x498 */
 340         unsigned int resv21[3];
 341
 342         unsigned int i2c1clkctrl;       /* offset 0x4A8 */
 343         unsigned int resv22;
 344         unsigned int i2c2clkctrl;       /* offset 0x4B0 */
 345         unsigned int resv23[3];
 346         unsigned int mmc0clkctrl;       /* offset 0x4C0 */
 347         unsigned int resv24;
 348         unsigned int mmc1clkctrl;       /* offset 0x4C8 */
 349
 350         unsigned int resv25[13];
 351         unsigned int spi0clkctrl;       /* offset 0x500 */
 352         unsigned int resv26;
 353         unsigned int spi1clkctrl;       /* offset 0x508 */
 354         unsigned int resv27[9];
 355         unsigned int timer2clkctrl;     /* offset 0x530 */
 356         unsigned int resv28;
 357         unsigned int timer3clkctrl;     /* offset 0x538 */
 358         unsigned int resv29;
 359         unsigned int timer4clkctrl;     /* offset 0x540 */
 360         unsigned int resv30[5];
 361         unsigned int timer7clkctrl;     /* offset 0x558 */
 362
 363         unsigned int resv31[9];
 364         unsigned int uart1clkctrl;      /* offset 0x580 */
 365         unsigned int resv32;
 366         unsigned int uart2clkctrl;      /* offset 0x588 */
 367         unsigned int resv33;
 368         unsigned int uart3clkctrl;      /* offset 0x590 */
 369         unsigned int resv34;
 370         unsigned int uart4clkctrl;      /* offset 0x598 */
 371         unsigned int resv35;
 372         unsigned int uart5clkctrl;      /* offset 0x5A0 */
 373         unsigned int resv36[87];
 374
 375         unsigned int emifclkstctrl;     /* offset 0x700 */
 376         unsigned int resv361[7];
 377         unsigned int emifclkctrl;       /* offset 0x720 */
 378         unsigned int resv37[3];
 379         unsigned int emiffwclkctrl;     /* offset 0x730 */
 380         unsigned int resv371;
 381         unsigned int otfaemifclkctrl;   /* offset 0x738 */
 382         unsigned int resv38[57];
 383         unsigned int lcdclkctrl;        /* offset 0x820 */
 384         unsigned int resv39[183];
 385         unsigned int cpswclkstctrl;     /* offset 0xB00 */
 386         unsigned int resv40[7];
 387         unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 388 };
 389
 390 struct cm_device_inst {
 391         unsigned int cm_clkout1_ctrl;
 392         unsigned int cm_dll_ctrl;
 393 };
 394
 395 struct prm_device_inst {
 396         unsigned int prm_rstctrl;
 397         unsigned int prm_rstst;
 398 };
 399
 400 struct cm_dpll {
 401         unsigned int resv1;
 402         unsigned int clktimer2clk;      /* offset 0x04 */
 403         unsigned int resv2[11];
 404         unsigned int clkselmacclk;      /* offset 0x34 */
 405 };
 406 #endif /* CONFIG_AM43XX */
 407
 408 /* Control Module RTC registers */
 409 struct cm_rtc {
 410         unsigned int rtcclkctrl;        /* offset 0x0 */
 411         unsigned int clkstctrl;         /* offset 0x4 */
 412 };
 413
 414 /* Watchdog timer registers */
 415 struct wd_timer {
 416         unsigned int resv1[4];
 417         unsigned int wdtwdsc;   /* offset 0x010 */
 418         unsigned int wdtwdst;   /* offset 0x014 */
 419         unsigned int wdtwisr;   /* offset 0x018 */
 420         unsigned int wdtwier;   /* offset 0x01C */
 421         unsigned int wdtwwer;   /* offset 0x020 */
 422         unsigned int wdtwclr;   /* offset 0x024 */
 423         unsigned int wdtwcrr;   /* offset 0x028 */
 424         unsigned int wdtwldr;   /* offset 0x02C */
 425         unsigned int wdtwtgr;   /* offset 0x030 */
 426         unsigned int wdtwwps;   /* offset 0x034 */
 427         unsigned int resv2[3];
 428         unsigned int wdtwdly;   /* offset 0x044 */
 429         unsigned int wdtwspr;   /* offset 0x048 */
 430         unsigned int resv3[1];
 431         unsigned int wdtwqeoi;  /* offset 0x050 */
 432         unsigned int wdtwqstar; /* offset 0x054 */
 433         unsigned int wdtwqsta;  /* offset 0x058 */
 434         unsigned int wdtwqens;  /* offset 0x05C */
 435         unsigned int wdtwqenc;  /* offset 0x060 */
 436         unsigned int resv4[39];
 437         unsigned int wdt_unfr;  /* offset 0x100 */
 438 };
 439
 440 /* Timer 32 bit registers */
 441 struct gptimer {
 442         unsigned int tidr;              /* offset 0x00 */
 443         unsigned char res1[12];
 444         unsigned int tiocp_cfg;         /* offset 0x10 */
 445         unsigned char res2[12];
 446         unsigned int tier;              /* offset 0x20 */
 447         unsigned int tistatr;           /* offset 0x24 */
 448         unsigned int tistat;            /* offset 0x28 */
 449         unsigned int tisr;              /* offset 0x2c */
 450         unsigned int tcicr;             /* offset 0x30 */
 451         unsigned int twer;              /* offset 0x34 */
 452         unsigned int tclr;              /* offset 0x38 */
 453         unsigned int tcrr;              /* offset 0x3c */
 454         unsigned int tldr;              /* offset 0x40 */
 455         unsigned int ttgr;              /* offset 0x44 */
 456         unsigned int twpc;              /* offset 0x48 */
 457         unsigned int tmar;              /* offset 0x4c */
 458         unsigned int tcar1;             /* offset 0x50 */
 459         unsigned int tscir;             /* offset 0x54 */
 460         unsigned int tcar2;             /* offset 0x58 */
 461 };
 462
 463 /* UART Registers */
 464 struct uart_sys {
 465         unsigned int resv1[21];
 466         unsigned int uartsyscfg;        /* offset 0x54 */
 467         unsigned int uartsyssts;        /* offset 0x58 */
 468 };
 469
 470 /* VTP Registers */
 471 struct vtp_reg {
 472         unsigned int vtp0ctrlreg;
 473 };
 474
 475 /* Control Status Register */
 476 struct ctrl_stat {
 477         unsigned int resv1[16];
 478         unsigned int statusreg;         /* ofset 0x40 */
 479         unsigned int resv2[51];
 480         unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
 481         unsigned int resv3[319];
 482         unsigned int dev_attr;
 483 };
 484
 485 /* AM33XX GPIO registers */
 486 #define OMAP_GPIO_REVISION              0x0000
 487 #define OMAP_GPIO_SYSCONFIG             0x0010
 488 #define OMAP_GPIO_SYSSTATUS             0x0114
 489 #define OMAP_GPIO_IRQSTATUS1            0x002c
 490 #define OMAP_GPIO_IRQSTATUS2            0x0030
 491 #define OMAP_GPIO_CTRL                  0x0130
 492 #define OMAP_GPIO_OE                    0x0134
 493 #define OMAP_GPIO_DATAIN                0x0138
 494 #define OMAP_GPIO_DATAOUT               0x013c
 495 #define OMAP_GPIO_LEVELDETECT0          0x0140
 496 #define OMAP_GPIO_LEVELDETECT1          0x0144
 497 #define OMAP_GPIO_RISINGDETECT          0x0148
 498 #define OMAP_GPIO_FALLINGDETECT         0x014c
 499 #define OMAP_GPIO_DEBOUNCE_EN           0x0150
 500 #define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 501 #define OMAP_GPIO_CLEARDATAOUT          0x0190
 502 #define OMAP_GPIO_SETDATAOUT            0x0194
 503
 504 /* Control Device Register */
 505
 506  /* Control Device Register */
 507 #define MREQPRIO_0_SAB_INIT1_MASK       0xFFFFFF8F
 508 #define MREQPRIO_0_SAB_INIT0_MASK       0xFFFFFFF8
 509 #define MREQPRIO_1_DSS_MASK             0xFFFFFF8F
 510
 511 struct ctrl_dev {
 512         unsigned int deviceid;          /* offset 0x00 */
 513         unsigned int resv1[7];
 514         unsigned int usb_ctrl0;         /* offset 0x20 */
 515         unsigned int resv2;
 516         unsigned int usb_ctrl1;         /* offset 0x28 */
 517         unsigned int resv3;
 518         unsigned int macid0l;           /* offset 0x30 */
 519         unsigned int macid0h;           /* offset 0x34 */
 520         unsigned int macid1l;           /* offset 0x38 */
 521         unsigned int macid1h;           /* offset 0x3c */
 522         unsigned int resv4[4];
 523         unsigned int miisel;            /* offset 0x50 */
 524         unsigned int resv5[7];
 525         unsigned int mreqprio_0;        /* offset 0x70 */
 526         unsigned int mreqprio_1;        /* offset 0x74 */
 527         unsigned int resv6[97];
 528         unsigned int efuse_sma;         /* offset 0x1FC */
 529 };
 530
 531 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
 532 #define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
 533 #define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
 534 #define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
 535
 536 struct l3f_cfg_bwlimiter {
 537         u32 padding0[2];
 538         u32 modena_init0_bw_fractional;
 539         u32 modena_init0_bw_integer;
 540         u32 modena_init0_watermark_0;
 541 };
 542
 543 /* gmii_sel register defines */
 544 #define GMII1_SEL_MII           0x0
 545 #define GMII1_SEL_RMII          0x1
 546 #define GMII1_SEL_RGMII         0x2
 547 #define GMII2_SEL_MII           0x0
 548 #define GMII2_SEL_RMII          0x4
 549 #define GMII2_SEL_RGMII         0x8
 550 #define RGMII1_IDMODE           BIT(4)
 551 #define RGMII2_IDMODE           BIT(5)
 552 #define RMII1_IO_CLK_EN         BIT(6)
 553 #define RMII2_IO_CLK_EN         BIT(7)
 554
 555 #define MII_MODE_ENABLE         (GMII1_SEL_MII | GMII2_SEL_MII)
 556 #define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
 557 #define RGMII_MODE_ENABLE       (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 558 #define RGMII_INT_DELAY         (RGMII1_IDMODE | RGMII2_IDMODE)
 559 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 560
 561 /* PWMSS */
 562 struct pwmss_regs {
 563         unsigned int idver;
 564         unsigned int sysconfig;
 565         unsigned int clkconfig;
 566         unsigned int clkstatus;
 567 };
 568 #define ECAP_CLK_EN             BIT(0)
 569 #define ECAP_CLK_STOP_REQ       BIT(1)
 570
 571 struct pwmss_ecap_regs {
 572         unsigned int tsctr;
 573         unsigned int ctrphs;
 574         unsigned int cap1;
 575         unsigned int cap2;
 576         unsigned int cap3;
 577         unsigned int cap4;
 578         unsigned int resv1[4];
 579         unsigned short ecctl1;
 580         unsigned short ecctl2;
 581 };
 582
 583 /* Capture Control register 2 */
 584 #define ECTRL2_SYNCOSEL_MASK    (0x03 << 6)
 585 #define ECTRL2_MDSL_ECAP        BIT(9)
 586 #define ECTRL2_CTRSTP_FREERUN   BIT(4)
 587 #define ECTRL2_PLSL_LOW         BIT(10)
 588 #define ECTRL2_SYNC_EN          BIT(5)
 589
 590 #endif /* __ASSEMBLY__ */
 591 #endif /* __KERNEL_STRICT_NAMES */
 592
 593 #endif /* _AM33XX_CPU_H */