arch/arm/include/asm/arch-am33xx/mux_am33xx.h

   1 /*
   2  * mux_am33xx.h
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _MUX_AM33XX_H_
  17 #define _MUX_AM33XX_H_
  18
  19 #include <common.h>
  20 #include <asm/io.h>
  21
  22 #define MUX_CFG(value, offset)  \
  23         __raw_writel(value, (CTRL_BASE + offset));
  24
  25 /* PAD Control Fields */
  26 #define SLEWCTRL        (0x1 << 6)
  27 #define RXACTIVE        (0x1 << 5)
  28 #define PULLDOWN_EN     (0x0 << 4) /* Pull Down Selection */
  29 #define PULLUP_EN       (0x1 << 4) /* Pull Up Selection */
  30 #define PULLUDEN        (0x0 << 3) /* Pull up enabled */
  31 #define PULLUDDIS       (0x1 << 3) /* Pull up disabled */
  32 #define MODE(val)       val     /* used for Readability */
  33
  34 /*
  35  * PAD CONTROL OFFSETS
  36  * Field names corresponds to the pad signal name
  37  */
  38 struct pad_signals {
  39         int gpmc_ad0;
  40         int gpmc_ad1;
  41         int gpmc_ad2;
  42         int gpmc_ad3;
  43         int gpmc_ad4;
  44         int gpmc_ad5;
  45         int gpmc_ad6;
  46         int gpmc_ad7;
  47         int gpmc_ad8;
  48         int gpmc_ad9;
  49         int gpmc_ad10;
  50         int gpmc_ad11;
  51         int gpmc_ad12;
  52         int gpmc_ad13;
  53         int gpmc_ad14;
  54         int gpmc_ad15;
  55         int gpmc_a0;
  56         int gpmc_a1;
  57         int gpmc_a2;
  58         int gpmc_a3;
  59         int gpmc_a4;
  60         int gpmc_a5;
  61         int gpmc_a6;
  62         int gpmc_a7;
  63         int gpmc_a8;
  64         int gpmc_a9;
  65         int gpmc_a10;
  66         int gpmc_a11;
  67         int gpmc_wait0;
  68         int gpmc_wpn;
  69         int gpmc_be1n;
  70         int gpmc_csn0;
  71         int gpmc_csn1;
  72         int gpmc_csn2;
  73         int gpmc_csn3;
  74         int gpmc_clk;
  75         int gpmc_advn_ale;
  76         int gpmc_oen_ren;
  77         int gpmc_wen;
  78         int gpmc_be0n_cle;
  79         int lcd_data0;
  80         int lcd_data1;
  81         int lcd_data2;
  82         int lcd_data3;
  83         int lcd_data4;
  84         int lcd_data5;
  85         int lcd_data6;
  86         int lcd_data7;
  87         int lcd_data8;
  88         int lcd_data9;
  89         int lcd_data10;
  90         int lcd_data11;
  91         int lcd_data12;
  92         int lcd_data13;
  93         int lcd_data14;
  94         int lcd_data15;
  95         int lcd_vsync;
  96         int lcd_hsync;
  97         int lcd_pclk;
  98         int lcd_ac_bias_en;
  99         int mmc0_dat3;
 100         int mmc0_dat2;
 101         int mmc0_dat1;
 102         int mmc0_dat0;
 103         int mmc0_clk;
 104         int mmc0_cmd;
 105         int mii1_col;
 106         int mii1_crs;
 107         int mii1_rxerr;
 108         int mii1_txen;
 109         int mii1_rxdv;
 110         int mii1_txd3;
 111         int mii1_txd2;
 112         int mii1_txd1;
 113         int mii1_txd0;
 114         int mii1_txclk;
 115         int mii1_rxclk;
 116         int mii1_rxd3;
 117         int mii1_rxd2;
 118         int mii1_rxd1;
 119         int mii1_rxd0;
 120         int rmii1_refclk;
 121         int mdio_data;
 122         int mdio_clk;
 123         int spi0_sclk;
 124         int spi0_d0;
 125         int spi0_d1;
 126         int spi0_cs0;
 127         int spi0_cs1;
 128         int ecap0_in_pwm0_out;
 129         int uart0_ctsn;
 130         int uart0_rtsn;
 131         int uart0_rxd;
 132         int uart0_txd;
 133         int uart1_ctsn;
 134         int uart1_rtsn;
 135         int uart1_rxd;
 136         int uart1_txd;
 137         int i2c0_sda;
 138         int i2c0_scl;
 139         int mcasp0_aclkx;
 140         int mcasp0_fsx;
 141         int mcasp0_axr0;
 142         int mcasp0_ahclkr;
 143         int mcasp0_aclkr;
 144         int mcasp0_fsr;
 145         int mcasp0_axr1;
 146         int mcasp0_ahclkx;
 147         int xdma_event_intr0;
 148         int xdma_event_intr1;
 149         int nresetin_out;
 150         int porz;
 151         int nnmi;
 152         int osc0_in;
 153         int osc0_out;
 154         int rsvd1;
 155         int tms;
 156         int tdi;
 157         int tdo;
 158         int tck;
 159         int ntrst;
 160         int emu0;
 161         int emu1;
 162         int osc1_in;
 163         int osc1_out;
 164         int pmic_power_en;
 165         int rtc_porz;
 166         int rsvd2;
 167         int ext_wakeup;
 168         int enz_kaldo_1p8v;
 169         int usb0_dm;
 170         int usb0_dp;
 171         int usb0_ce;
 172         int usb0_id;
 173         int usb0_vbus;
 174         int usb0_drvvbus;
 175         int usb1_dm;
 176         int usb1_dp;
 177         int usb1_ce;
 178         int usb1_id;
 179         int usb1_vbus;
 180         int usb1_drvvbus;
 181         int ddr_resetn;
 182         int ddr_csn0;
 183         int ddr_cke;
 184         int ddr_ck;
 185         int ddr_nck;
 186         int ddr_casn;
 187         int ddr_rasn;
 188         int ddr_wen;
 189         int ddr_ba0;
 190         int ddr_ba1;
 191         int ddr_ba2;
 192         int ddr_a0;
 193         int ddr_a1;
 194         int ddr_a2;
 195         int ddr_a3;
 196         int ddr_a4;
 197         int ddr_a5;
 198         int ddr_a6;
 199         int ddr_a7;
 200         int ddr_a8;
 201         int ddr_a9;
 202         int ddr_a10;
 203         int ddr_a11;
 204         int ddr_a12;
 205         int ddr_a13;
 206         int ddr_a14;
 207         int ddr_a15;
 208         int ddr_odt;
 209         int ddr_d0;
 210         int ddr_d1;
 211         int ddr_d2;
 212         int ddr_d3;
 213         int ddr_d4;
 214         int ddr_d5;
 215         int ddr_d6;
 216         int ddr_d7;
 217         int ddr_d8;
 218         int ddr_d9;
 219         int ddr_d10;
 220         int ddr_d11;
 221         int ddr_d12;
 222         int ddr_d13;
 223         int ddr_d14;
 224         int ddr_d15;
 225         int ddr_dqm0;
 226         int ddr_dqm1;
 227         int ddr_dqs0;
 228         int ddr_dqsn0;
 229         int ddr_dqs1;
 230         int ddr_dqsn1;
 231         int ddr_vref;
 232         int ddr_vtp;
 233         int ddr_strben0;
 234         int ddr_strben1;
 235         int ain7;
 236         int ain6;
 237         int ain5;
 238         int ain4;
 239         int ain3;
 240         int ain2;
 241         int ain1;
 242         int ain0;
 243         int vrefp;
 244         int vrefn;
 245 };
 246
 247 #endif /* endif _MUX_AM33XX_H_ */