arch/arm/include/asm/arch-davinci/i2c_defs.h

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 #ifndef _DAVINCI_I2C_H_
  26 #define _DAVINCI_I2C_H_
  27
  28 #define I2C_WRITE               0
  29 #define I2C_READ                1
  30
  31 #ifndef CONFIG_SOC_DA8XX
  32 #define I2C_BASE                0x01c21000
  33 #else
  34 #define I2C_BASE                0x01c22000
  35 #endif
  36
  37 #define I2C_OA                  (I2C_BASE + 0x00)
  38 #define I2C_IE                  (I2C_BASE + 0x04)
  39 #define I2C_STAT                (I2C_BASE + 0x08)
  40 #define I2C_SCLL                (I2C_BASE + 0x0c)
  41 #define I2C_SCLH                (I2C_BASE + 0x10)
  42 #define I2C_CNT                 (I2C_BASE + 0x14)
  43 #define I2C_DRR                 (I2C_BASE + 0x18)
  44 #define I2C_SA                  (I2C_BASE + 0x1c)
  45 #define I2C_DXR                 (I2C_BASE + 0x20)
  46 #define I2C_CON                 (I2C_BASE + 0x24)
  47 #define I2C_IV                  (I2C_BASE + 0x28)
  48 #define I2C_PSC                 (I2C_BASE + 0x30)
  49
  50 /* I2C masks */
  51
  52 /* I2C Interrupt Enable Register (I2C_IE): */
  53 #define I2C_IE_SCD_IE   (1 << 5)        /* Stop condition detect interrupt enable */
  54 #define I2C_IE_XRDY_IE  (1 << 4)        /* Transmit data ready interrupt enable */
  55 #define I2C_IE_RRDY_IE  (1 << 3)        /* Receive data ready interrupt enable */
  56 #define I2C_IE_ARDY_IE  (1 << 2)        /* Register access ready interrupt enable */
  57 #define I2C_IE_NACK_IE  (1 << 1)        /* No acknowledgment interrupt enable */
  58 #define I2C_IE_AL_IE    (1 << 0)        /* Arbitration lost interrupt enable */
  59
  60 /* I2C Status Register (I2C_STAT): */
  61
  62 #define I2C_STAT_BB     (1 << 12)       /* Bus busy */
  63 #define I2C_STAT_ROVR   (1 << 11)       /* Receive overrun */
  64 #define I2C_STAT_XUDF   (1 << 10)       /* Transmit underflow */
  65 #define I2C_STAT_AAS    (1 << 9)        /* Address as slave */
  66 #define I2C_STAT_SCD    (1 << 5)        /* Stop condition detect */
  67 #define I2C_STAT_XRDY   (1 << 4)        /* Transmit data ready */
  68 #define I2C_STAT_RRDY   (1 << 3)        /* Receive data ready */
  69 #define I2C_STAT_ARDY   (1 << 2)        /* Register access ready */
  70 #define I2C_STAT_NACK   (1 << 1)        /* No acknowledgment interrupt enable */
  71 #define I2C_STAT_AL     (1 << 0)        /* Arbitration lost interrupt enable */
  72
  73
  74 /* I2C Interrupt Code Register (I2C_INTCODE): */
  75
  76 #define I2C_INTCODE_MASK        7
  77 #define I2C_INTCODE_NONE        0
  78 #define I2C_INTCODE_AL          1       /* Arbitration lost */
  79 #define I2C_INTCODE_NAK         2       /* No acknowledgement/general call */
  80 #define I2C_INTCODE_ARDY        3       /* Register access ready */
  81 #define I2C_INTCODE_RRDY        4       /* Rcv data ready */
  82 #define I2C_INTCODE_XRDY        5       /* Xmit data ready */
  83 #define I2C_INTCODE_SCD         6       /* Stop condition detect */
  84
  85
  86 /* I2C Configuration Register (I2C_CON): */
  87
  88 #define I2C_CON_EN      (1 << 5)        /* I2C module enable */
  89 #define I2C_CON_STB     (1 << 4)        /* Start byte mode (master mode only) */
  90 #define I2C_CON_MST     (1 << 10)       /* Master/slave mode */
  91 #define I2C_CON_TRX     (1 << 9)        /* Transmitter/receiver mode (master mode only) */
  92 #define I2C_CON_XA      (1 << 8)        /* Expand address */
  93 #define I2C_CON_STP     (1 << 11)       /* Stop condition (master mode only) */
  94 #define I2C_CON_STT     (1 << 13)       /* Start condition (master mode only) */
  95 #define I2C_CON_FREE    (1 << 14)       /* Free run on emulation */
  96
  97 #define I2C_TIMEOUT     0xffff0000      /* Timeout mask for poll_i2c_irq() */
  98
  99 #endif