arch/arm/include/asm/arch-ep93xx/ep93xx.h

   1 /*
   2  * Cirrus Logic EP93xx register definitions.
   3  *
   4  * Copyright (C) 2009
   5  * Matthias Kaehlcke <matthias@kaehlcke.net>
   6  *
   7  * Copyright (C) 2006
   8  * Dominic Rath <Dominic.Rath@gmx.de>
   9  *
  10  * Copyright (C) 2004, 2005
  11  * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
  12  *
  13  * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
  14  *
  15  * Copyright (C) 2004 Ray Lehtiniemi
  16  * Copyright (C) 2003 Cirrus Logic, Inc
  17  * Copyright (C) 1999 ARM Limited.
  18  *
  19  * SPDX-License-Identifier:     GPL-2.0+
  20  */
  21
  22 #define EP93XX_AHB_BASE                 0x80000000
  23 #define EP93XX_APB_BASE                 0x80800000
  24
  25 /*
  26  * 0x80000000 - 0x8000FFFF: DMA
  27  */
  28 #define DMA_OFFSET                      0x000000
  29 #define DMA_BASE                        (EP93XX_AHB_BASE | DMA_OFFSET)
  30
  31 #ifndef __ASSEMBLY__
  32 struct dma_channel {
  33         uint32_t control;
  34         uint32_t interrupt;
  35         uint32_t ppalloc;
  36         uint32_t status;
  37         uint32_t reserved0;
  38         uint32_t remain;
  39         uint32_t reserved1[2];
  40         uint32_t maxcnt0;
  41         uint32_t base0;
  42         uint32_t current0;
  43         uint32_t reserved2;
  44         uint32_t maxcnt1;
  45         uint32_t base1;
  46         uint32_t current1;
  47         uint32_t reserved3;
  48 };
  49
  50 struct dma_regs {
  51         struct dma_channel m2p_channel_0;
  52         struct dma_channel m2p_channel_1;
  53         struct dma_channel m2p_channel_2;
  54         struct dma_channel m2p_channel_3;
  55         struct dma_channel m2m_channel_0;
  56         struct dma_channel m2m_channel_1;
  57         struct dma_channel reserved0[2];
  58         struct dma_channel m2p_channel_5;
  59         struct dma_channel m2p_channel_4;
  60         struct dma_channel m2p_channel_7;
  61         struct dma_channel m2p_channel_6;
  62         struct dma_channel m2p_channel_9;
  63         struct dma_channel m2p_channel_8;
  64         uint32_t channel_arbitration;
  65         uint32_t reserved[15];
  66         uint32_t global_interrupt;
  67 };
  68 #endif
  69
  70 /*
  71  * 0x80010000 - 0x8001FFFF: Ethernet MAC
  72  */
  73 #define MAC_OFFSET                      0x010000
  74 #define MAC_BASE                        (EP93XX_AHB_BASE | MAC_OFFSET)
  75
  76 #ifndef __ASSEMBLY__
  77 struct mac_queue {
  78         uint32_t badd;
  79         union { /* deal with half-word aligned registers */
  80                 uint32_t blen;
  81                 union {
  82                         uint16_t filler;
  83                         uint16_t curlen;
  84                 };
  85         };
  86         uint32_t curadd;
  87 };
  88
  89 struct mac_regs {
  90         uint32_t rxctl;
  91         uint32_t txctl;
  92         uint32_t testctl;
  93         uint32_t reserved0;
  94         uint32_t miicmd;
  95         uint32_t miidata;
  96         uint32_t miists;
  97         uint32_t reserved1;
  98         uint32_t selfctl;
  99         uint32_t inten;
 100         uint32_t intstsp;
 101         uint32_t intstsc;
 102         uint32_t reserved2[2];
 103         uint32_t diagad;
 104         uint32_t diagdata;
 105         uint32_t gt;
 106         uint32_t fct;
 107         uint32_t fcf;
 108         uint32_t afp;
 109         union {
 110                 struct {
 111                         uint32_t indad;
 112                         uint32_t indad_upper;
 113                 };
 114                 uint32_t hashtbl;
 115         };
 116         uint32_t reserved3[2];
 117         uint32_t giintsts;
 118         uint32_t giintmsk;
 119         uint32_t giintrosts;
 120         uint32_t giintfrc;
 121         uint32_t txcollcnt;
 122         uint32_t rxmissnct;
 123         uint32_t rxruntcnt;
 124         uint32_t reserved4;
 125         uint32_t bmctl;
 126         uint32_t bmsts;
 127         uint32_t rxbca;
 128         uint32_t reserved5;
 129         struct mac_queue rxdq;
 130         uint32_t rxdqenq;
 131         struct mac_queue rxstsq;
 132         uint32_t rxstsqenq;
 133         struct mac_queue txdq;
 134         uint32_t txdqenq;
 135         struct mac_queue txstsq;
 136         uint32_t reserved6;
 137         uint32_t rxbufthrshld;
 138         uint32_t txbufthrshld;
 139         uint32_t rxststhrshld;
 140         uint32_t txststhrshld;
 141         uint32_t rxdthrshld;
 142         uint32_t txdthrshld;
 143         uint32_t maxfrmlen;
 144         uint32_t maxhdrlen;
 145 };
 146 #endif
 147
 148 #define SELFCTL_RWP             (1 << 7)
 149 #define SELFCTL_GPO0            (1 << 5)
 150 #define SELFCTL_PUWE            (1 << 4)
 151 #define SELFCTL_PDWE            (1 << 3)
 152 #define SELFCTL_MIIL            (1 << 2)
 153 #define SELFCTL_RESET           (1 << 0)
 154
 155 #define INTSTS_RWI              (1 << 30)
 156 #define INTSTS_RXMI             (1 << 29)
 157 #define INTSTS_RXBI             (1 << 28)
 158 #define INTSTS_RXSQI            (1 << 27)
 159 #define INTSTS_TXLEI            (1 << 26)
 160 #define INTSTS_ECIE             (1 << 25)
 161 #define INTSTS_TXUHI            (1 << 24)
 162 #define INTSTS_MOI              (1 << 18)
 163 #define INTSTS_TXCOI            (1 << 17)
 164 #define INTSTS_RXROI            (1 << 16)
 165 #define INTSTS_MIII             (1 << 12)
 166 #define INTSTS_PHYI             (1 << 11)
 167 #define INTSTS_TI               (1 << 10)
 168 #define INTSTS_AHBE             (1 << 8)
 169 #define INTSTS_OTHER            (1 << 4)
 170 #define INTSTS_TXSQ             (1 << 3)
 171 #define INTSTS_RXSQ             (1 << 2)
 172
 173 #define BMCTL_MT                (1 << 13)
 174 #define BMCTL_TT                (1 << 12)
 175 #define BMCTL_UNH               (1 << 11)
 176 #define BMCTL_TXCHR             (1 << 10)
 177 #define BMCTL_TXDIS             (1 << 9)
 178 #define BMCTL_TXEN              (1 << 8)
 179 #define BMCTL_EH2               (1 << 6)
 180 #define BMCTL_EH1               (1 << 5)
 181 #define BMCTL_EEOB              (1 << 4)
 182 #define BMCTL_RXCHR             (1 << 2)
 183 #define BMCTL_RXDIS             (1 << 1)
 184 #define BMCTL_RXEN              (1 << 0)
 185
 186 #define BMSTS_TXACT             (1 << 7)
 187 #define BMSTS_TP                (1 << 4)
 188 #define BMSTS_RXACT             (1 << 3)
 189 #define BMSTS_QID_MASK          0x07
 190 #define BMSTS_QID_RXDATA        0x00
 191 #define BMSTS_QID_TXDATA        0x01
 192 #define BMSTS_QID_RXSTS         0x02
 193 #define BMSTS_QID_TXSTS         0x03
 194 #define BMSTS_QID_RXDESC        0x04
 195 #define BMSTS_QID_TXDESC        0x05
 196
 197 #define AFP_MASK                0x07
 198 #define AFP_IAPRIMARY           0x00
 199 #define AFP_IASECONDARY1        0x01
 200 #define AFP_IASECONDARY2        0x02
 201 #define AFP_IASECONDARY3        0x03
 202 #define AFP_TX                  0x06
 203 #define AFP_HASH                0x07
 204
 205 #define RXCTL_PAUSEA            (1 << 20)
 206 #define RXCTL_RXFCE1            (1 << 19)
 207 #define RXCTL_RXFCE0            (1 << 18)
 208 #define RXCTL_BCRC              (1 << 17)
 209 #define RXCTL_SRXON             (1 << 16)
 210 #define RXCTL_RCRCA             (1 << 13)
 211 #define RXCTL_RA                (1 << 12)
 212 #define RXCTL_PA                (1 << 11)
 213 #define RXCTL_BA                (1 << 10)
 214 #define RXCTL_MA                (1 << 9)
 215 #define RXCTL_IAHA              (1 << 8)
 216 #define RXCTL_IA3               (1 << 3)
 217 #define RXCTL_IA2               (1 << 2)
 218 #define RXCTL_IA1               (1 << 1)
 219 #define RXCTL_IA0               (1 << 0)
 220
 221 #define TXCTL_DEFDIS            (1 << 7)
 222 #define TXCTL_MBE               (1 << 6)
 223 #define TXCTL_ICRC              (1 << 5)
 224 #define TXCTL_TPD               (1 << 4)
 225 #define TXCTL_OCOLL             (1 << 3)
 226 #define TXCTL_SP                (1 << 2)
 227 #define TXCTL_PB                (1 << 1)
 228 #define TXCTL_STXON             (1 << 0)
 229
 230 #define MIICMD_REGAD_MASK       (0x001F)
 231 #define MIICMD_PHYAD_MASK       (0x03E0)
 232 #define MIICMD_OPCODE_MASK      (0xC000)
 233 #define MIICMD_PHYAD_8950       (0x0000)
 234 #define MIICMD_OPCODE_READ      (0x8000)
 235 #define MIICMD_OPCODE_WRITE     (0x4000)
 236
 237 #define MIISTS_BUSY             (1 << 0)
 238
 239 /*
 240  * 0x80020000 - 0x8002FFFF: USB OHCI
 241  */
 242 #define USB_OFFSET                      0x020000
 243 #define USB_BASE                        (EP93XX_AHB_BASE | USB_OFFSET)
 244
 245 /*
 246  * 0x80030000 - 0x8003FFFF: Raster engine
 247  */
 248 #if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
 249 #define RASTER_OFFSET                   0x030000
 250 #define RASTER_BASE                     (EP93XX_AHB_BASE | RASTER_OFFSET)
 251 #endif
 252
 253 /*
 254  * 0x80040000 - 0x8004FFFF: Graphics accelerator
 255  */
 256 #if defined(CONFIG_EP9315)
 257 #define GFX_OFFSET                      0x040000
 258 #define GFX_BASE                        (EP93XX_AHB_BASE | GFX_OFFSET)
 259 #endif
 260
 261 /*
 262  * 0x80050000 - 0x8005FFFF: Reserved
 263  */
 264
 265 /*
 266  * 0x80060000 - 0x8006FFFF: SDRAM controller
 267  */
 268 #define SDRAM_OFFSET                    0x060000
 269 #define SDRAM_BASE                      (EP93XX_AHB_BASE | SDRAM_OFFSET)
 270
 271 #ifndef __ASSEMBLY__
 272 struct sdram_regs {
 273         uint32_t reserved;
 274         uint32_t glconfig;
 275         uint32_t refrshtimr;
 276         uint32_t bootsts;
 277         uint32_t devcfg0;
 278         uint32_t devcfg1;
 279         uint32_t devcfg2;
 280         uint32_t devcfg3;
 281 };
 282 #endif
 283
 284 #define SDRAM_DEVCFG_EXTBUSWIDTH        (1 << 2)
 285 #define SDRAM_DEVCFG_BANKCOUNT          (1 << 3)
 286 #define SDRAM_DEVCFG_SROMLL             (1 << 5)
 287 #define SDRAM_DEVCFG_CASLAT_2           0x00010000
 288 #define SDRAM_DEVCFG_RASTOCAS_2         0x00200000
 289
 290 #define GLCONFIG_INIT                   (1 << 0)
 291 #define GLCONFIG_MRS                    (1 << 1)
 292 #define GLCONFIG_SMEMBUSY               (1 << 5)
 293 #define GLCONFIG_LCR                    (1 << 6)
 294 #define GLCONFIG_REARBEN                (1 << 7)
 295 #define GLCONFIG_CLKSHUTDOWN            (1 << 30)
 296 #define GLCONFIG_CKE                    (1 << 31)
 297
 298 /*
 299  * 0x80070000 - 0x8007FFFF: Reserved
 300  */
 301
 302 /*
 303  * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
 304  */
 305 #define SMC_OFFSET                      0x080000
 306 #define SMC_BASE                        (EP93XX_AHB_BASE | SMC_OFFSET)
 307
 308 #ifndef __ASSEMBLY__
 309 struct smc_regs {
 310         uint32_t bcr0;
 311         uint32_t bcr1;
 312         uint32_t bcr2;
 313         uint32_t bcr3;
 314         uint32_t reserved0[2];
 315         uint32_t bcr6;
 316         uint32_t bcr7;
 317 #if defined(CONFIG_EP9315)
 318         uint32_t pcattribute;
 319         uint32_t pccommon;
 320         uint32_t pcio;
 321         uint32_t reserved1[5];
 322         uint32_t pcmciactrl;
 323 #endif
 324 };
 325 #endif
 326
 327 #define SMC_BCR_IDCY_SHIFT      0
 328 #define SMC_BCR_WST1_SHIFT      5
 329 #define SMC_BCR_BLE             (1 << 10)
 330 #define SMC_BCR_WST2_SHIFT      11
 331 #define SMC_BCR_MW_SHIFT        28
 332
 333 /*
 334  * 0x80090000 - 0x8009FFFF: Boot ROM
 335  */
 336
 337 /*
 338  * 0x800A0000 - 0x800AFFFF: IDE interface
 339  */
 340
 341 /*
 342  * 0x800B0000 - 0x800BFFFF: VIC1
 343  */
 344
 345 /*
 346  * 0x800C0000 - 0x800CFFFF: VIC2
 347  */
 348
 349 /*
 350  * 0x800D0000 - 0x800FFFFF: Reserved
 351  */
 352
 353 /*
 354  * 0x80800000 - 0x8080FFFF: Reserved
 355  */
 356
 357 /*
 358  * 0x80810000 - 0x8081FFFF: Timers
 359  */
 360 #define TIMER_OFFSET            0x010000
 361 #define TIMER_BASE              (EP93XX_APB_BASE | TIMER_OFFSET)
 362
 363 #ifndef __ASSEMBLY__
 364 struct timer {
 365         uint32_t load;
 366         uint32_t value;
 367         uint32_t control;
 368         uint32_t clear;
 369 };
 370
 371 struct timer4 {
 372         uint32_t value_low;
 373         uint32_t value_high;
 374 };
 375
 376 struct timer_regs {
 377         struct timer timer1;
 378         uint32_t reserved0[4];
 379         struct timer timer2;
 380         uint32_t reserved1[12];
 381         struct timer4 timer4;
 382         uint32_t reserved2[6];
 383         struct timer timer3;
 384 };
 385 #endif
 386
 387 /*
 388  * 0x80820000 - 0x8082FFFF: I2S
 389  */
 390 #define I2S_OFFSET              0x020000
 391 #define I2S_BASE                (EP93XX_APB_BASE | I2S_OFFSET)
 392
 393 /*
 394  * 0x80830000 - 0x8083FFFF: Security
 395  */
 396 #define SECURITY_OFFSET         0x030000
 397 #define SECURITY_BASE           (EP93XX_APB_BASE | SECURITY_OFFSET)
 398
 399 #define EXTENSIONID             (SECURITY_BASE + 0x2714)
 400
 401 /*
 402  * 0x80840000 - 0x8084FFFF: GPIO
 403  */
 404 #define GPIO_OFFSET             0x040000
 405 #define GPIO_BASE               (EP93XX_APB_BASE | GPIO_OFFSET)
 406
 407 #ifndef __ASSEMBLY__
 408 struct gpio_int {
 409         uint32_t inttype1;
 410         uint32_t inttype2;
 411         uint32_t eoi;
 412         uint32_t inten;
 413         uint32_t intsts;
 414         uint32_t rawintsts;
 415         uint32_t db;
 416 };
 417
 418 struct gpio_regs {
 419         uint32_t padr;
 420         uint32_t pbdr;
 421         uint32_t pcdr;
 422         uint32_t pddr;
 423         uint32_t paddr;
 424         uint32_t pbddr;
 425         uint32_t pcddr;
 426         uint32_t pdddr;
 427         uint32_t pedr;
 428         uint32_t peddr;
 429         uint32_t reserved0[2];
 430         uint32_t pfdr;
 431         uint32_t pfddr;
 432         uint32_t pgdr;
 433         uint32_t pgddr;
 434         uint32_t phdr;
 435         uint32_t phddr;
 436         uint32_t reserved1;
 437         uint32_t finttype1;
 438         uint32_t finttype2;
 439         uint32_t reserved2;
 440         struct gpio_int pfint;
 441         uint32_t reserved3[10];
 442         struct gpio_int paint;
 443         struct gpio_int pbint;
 444         uint32_t eedrive;
 445 };
 446 #endif
 447
 448 /*
 449  * 0x80850000 - 0x8087FFFF: Reserved
 450  */
 451
 452 /*
 453  * 0x80880000 - 0x8088FFFF: AAC
 454  */
 455 #define AAC_OFFSET              0x080000
 456 #define AAC_BASE                (EP93XX_APB_BASE | AAC_OFFSET)
 457
 458 /*
 459  * 0x80890000 - 0x8089FFFF: Reserved
 460  */
 461
 462 /*
 463  * 0x808A0000 - 0x808AFFFF: SPI
 464  */
 465 #define SPI_OFFSET              0x0A0000
 466 #define SPI_BASE                (EP93XX_APB_BASE | SPI_OFFSET)
 467
 468 /*
 469  * 0x808B0000 - 0x808BFFFF: IrDA
 470  */
 471 #define IRDA_OFFSET             0x0B0000
 472 #define IRDA_BASE               (EP93XX_APB_BASE | IRDA_OFFSET)
 473
 474 /*
 475  * 0x808C0000 - 0x808CFFFF: UART1
 476  */
 477 #define UART1_OFFSET            0x0C0000
 478 #define UART1_BASE              (EP93XX_APB_BASE | UART1_OFFSET)
 479
 480 /*
 481  * 0x808D0000 - 0x808DFFFF: UART2
 482  */
 483 #define UART2_OFFSET            0x0D0000
 484 #define UART2_BASE              (EP93XX_APB_BASE | UART2_OFFSET)
 485
 486 /*
 487  * 0x808E0000 - 0x808EFFFF: UART3
 488  */
 489 #define UART3_OFFSET            0x0E0000
 490 #define UART3_BASE              (EP93XX_APB_BASE | UART3_OFFSET)
 491
 492 /*
 493  * 0x808F0000 - 0x808FFFFF: Key Matrix
 494  */
 495 #define KEY_OFFSET              0x0F0000
 496 #define KEY_BASE                (EP93XX_APB_BASE | KEY_OFFSET)
 497
 498 /*
 499  * 0x80900000 - 0x8090FFFF: Touchscreen
 500  */
 501 #define TOUCH_OFFSET            0x900000
 502 #define TOUCH_BASE              (EP93XX_APB_BASE | TOUCH_OFFSET)
 503
 504 /*
 505  * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
 506  */
 507 #define PWM_OFFSET              0x910000
 508 #define PWM_BASE                (EP93XX_APB_BASE | PWM_OFFSET)
 509
 510 /*
 511  * 0x80920000 - 0x8092FFFF: Real time clock
 512  */
 513 #define RTC_OFFSET              0x920000
 514 #define RTC_BASE                (EP93XX_APB_BASE | RTC_OFFSET)
 515
 516 /*
 517  * 0x80930000 - 0x8093FFFF: Syscon
 518  */
 519 #define SYSCON_OFFSET           0x930000
 520 #define SYSCON_BASE             (EP93XX_APB_BASE | SYSCON_OFFSET)
 521
 522 #ifndef __ASSEMBLY__
 523 struct syscon_regs {
 524         uint32_t pwrsts;
 525         uint32_t pwrcnt;
 526         uint32_t halt;
 527         uint32_t stby;
 528         uint32_t reserved0[2];
 529         uint32_t teoi;
 530         uint32_t stfclr;
 531         uint32_t clkset1;
 532         uint32_t clkset2;
 533         uint32_t reserved1[6];
 534         uint32_t scratch0;
 535         uint32_t scratch1;
 536         uint32_t reserved2[2];
 537         uint32_t apbwait;
 538         uint32_t bustmstrarb;
 539         uint32_t bootmodeclr;
 540         uint32_t reserved3[9];
 541         uint32_t devicecfg;
 542         uint32_t vidclkdiv;
 543         uint32_t mirclkdiv;
 544         uint32_t i2sclkdiv;
 545         uint32_t keytchclkdiv;
 546         uint32_t chipid;
 547         uint32_t reserved4;
 548         uint32_t syscfg;
 549         uint32_t reserved5[8];
 550         uint32_t sysswlock;
 551 };
 552 #else
 553 #define SYSCON_SCRATCH0         (SYSCON_BASE + 0x0040)
 554 #endif
 555
 556 #define SYSCON_PWRCNT_UART_BAUD                 (1 << 29)
 557
 558 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT           0
 559 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT          5
 560 #define SYSCON_CLKSET_PLL_X1FBD1_SHIFT          11
 561 #define SYSCON_CLKSET_PLL_PS_SHIFT              16
 562 #define SYSCON_CLKSET1_PCLK_DIV_SHIFT           18
 563 #define SYSCON_CLKSET1_HCLK_DIV_SHIFT           20
 564 #define SYSCON_CLKSET1_NBYP1                    (1 << 23)
 565 #define SYSCON_CLKSET1_FCLK_DIV_SHIFT           25
 566
 567 #define SYSCON_CLKSET2_PLL2_EN                  (1 << 18)
 568 #define SYSCON_CLKSET2_NBYP2                    (1 << 19)
 569 #define SYSCON_CLKSET2_USB_DIV_SHIFT            28
 570
 571 #define SYSCON_CHIPID_REV_MASK                  0xF0000000
 572 #define SYSCON_DEVICECFG_SWRST                  (1 << 31)
 573
 574 /*
 575  * 0x80930000 - 0x8093FFFF: Watchdog Timer
 576  */
 577 #define WATCHDOG_OFFSET         0x940000
 578 #define WATCHDOG_BASE           (EP93XX_APB_BASE | WATCHDOG_OFFSET)
 579
 580 /*
 581  * 0x80950000 - 0x9000FFFF: Reserved
 582  */