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[people/ms/u-boot.git] / arch / arm / include / asm / arch-exynos / dp.h
1 /*
2 * Copyright (C) 2012 Samsung Electronics
3 *
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 #ifndef __ASM_ARM_ARCH_DP_H_
23 #define __ASM_ARM_ARCH_DP_H_
24
25 #ifndef __ASSEMBLY__
26
27 struct exynos_dp {
28 unsigned char res1[0x10];
29 unsigned int tx_version;
30 unsigned int tx_sw_reset;
31 unsigned int func_en1;
32 unsigned int func_en2;
33 unsigned int video_ctl1;
34 unsigned int video_ctl2;
35 unsigned int video_ctl3;
36 unsigned int video_ctl4;
37 unsigned int color_blue_cb;
38 unsigned int color_green_y;
39 unsigned int color_red_cr;
40 unsigned int video_ctl8;
41 unsigned char res2[0x4];
42 unsigned int video_ctl10;
43 unsigned int total_ln_cfg_l;
44 unsigned int total_ln_cfg_h;
45 unsigned int active_ln_cfg_l;
46 unsigned int active_ln_cfg_h;
47 unsigned int vfp_cfg;
48 unsigned int vsw_cfg;
49 unsigned int vbp_cfg;
50 unsigned int total_pix_cfg_l;
51 unsigned int total_pix_cfg_h;
52 unsigned int active_pix_cfg_l;
53 unsigned int active_pix_cfg_h;
54 unsigned int hfp_cfg_l;
55 unsigned int hfp_cfg_h;
56 unsigned int hsw_cfg_l;
57 unsigned int hsw_cfg_h;
58 unsigned int hbp_cfg_l;
59 unsigned int hbp_cfg_h;
60 unsigned int video_status;
61 unsigned int total_ln_sta_l;
62 unsigned int total_ln_sta_h;
63 unsigned int active_ln_sta_l;
64 unsigned int active_ln_sta_h;
65
66 unsigned int vfp_sta;
67 unsigned int vsw_sta;
68 unsigned int vbp_sta;
69
70 unsigned int total_pix_sta_l;
71 unsigned int total_pix_sta_h;
72 unsigned int active_pix_sta_l;
73 unsigned int active_pix_sta_h;
74
75 unsigned int hfp_sta_l;
76 unsigned int hfp_sta_h;
77 unsigned int hsw_sta_l;
78 unsigned int hsw_sta_h;
79 unsigned int hbp_sta_l;
80 unsigned int hbp_sta_h;
81
82 unsigned char res3[0x288];
83
84 unsigned int lane_map;
85 unsigned char res4[0x10];
86 unsigned int analog_ctl1;
87 unsigned int analog_ctl2;
88 unsigned int analog_ctl3;
89
90 unsigned int pll_filter_ctl1;
91 unsigned int amp_tuning_ctl;
92 unsigned char res5[0xc];
93
94 unsigned int aux_hw_retry_ctl;
95 unsigned char res6[0x2c];
96 unsigned int int_state;
97 unsigned int common_int_sta1;
98 unsigned int common_int_sta2;
99 unsigned int common_int_sta3;
100 unsigned int common_int_sta4;
101 unsigned char res7[0x8];
102
103 unsigned int int_sta;
104 unsigned char res8[0x1c];
105 unsigned int int_ctl;
106 unsigned char res9[0x200];
107 unsigned int sys_ctl1;
108 unsigned int sys_ctl2;
109 unsigned int sys_ctl3;
110 unsigned int sys_ctl4;
111 unsigned int vid_ctl;
112 unsigned char res10[0x2c];
113 unsigned int pkt_send_ctl;
114 unsigned char res[0x4];
115 unsigned int hdcp_ctl;
116 unsigned char res11[0x34];
117 unsigned int link_bw_set;
118
119 unsigned int lane_count_set;
120 unsigned int training_ptn_set;
121 unsigned int ln0_link_training_ctl;
122 unsigned int ln1_link_training_ctl;
123 unsigned int ln2_link_training_ctl;
124 unsigned int ln3_link_training_ctl;
125 unsigned int dn_spread_ctl;
126 unsigned int hw_link_training_ctl;
127 unsigned char res12[0x1c];
128
129 unsigned int debug_ctl;
130 unsigned int hpd_deglitch_l;
131 unsigned int hpd_deglitch_h;
132
133 unsigned char res13[0x14];
134 unsigned int link_debug_ctl;
135
136 unsigned char res14[0x1c];
137
138 unsigned int m_vid0;
139 unsigned int m_vid1;
140 unsigned int m_vid2;
141 unsigned int n_vid0;
142 unsigned int n_vid1;
143 unsigned int n_vid2;
144 unsigned int m_vid_mon;
145 unsigned int pll_ctl;
146 unsigned int phy_pd;
147 unsigned int phy_test;
148 unsigned char res15[0x8];
149
150 unsigned int video_fifo_thrd;
151 unsigned char res16[0x8];
152 unsigned int audio_margin;
153
154 unsigned int dn_spread_ctl1;
155 unsigned int dn_spread_ctl2;
156 unsigned char res17[0x18];
157 unsigned int m_cal_ctl;
158 unsigned int m_vid_gen_filter_th;
159 unsigned char res18[0x10];
160 unsigned int m_aud_gen_filter_th;
161 unsigned char res50[0x4];
162
163 unsigned int aux_ch_sta;
164 unsigned int aux_err_num;
165 unsigned int aux_ch_defer_ctl;
166 unsigned int aux_rx_comm;
167 unsigned int buffer_data_ctl;
168
169 unsigned int aux_ch_ctl1;
170 unsigned int aux_addr_7_0;
171 unsigned int aux_addr_15_8;
172 unsigned int aux_addr_19_16;
173 unsigned int aux_ch_ctl2;
174 unsigned char res19[0x18];
175 unsigned int buf_data0;
176 unsigned char res20[0x3c];
177
178 unsigned int soc_general_ctl;
179 unsigned char res21[0x8c];
180 unsigned int crc_con;
181 unsigned int crc_result;
182 unsigned char res22[0x8];
183
184 unsigned int common_int_mask1;
185 unsigned int common_int_mask2;
186 unsigned int common_int_mask3;
187 unsigned int common_int_mask4;
188 unsigned int int_sta_mask1;
189 unsigned int int_sta_mask2;
190 unsigned int int_sta_mask3;
191 unsigned int int_sta_mask4;
192 unsigned int int_sta_mask;
193 unsigned int crc_result2;
194 unsigned int scrambler_reset_cnt;
195
196 unsigned int pn_inv;
197 unsigned int psr_config;
198 unsigned int psr_command0;
199 unsigned int psr_command1;
200 unsigned int psr_crc_mon0;
201 unsigned int psr_crc_mon1;
202
203 unsigned char res24[0x30];
204 unsigned int phy_bist_ctrl;
205 unsigned char res25[0xc];
206 unsigned int phy_ctrl;
207 unsigned char res26[0x1c];
208 unsigned int test_pattern_gen_en;
209 unsigned int test_pattern_gen_ctrl;
210 };
211
212 #endif /* __ASSEMBLY__ */
213
214 /* For DP VIDEO CTL 1 */
215 #define VIDEO_EN_MASK (0x01 << 7)
216 #define VIDEO_MUTE_MASK (0x01 << 6)
217
218 /* For DP VIDEO CTL 4 */
219 #define VIDEO_BIST_MASK (0x1 << 3)
220
221 /* EXYNOS_DP_ANALOG_CTL_1 */
222 #define SEL_BG_NEW_BANDGAP (0x0 << 6)
223 #define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
224 #define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
225 #define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
226 #define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
227 #define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
228 #define SWING_A_30PER_G_INCREASE (0x1 << 3)
229 #define SWING_A_30PER_G_NORMAL (0x0 << 3)
230
231 /* EXYNOS_DP_ANALOG_CTL_2 */
232 #define CPREG_BLEED (0x1 << 4)
233 #define SEL_24M (0x1 << 3)
234 #define TX_DVDD_BIT_1_0000V (0x3 << 0)
235 #define TX_DVDD_BIT_1_0625V (0x4 << 0)
236 #define TX_DVDD_BIT_1_1250V (0x5 << 0)
237
238 /* EXYNOS_DP_ANALOG_CTL_3 */
239 #define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
240 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
241 #define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
242 #define SEL_CURRENT_DEFAULT (0x0 << 3)
243 #define VCO_BIT_000_MICRO (0x0 << 0)
244 #define VCO_BIT_200_MICRO (0x1 << 0)
245 #define VCO_BIT_300_MICRO (0x2 << 0)
246 #define VCO_BIT_400_MICRO (0x3 << 0)
247 #define VCO_BIT_500_MICRO (0x4 << 0)
248 #define VCO_BIT_600_MICRO (0x5 << 0)
249 #define VCO_BIT_700_MICRO (0x6 << 0)
250 #define VCO_BIT_900_MICRO (0x7 << 0)
251
252 /* EXYNOS_DP_PLL_FILTER_CTL_1 */
253 #define PD_RING_OSC (0x1 << 6)
254 #define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
255 #define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
256 #define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
257 #define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
258 #define TX_CUR1_1X (0x0 << 2)
259 #define TX_CUR1_2X (0x1 << 2)
260 #define TX_CUR1_3X (0x2 << 2)
261 #define TX_CUR_1_MA (0x0 << 0)
262 #define TX_CUR_2_MA (0x1 << 0)
263 #define TX_CUR_3_MA (0x2 << 0)
264 #define TX_CUR_4_MA (0x3 << 0)
265
266 /* EXYNOS_DP_PLL_FILTER_CTL_2 */
267 #define CH3_AMP_0_MV (0x3 << 12)
268 #define CH2_AMP_0_MV (0x3 << 8)
269 #define CH1_AMP_0_MV (0x3 << 4)
270 #define CH0_AMP_0_MV (0x3 << 0)
271
272 /* EXYNOS_DP_PLL_CTL */
273 #define DP_PLL_PD (0x1 << 7)
274 #define DP_PLL_RESET (0x1 << 6)
275 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
276 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
277 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
278
279 /* EXYNOS_DP_INT_CTL */
280 #define SOFT_INT_CTRL (0x1 << 2)
281 #define INT_POL (0x1 << 0)
282
283 /* DP TX SW RESET */
284 #define RESET_DP_TX (0x01 << 0)
285
286 /* DP FUNC_EN_1 */
287 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
288 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
289 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
290 #define AUD_FUNC_EN_N (0x1 << 3)
291 #define HDCP_FUNC_EN_N (0x1 << 2)
292 #define CRC_FUNC_EN_N (0x1 << 1)
293 #define SW_FUNC_EN_N (0x1 << 0)
294
295 /* DP FUNC_EN_2 */
296 #define SSC_FUNC_EN_N (0x1 << 7)
297 #define AUX_FUNC_EN_N (0x1 << 2)
298 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
299 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
300
301 /* EXYNOS_DP_PHY_PD */
302 #define PHY_PD (0x1 << 5)
303 #define AUX_PD (0x1 << 4)
304 #define CH3_PD (0x1 << 3)
305 #define CH2_PD (0x1 << 2)
306 #define CH1_PD (0x1 << 1)
307 #define CH0_PD (0x1 << 0)
308
309 /* EXYNOS_DP_COMMON_INT_STA_1 */
310 #define VSYNC_DET (0x1 << 7)
311 #define PLL_LOCK_CHG (0x1 << 6)
312 #define SPDIF_ERR (0x1 << 5)
313 #define SPDIF_UNSTBL (0x1 << 4)
314 #define VID_FORMAT_CHG (0x1 << 3)
315 #define AUD_CLK_CHG (0x1 << 2)
316 #define VID_CLK_CHG (0x1 << 1)
317 #define SW_INT (0x1 << 0)
318
319 /* EXYNOS_DP_DEBUG_CTL */
320 #define PLL_LOCK (0x1 << 4)
321 #define F_PLL_LOCK (0x1 << 3)
322 #define PLL_LOCK_CTRL (0x1 << 2)
323
324 /* EXYNOS_DP_FUNC_EN_2 */
325 #define SSC_FUNC_EN_N (0x1 << 7)
326 #define AUX_FUNC_EN_N (0x1 << 2)
327 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
328 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
329
330 /* EXYNOS_DP_COMMON_INT_STA_4 */
331 #define PSR_ACTIVE (0x1 << 7)
332 #define PSR_INACTIVE (0x1 << 6)
333 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
334 #define HOTPLUG_CHG (0x1 << 2)
335 #define HPD_LOST (0x1 << 1)
336 #define PLUG (0x1 << 0)
337
338 /* EXYNOS_DP_INT_STA */
339 #define INT_HPD (0x1 << 6)
340 #define HW_TRAINING_FINISH (0x1 << 5)
341 #define RPLY_RECEIV (0x1 << 1)
342 #define AUX_ERR (0x1 << 0)
343
344 /* EXYNOS_DP_SYS_CTL_3 */
345 #define HPD_STATUS (0x1 << 6)
346 #define F_HPD (0x1 << 5)
347 #define HPD_CTRL (0x1 << 4)
348 #define HDCP_RDY (0x1 << 3)
349 #define STRM_VALID (0x1 << 2)
350 #define F_VALID (0x1 << 1)
351 #define VALID_CTRL (0x1 << 0)
352
353 /* EXYNOS_DP_AUX_HW_RETRY_CTL */
354 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
355 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
356 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
357 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
358 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
359 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
360 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
361
362 /* EXYNOS_DP_AUX_CH_DEFER_CTL */
363 #define DEFER_CTRL_EN (0x1 << 7)
364 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
365
366 #define COMMON_INT_MASK_1 (0)
367 #define COMMON_INT_MASK_2 (0)
368 #define COMMON_INT_MASK_3 (0)
369 #define COMMON_INT_MASK_4 (0)
370 #define INT_STA_MASK (0)
371
372 /* EXYNOS_DP_BUFFER_DATA_CTL */
373 #define BUF_CLR (0x1 << 7)
374 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
375
376 /* EXYNOS_DP_AUX_ADDR_7_0 */
377 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
378
379 /* EXYNOS_DP_AUX_ADDR_15_8 */
380 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
381
382 /* EXYNOS_DP_AUX_ADDR_19_16 */
383 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
384
385 /* EXYNOS_DP_AUX_CH_CTL_1 */
386 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
387 #define AUX_TX_COMM_MASK (0xf << 0)
388 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
389 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
390 #define AUX_TX_COMM_MOT (0x1 << 2)
391 #define AUX_TX_COMM_WRITE (0x0 << 0)
392 #define AUX_TX_COMM_READ (0x1 << 0)
393
394 /* EXYNOS_DP_AUX_CH_CTL_2 */
395 #define ADDR_ONLY (0x1 << 1)
396 #define AUX_EN (0x1 << 0)
397
398 /* EXYNOS_DP_AUX_CH_STA */
399 #define AUX_BUSY (0x1 << 4)
400 #define AUX_STATUS_MASK (0xf << 0)
401
402 /* EXYNOS_DP_AUX_RX_COMM */
403 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
404 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
405
406 /* EXYNOS_DP_PHY_TEST */
407 #define MACRO_RST (0x1 << 5)
408 #define CH1_TEST (0x1 << 1)
409 #define CH0_TEST (0x1 << 0)
410
411 /* EXYNOS_DP_TRAINING_PTN_SET */
412 #define SCRAMBLER_TYPE (0x1 << 9)
413 #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
414 #define SCRAMBLING_DISABLE (0x1 << 5)
415 #define SCRAMBLING_ENABLE (0x0 << 5)
416 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
417 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
418 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
419 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
420 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
421 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
422 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
423 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
424
425 /* EXYNOS_DP_TOTAL_LINE_CFG */
426 #define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
427 #define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
428 #define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
429 #define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
430 #define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
431 #define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
432 #define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
433 #define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
434
435 #define H_F_PORCH_CFG_L(x) ((x) & 0xff)
436 #define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
437 #define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
438 #define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
439 #define H_B_PORCH_CFG_L(x) ((x) & 0xff)
440 #define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
441
442 /* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
443 #define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
444 #define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
445 #define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
446 #define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
447 #define PRE_EMPHASIS_SET_0_SHIFT (3)
448 #define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
449 #define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
450 #define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
451 #define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
452 #define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
453 #define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
454 #define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
455 #define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
456 #define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
457 #define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
458 #define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
459 #define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
460
461 /* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
462 #define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
463 #define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
464 #define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
465 #define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
466 #define PRE_EMPHASIS_SET_1_SHIFT (3)
467 #define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
468 #define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
469 #define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
470 #define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
471 #define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
472 #define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
473 #define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
474 #define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
475 #define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
476 #define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
477 #define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
478 #define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
479
480 /* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
481 #define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
482 #define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
483 #define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
484 #define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
485 #define PRE_EMPHASIS_SET_2_SHIFT (3)
486 #define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
487 #define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
488 #define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
489 #define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
490 #define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
491 #define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
492 #define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
493 #define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
494 #define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
495 #define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
496 #define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
497 #define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
498
499 /* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
500 #define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
501 #define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
502 #define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
503 #define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
504 #define PRE_EMPHASIS_SET_3_SHIFT (3)
505 #define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
506 #define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
507 #define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
508 #define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
509 #define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
510 #define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
511 #define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
512 #define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
513 #define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
514 #define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
515 #define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
516 #define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
517
518 /* EXYNOS_DP_VIDEO_CTL_10 */
519 #define FORMAT_SEL (0x1 << 4)
520 #define INTERACE_SCAN_CFG (0x1 << 2)
521 #define INTERACE_SCAN_CFG_SHIFT (2)
522 #define VSYNC_POLARITY_CFG (0x1 << 1)
523 #define V_S_POLARITY_CFG_SHIFT (1)
524 #define HSYNC_POLARITY_CFG (0x1 << 0)
525 #define H_S_POLARITY_CFG_SHIFT (0)
526
527 /* EXYNOS_DP_SOC_GENERAL_CTL */
528 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
529 #define AUDIO_MODE_MASTER_MODE (0x0 << 8)
530 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
531 #define VIDEO_MASTER_CLK_SEL (0x1 << 2)
532 #define VIDEO_MASTER_MODE_EN (0x1 << 1)
533 #define VIDEO_MODE_MASK (0x1 << 0)
534 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
535 #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
536
537 /* EXYNOS_DP_VIDEO_CTL_1 */
538 #define VIDEO_EN (0x1 << 7)
539 #define HDCP_VIDEO_MUTE (0x1 << 6)
540
541 /* EXYNOS_DP_VIDEO_CTL_2 */
542 #define IN_D_RANGE_MASK (0x1 << 7)
543 #define IN_D_RANGE_SHIFT (7)
544 #define IN_D_RANGE_CEA (0x1 << 7)
545 #define IN_D_RANGE_VESA (0x0 << 7)
546 #define IN_BPC_MASK (0x7 << 4)
547 #define IN_BPC_SHIFT (4)
548 #define IN_BPC_12_BITS (0x3 << 4)
549 #define IN_BPC_10_BITS (0x2 << 4)
550 #define IN_BPC_8_BITS (0x1 << 4)
551 #define IN_BPC_6_BITS (0x0 << 4)
552 #define IN_COLOR_F_MASK (0x3 << 0)
553 #define IN_COLOR_F_SHIFT (0)
554 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
555 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
556 #define IN_COLOR_F_RGB (0x0 << 0)
557
558 /* EXYNOS_DP_VIDEO_CTL_3 */
559 #define IN_YC_COEFFI_MASK (0x1 << 7)
560 #define IN_YC_COEFFI_SHIFT (7)
561 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
562 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
563 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
564 #define VID_CHK_UPDATE_TYPE_SHIFT (4)
565 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
566 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
567
568 /* EXYNOS_DP_TEST_PATTERN_GEN_EN */
569 #define TEST_PATTERN_GEN_EN (0x1 << 0)
570 #define TEST_PATTERN_GEN_DIS (0x0 << 0)
571
572 /* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
573 #define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
574 #define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
575 #define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
576
577 /* EXYNOS_DP_VIDEO_CTL_4 */
578 #define BIST_EN (0x1 << 3)
579 #define BIST_WIDTH_MASK (0x1 << 2)
580 #define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
581 #define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
582 #define BIST_TYPE_MASK (0x3 << 0)
583 #define BIST_TYPE_COLOR_BAR (0x0 << 0)
584 #define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
585 #define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
586
587 /* EXYNOS_DP_SYS_CTL_1 */
588 #define DET_STA (0x1 << 2)
589 #define FORCE_DET (0x1 << 1)
590 #define DET_CTRL (0x1 << 0)
591
592 /* EXYNOS_DP_SYS_CTL_2 */
593 #define CHA_CRI(x) (((x) & 0xf) << 4)
594 #define CHA_STA (0x1 << 2)
595 #define FORCE_CHA (0x1 << 1)
596 #define CHA_CTRL (0x1 << 0)
597
598 /* EXYNOS_DP_SYS_CTL_3 */
599 #define HPD_STATUS (0x1 << 6)
600 #define F_HPD (0x1 << 5)
601 #define HPD_CTRL (0x1 << 4)
602 #define HDCP_RDY (0x1 << 3)
603 #define STRM_VALID (0x1 << 2)
604 #define F_VALID (0x1 << 1)
605 #define VALID_CTRL (0x1 << 0)
606
607 /* EXYNOS_DP_SYS_CTL_4 */
608 #define FIX_M_AUD (0x1 << 4)
609 #define ENHANCED (0x1 << 3)
610 #define FIX_M_VID (0x1 << 2)
611 #define M_VID_UPDATE_CTRL (0x3 << 0)
612
613 /* EXYNOS_M_VID_X */
614 #define M_VID0_CFG(x) ((x) & 0xff)
615 #define M_VID1_CFG(x) (((x) >> 8) & 0xff)
616 #define M_VID2_CFG(x) (((x) >> 16) & 0xff)
617
618 /* EXYNOS_M_VID_X */
619 #define N_VID0_CFG(x) ((x) & 0xff)
620 #define N_VID1_CFG(x) (((x) >> 8) & 0xff)
621 #define N_VID2_CFG(x) (((x) >> 16) & 0xff)
622
623 /* DPCD_TRAINING_PATTERN_SET */
624 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
625 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
626 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
627 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
628 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
629
630 /* Definition for DPCD Register */
631 #define DPCD_DPCD_REV (0x0000)
632 #define DPCD_MAX_LINK_RATE (0x0001)
633 #define DPCD_MAX_LANE_COUNT (0x0002)
634 #define DPCD_LINK_BW_SET (0x0100)
635 #define DPCD_LANE_COUNT_SET (0x0101)
636 #define DPCD_TRAINING_PATTERN_SET (0x0102)
637 #define DPCD_TRAINING_LANE0_SET (0x0103)
638 #define DPCD_LANE0_1_STATUS (0x0202)
639 #define DPCD_LN_ALIGN_UPDATED (0x0204)
640 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
641 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
642 #define DPCD_TEST_REQUEST (0x0218)
643 #define DPCD_TEST_RESPONSE (0x0260)
644 #define DPCD_TEST_EDID_CHECKSUM (0x0261)
645 #define DPCD_SINK_POWER_STATE (0x0600)
646
647 /* DPCD_TEST_REQUEST */
648 #define DPCD_TEST_EDID_READ (0x1 << 2)
649
650 /* DPCD_TEST_RESPONSE */
651 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
652
653 /* DPCD_SINK_POWER_STATE */
654 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
655 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
656
657 /* I2C EDID Chip ID, Slave Address */
658 #define I2C_EDID_DEVICE_ADDR (0x50)
659 #define I2C_E_EDID_DEVICE_ADDR (0x30)
660 #define EDID_BLOCK_LENGTH (0x80)
661 #define EDID_HEADER_PATTERN (0x00)
662 #define EDID_EXTENSION_FLAG (0x7e)
663 #define EDID_CHECKSUM (0x7f)
664
665 /* DPCD_LANE0_1_STATUS */
666 #define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
667 #define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
668 #define DPCD_LANE1_CR_DONE (0x1 << 4)
669 #define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
670 #define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
671 #define DPCD_LANE0_CR_DONE (0x1 << 0)
672
673 /* DPCD_ADJUST_REQUEST_LANE0_1 */
674 #define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
675 #define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
676 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
677 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
678 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
679 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
680 #define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
681 #define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
682 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
683 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
684 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
685 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
686 #define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
687 #define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
688 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
689 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
690 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
691 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
692 #define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
693 #define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
694 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
695 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
696 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
697 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
698
699 /* DPCD_ADJUST_REQUEST_LANE2_3 */
700 #define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
701 #define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
702 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
703 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
704 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
705 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
706 #define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
707 #define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
708 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
709 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
710 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
711 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
712 #define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
713 #define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
714 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
715 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
716 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
717 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
718 #define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
719 #define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
720 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
721 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
722 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
723 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
724
725 /* DPCD_LANE_COUNT_SET */
726 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
727 #define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
728
729 /* DPCD_LANE_ALIGN__STATUS_UPDATED */
730 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
731 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
732 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
733
734 /* DPCD_TRAINING_LANE0_SET */
735 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
736 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
737 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
738 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
739 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
740 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
741 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
742 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
743
744 #define DPCD_REQ_ADJ_SWING (0x00)
745 #define DPCD_REQ_ADJ_EMPHASIS (0x01)
746
747 #define DP_LANE_STAT_CR_DONE (0x01 << 0)
748 #define DP_LANE_STAT_CE_DONE (0x01 << 1)
749 #define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
750
751 #endif
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