arch/arm/include/asm/arch-fsl-layerscape/config.h

   1 /*
   2  * Copyright 2015, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
   8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
   9
  10 #include <linux/kconfig.h>
  11 #include <fsl_ddrc_version.h>
  12
  13 #define CONFIG_STANDALONE_LOAD_ADDR     0x80300000
  14
  15 #ifdef CONFIG_SYS_FSL_DDR4
  16 #define CONFIG_SYS_FSL_DDRC_GEN4
  17 #else
  18 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3    /* Enable Freescale ARM DDR3 driver */
  19 #endif
  20
  21 #ifndef CONFIG_ARCH_LS1012A
  22 #define CONFIG_SYS_FSL_DDR              /* Freescale DDR driver */
  23 #define CONFIG_SYS_FSL_DDR_VER          FSL_DDR_VER_5_0
  24 #endif
  25
  26 /*
  27  * Reserve secure memory
  28  * To be aligned with MMU block size
  29  */
  30 #define CONFIG_SYS_MEM_RESERVE_SECURE   (2048 * 1024)   /* 2MB */
  31
  32 #ifdef CONFIG_LS2080A
  33 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS           { 1, 1, 4, 4 }
  34 #define SRDS_MAX_LANES  8
  35 #define CONFIG_SYS_FSL_SRDS_1
  36 #define CONFIG_SYS_FSL_SRDS_2
  37 #define CONFIG_SYS_PAGE_SIZE            0x10000
  38 #ifndef L1_CACHE_BYTES
  39 #define L1_CACHE_SHIFT          6
  40 #define L1_CACHE_BYTES          BIT(L1_CACHE_SHIFT)
  41 #endif
  42
  43 #define CONFIG_SYS_FSL_OCRAM_BASE       0x18000000      /* initial RAM */
  44 #define CONFIG_SYS_FSL_OCRAM_SIZE       0x00200000      /* 2M */
  45
  46 /* DDR */
  47 #define CONFIG_SYS_FSL_DDR_LE
  48 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
  49 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
  50
  51 #define CONFIG_SYS_FSL_CCSR_GUR_LE
  52 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
  53 #define CONFIG_SYS_FSL_ESDHC_LE
  54 #define CONFIG_SYS_FSL_IFC_LE
  55 #define CONFIG_SYS_FSL_PEX_LUT_LE
  56
  57 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  58
  59 /* Generic Interrupt Controller Definitions */
  60 #define GICD_BASE                       0x06000000
  61 #define GICR_BASE                       0x06100000
  62
  63 /* SMMU Defintions */
  64 #define SMMU_BASE                       0x05000000 /* GR0 Base */
  65
  66 /* SFP */
  67 #define CONFIG_SYS_FSL_SFP_VER_3_4
  68 #define CONFIG_SYS_FSL_SFP_LE
  69 #define CONFIG_SYS_FSL_SRK_LE
  70
  71 /* SEC */
  72 #define CONFIG_SYS_FSL_SEC_LE
  73 #define CONFIG_SYS_FSL_SEC_COMPAT       5
  74
  75 /* Security Monitor */
  76 #define CONFIG_SYS_FSL_SEC_MON_LE
  77
  78 /* Secure Boot */
  79 #define CONFIG_ESBC_HDR_LS
  80
  81 /* DCFG - GUR */
  82 #define CONFIG_SYS_FSL_CCSR_GUR_LE
  83
  84 /* Cache Coherent Interconnect */
  85 #define CCI_MN_BASE                     0x04000000
  86 #define CCI_MN_RNF_NODEID_LIST          0x180
  87 #define CCI_MN_DVM_DOMAIN_CTL           0x200
  88 #define CCI_MN_DVM_DOMAIN_CTL_SET       0x210
  89
  90 #define CCI_HN_F_0_BASE                 (CCI_MN_BASE + 0x200000)
  91 #define CCI_HN_F_1_BASE                 (CCI_MN_BASE + 0x210000)
  92 #define CCN_HN_F_SAM_CTL                0x8     /* offset on base HN_F base */
  93 #define CCN_HN_F_SAM_NODEID_MASK        0x7f
  94 #define CCN_HN_F_SAM_NODEID_DDR0        0x4
  95 #define CCN_HN_F_SAM_NODEID_DDR1        0xe
  96
  97 #define CCI_RN_I_0_BASE                 (CCI_MN_BASE + 0x800000)
  98 #define CCI_RN_I_2_BASE                 (CCI_MN_BASE + 0x820000)
  99 #define CCI_RN_I_6_BASE                 (CCI_MN_BASE + 0x860000)
 100 #define CCI_RN_I_12_BASE                (CCI_MN_BASE + 0x8C0000)
 101 #define CCI_RN_I_16_BASE                (CCI_MN_BASE + 0x900000)
 102 #define CCI_RN_I_20_BASE                (CCI_MN_BASE + 0x940000)
 103
 104 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
 105 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
 106 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
 107
 108 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
 109
 110 /* TZ Protection Controller Definitions */
 111 #define TZPC_BASE                               0x02200000
 112 #define TZPCR0SIZE_BASE                         (TZPC_BASE)
 113 #define TZPCDECPROT_0_STAT_BASE                 (TZPC_BASE + 0x800)
 114 #define TZPCDECPROT_0_SET_BASE                  (TZPC_BASE + 0x804)
 115 #define TZPCDECPROT_0_CLR_BASE                  (TZPC_BASE + 0x808)
 116 #define TZPCDECPROT_1_STAT_BASE                 (TZPC_BASE + 0x80C)
 117 #define TZPCDECPROT_1_SET_BASE                  (TZPC_BASE + 0x810)
 118 #define TZPCDECPROT_1_CLR_BASE                  (TZPC_BASE + 0x814)
 119 #define TZPCDECPROT_2_STAT_BASE                 (TZPC_BASE + 0x818)
 120 #define TZPCDECPROT_2_SET_BASE                  (TZPC_BASE + 0x81C)
 121 #define TZPCDECPROT_2_CLR_BASE                  (TZPC_BASE + 0x820)
 122
 123 #define DCSR_CGACRE5            0x700070914ULL
 124 #define EPU_EPCMPR5             0x700060914ULL
 125 #define EPU_EPCCR5              0x700060814ULL
 126 #define EPU_EPSMCR5             0x700060228ULL
 127 #define EPU_EPECR5              0x700060314ULL
 128 #define EPU_EPCTR5              0x700060a14ULL
 129 #define EPU_EPGCR               0x700060000ULL
 130
 131 #define CONFIG_SYS_FSL_ERRATUM_A008336
 132 #define CONFIG_SYS_FSL_ERRATUM_A008511
 133 #define CONFIG_SYS_FSL_ERRATUM_A008514
 134 #define CONFIG_SYS_FSL_ERRATUM_A008585
 135 #define CONFIG_SYS_FSL_ERRATUM_A008751
 136 #define CONFIG_SYS_FSL_ERRATUM_A009635
 137 #define CONFIG_SYS_FSL_ERRATUM_A009663
 138 #define CONFIG_SYS_FSL_ERRATUM_A009801
 139 #define CONFIG_SYS_FSL_ERRATUM_A009803
 140 #define CONFIG_SYS_FSL_ERRATUM_A009942
 141 #define CONFIG_SYS_FSL_ERRATUM_A010165
 142
 143 /* ARM A57 CORE ERRATA */
 144 #define CONFIG_ARM_ERRATA_826974
 145 #define CONFIG_ARM_ERRATA_828024
 146 #define CONFIG_ARM_ERRATA_829520
 147 #define CONFIG_ARM_ERRATA_833471
 148
 149 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 150 #elif defined(CONFIG_FSL_LSCH2)
 151 #define CONFIG_SYS_FSL_SEC_COMPAT               5
 152 #define CONFIG_SYS_FSL_OCRAM_BASE               0x10000000 /* initial RAM */
 153 #define CONFIG_SYS_FSL_OCRAM_SIZE               0x00200000 /* 2M */
 154 #define CONFIG_SYS_CCSRBAR_DEFAULT              0x01000000
 155
 156 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
 157 #define CONFIG_SYS_FSL_ESDHC_BE
 158 #define CONFIG_SYS_FSL_WDOG_BE
 159 #define CONFIG_SYS_FSL_DSPI_BE
 160 #define CONFIG_SYS_FSL_QSPI_BE
 161 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 162 #define CONFIG_SYS_FSL_PEX_LUT_BE
 163 #define CONFIG_SYS_FSL_SEC_BE
 164
 165 #define CONFIG_SYS_FSL_SRDS_1
 166
 167 /* SoC related */
 168 #ifdef CONFIG_LS1043A
 169 #define CONFIG_SYS_FMAN_V3
 170 #define CONFIG_SYS_NUM_FMAN                     1
 171 #define CONFIG_SYS_NUM_FM1_DTSEC                7
 172 #define CONFIG_SYS_NUM_FM1_10GEC                1
 173 #define CONFIG_SYS_FSL_DDR_BE
 174 #define CONFIG_SYS_DDR_BLOCK1_SIZE              ((phys_size_t)2 << 30)
 175 #define CONFIG_MAX_MEM_MAPPED                   CONFIG_SYS_DDR_BLOCK1_SIZE
 176
 177 #define QE_MURAM_SIZE           0x6000UL
 178 #define MAX_QE_RISC             1
 179 #define QE_NUM_OF_SNUM          28
 180
 181 #define CONFIG_SYS_FSL_IFC_BE
 182 #define CONFIG_SYS_FSL_SFP_VER_3_2
 183 #define CONFIG_SYS_FSL_SEC_MON_BE
 184 #define CONFIG_SYS_FSL_SFP_BE
 185 #define CONFIG_SYS_FSL_SRK_LE
 186 #define CONFIG_KEY_REVOCATION
 187
 188 /* SMMU Defintions */
 189 #define SMMU_BASE               0x09000000
 190
 191 /* Generic Interrupt Controller Definitions */
 192 #define GICD_BASE               0x01401000
 193 #define GICC_BASE               0x01402000
 194
 195 #define CONFIG_SYS_FSL_ERRATUM_A008850
 196 #define CONFIG_SYS_FSL_ERRATUM_A009663
 197 #define CONFIG_SYS_FSL_ERRATUM_A009929
 198 #define CONFIG_SYS_FSL_ERRATUM_A009942
 199 #define CONFIG_SYS_FSL_ERRATUM_A009660
 200 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 201 #elif defined(CONFIG_ARCH_LS1012A)
 202 #undef  CONFIG_SYS_FSL_DDRC_ARM_GEN3
 203
 204 #define GICD_BASE               0x01401000
 205 #define GICC_BASE               0x01402000
 206 #elif defined(CONFIG_ARCH_LS1046A)
 207 #define CONFIG_SYS_FMAN_V3
 208 #define CONFIG_SYS_NUM_FMAN                     1
 209 #define CONFIG_SYS_NUM_FM1_DTSEC                8
 210 #define CONFIG_SYS_NUM_FM1_10GEC                2
 211 #define CONFIG_SYS_FSL_DDR_BE
 212 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 213 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 214
 215 #define CONFIG_SYS_FSL_SRDS_2
 216 #define CONFIG_SYS_FSL_IFC_BE
 217 #define CONFIG_SYS_FSL_SFP_VER_3_2
 218 #define CONFIG_SYS_FSL_SNVS_LE
 219 #define CONFIG_SYS_FSL_SFP_BE
 220 #define CONFIG_SYS_FSL_SRK_LE
 221 #define CONFIG_KEY_REVOCATION
 222
 223 /* SMMU Defintions */
 224 #define SMMU_BASE               0x09000000
 225
 226 /* Generic Interrupt Controller Definitions */
 227 #define GICD_BASE               0x01410000
 228 #define GICC_BASE               0x01420000
 229
 230 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 231
 232 #define CONFIG_SYS_FSL_ERRATUM_A008511
 233 #define CONFIG_SYS_FSL_ERRATUM_A009801
 234 #define CONFIG_SYS_FSL_ERRATUM_A009803
 235 #define CONFIG_SYS_FSL_ERRATUM_A009942
 236 #define CONFIG_SYS_FSL_ERRATUM_A010165
 237 #else
 238 #error SoC not defined
 239 #endif
 240 #endif
 241
 242 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */