arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #ifndef __FSL_STREAM_ID_H
   8 #define __FSL_STREAM_ID_H
   9
  10 /*
  11  * Stream IDs on ls2080a devices are not hardwired and are
  12  * programmed by sw.  There are a limited number of stream IDs
  13  * available, and the partitioning of them is scenario dependent.
  14  * This header defines the partitioning between legacy, PCI,
  15  * and DPAA2 devices.
  16  *
  17  * This partitioning can be customized in this file depending
  18  * on the specific hardware config:
  19  *
  20  *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
  21  *     -all legacy devices get a unique stream ID assigned and programmed in
  22  *      their AMQR registers by u-boot
  23  *
  24  *  -PCIe
  25  *     -there is a range of stream IDs set aside for PCI in this
  26  *      file.  U-boot will scan the PCI bus and for each device discovered:
  27  *         -allocate a streamID
  28  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  29  *         -set a msi-map entry in the PEXn controller node in the
  30  *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
  31  *          for more info on the msi-map definition)
  32  *
  33  *  -DPAA2
  34  *     -u-boot will allocate a range of stream IDs to be used by the Management
  35  *      Complex for containers and will set these values in the MC DPC image.
  36  *     -the MC is responsible for allocating and setting up 'isolation context
  37  *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  38  *
  39  * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
  40  * each of the different bus masters.  The relationship between
  41  * the AMQ registers and stream IDs is defined in the table below:
  42  *          AMQ bit    streamID bit
  43  *      ---------------------------
  44  *           PL[18]         9        // privilege bit
  45  *          BMT[17]         8        // bypass translation
  46  *           VA[16]         7        // reserved
  47  *             [15]         -        // unused
  48  *         ICID[14:7]       -        // unused
  49  *         ICID[6:0]        6-0      // isolation context id
  50  *     ----------------------------
  51  *
  52  */
  53
  54 #define AMQ_PL_MASK                     (0x1 << 18)   /* priviledge bit */
  55 #define AMQ_BMT_MASK                    (0x1 << 17)   /* bypass bit */
  56
  57 #define FSL_INVALID_STREAM_ID           0
  58
  59 #define FSL_BYPASS_AMQ                  (AMQ_PL_MASK | AMQ_BMT_MASK)
  60
  61 /* legacy devices */
  62 #define FSL_USB1_STREAM_ID              1
  63 #define FSL_USB2_STREAM_ID              2
  64 #define FSL_SDMMC_STREAM_ID             3
  65 #define FSL_SATA1_STREAM_ID             4
  66 #define FSL_SATA2_STREAM_ID             5
  67 #define FSL_DMA_STREAM_ID               6
  68
  69 /* PCI - programmed in PEXn_LUT */
  70 #define FSL_PEX_STREAM_ID_START         7
  71 #define FSL_PEX_STREAM_ID_END           22
  72
  73 /* DPAA2 - set in MC DPC and alloced by MC */
  74 #define FSL_DPAA2_STREAM_ID_START       23
  75 #define FSL_DPAA2_STREAM_ID_END         63
  76
  77 #endif