arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_LS102XA_DEVDIS_H_
   8 #define __FSL_LS102XA_DEVDIS_H_
   9
  10 #include <fsl_devdis.h>
  11
  12 const struct devdis_table devdis_tbl[] = {
  13         { "pbl", 0x0, 0x80000000 },     /* PBL  */
  14         { "esdhc", 0x0, 0x20000000 },   /* eSDHC        */
  15         { "qdma", 0x0, 0x800000 },      /* qDMA         */
  16         { "edma", 0x0, 0x400000 },      /* eDMA         */
  17         { "usb3", 0x0, 0x84000 },       /* USB3.0 controller and PHY*/
  18         { "usb2", 0x0, 0x40000 },       /* USB2.0 controller    */
  19         { "sata", 0x0, 0x8000 },        /* SATA         */
  20         { "sec", 0x0, 0x200 },          /* SEC          */
  21         { "dcu", 0x0, 0x2 },            /* Display controller Unit      */
  22         { "qe", 0x0, 0x1 },             /* QUICC Engine */
  23         { "etsec1", 0x1, 0x80000000 },  /* eTSEC1 controller    */
  24         { "etesc2", 0x1, 0x40000000 },  /* eTSEC2 controller    */
  25         { "etsec3", 0x1, 0x20000000 },  /* eTSEC3 controller    */
  26         { "pex1", 0x2, 0x80000000 },    /* PCIE controller 1    */
  27         { "pex2", 0x2, 0x40000000 },    /* PCIE controller 2    */
  28         { "duart1", 0x3, 0x20000000 },  /* DUART1       */
  29         { "duart2", 0x3, 0x10000000 },  /* DUART2       */
  30         { "qspi", 0x3, 0x8000000 },     /* QSPI         */
  31         { "ddr", 0x4, 0x80000000 },     /* DDR          */
  32         { "ocram1", 0x4, 0x8000000 },   /* OCRAM1       */
  33         { "ifc", 0x4, 0x800000 },       /* IFC          */
  34         { "gpio", 0x4, 0x400000 },      /* GPIO         */
  35         { "dbg", 0x4, 0x200000 },       /* DBG          */
  36         { "can1", 0x4, 0x80000 },       /* FlexCAN1     */
  37         { "can2_4", 0x4, 0x40000 },     /* FlexCAN2_3_4 */
  38         { "ftm2_8", 0x4, 0x20000 },     /* FlexTimer2_3_4_5_6_7_8       */
  39         { "secmon", 0x4, 0x4000 },      /* Security Monitor     */
  40         { "wdog1_2", 0x4, 0x400 },      /* WatchDog1_2  */
  41         { "i2c2_3", 0x4, 0x200 },       /* I2C2_3       */
  42         { "sai1_4", 0x4, 0x100 },       /* SAI1_2_3_4   */
  43         { "lpuart2_6", 0x4, 0x80 },     /* LPUART2_3_4_5_6      */
  44         { "dspi1_2", 0x4, 0x40 },       /* DSPI1_2      */
  45         { "asrc", 0x4, 0x20 },          /* ASRC         */
  46         { "spdif", 0x4, 0x10 },         /* SPDIF        */
  47         { "i2c1", 0x4, 0x4 },           /* I2C1         */
  48         { "lpuart1", 0x4, 0x2 },        /* LPUART1      */
  49         { "ftm1", 0x4, 0x1 },           /* FlexTimer1   */
  50 };
  51
  52 #endif