arch/arm/include/asm/arch-mx6/mx6-ddr.h

   1 /*
   2  * Copyright (C) 2013 Boundary Devices Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __ASM_ARCH_MX6_DDR_H__
   7 #define __ASM_ARCH_MX6_DDR_H__
   8
   9 #ifdef CONFIG_MX6Q
  10 #include "mx6q-ddr.h"
  11 #else
  12 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  13 #include "mx6dl-ddr.h"
  14 #else
  15 #error "Please select cpu"
  16 #endif  /* CONFIG_MX6DL or CONFIG_MX6S */
  17 #endif  /* CONFIG_MX6Q */
  18
  19 #define MX6_MMDC_P0_MDCTL       0x021b0000
  20 #define MX6_MMDC_P0_MDPDC       0x021b0004
  21 #define MX6_MMDC_P0_MDOTC       0x021b0008
  22 #define MX6_MMDC_P0_MDCFG0      0x021b000c
  23 #define MX6_MMDC_P0_MDCFG1      0x021b0010
  24 #define MX6_MMDC_P0_MDCFG2      0x021b0014
  25 #define MX6_MMDC_P0_MDMISC      0x021b0018
  26 #define MX6_MMDC_P0_MDSCR       0x021b001c
  27 #define MX6_MMDC_P0_MDREF       0x021b0020
  28 #define MX6_MMDC_P0_MDRWD       0x021b002c
  29 #define MX6_MMDC_P0_MDOR        0x021b0030
  30 #define MX6_MMDC_P0_MDASP       0x021b0040
  31 #define MX6_MMDC_P0_MAPSR       0x021b0404
  32 #define MX6_MMDC_P0_MPZQHWCTRL  0x021b0800
  33 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
  34 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
  35 #define MX6_MMDC_P0_MPODTCTRL   0x021b0818
  36 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
  37 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
  38 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
  39 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
  40 #define MX6_MMDC_P0_MPDGCTRL0   0x021b083c
  41 #define MX6_MMDC_P0_MPDGCTRL1   0x021b0840
  42 #define MX6_MMDC_P0_MPRDDLCTL   0x021b0848
  43 #define MX6_MMDC_P0_MPWRDLCTL   0x021b0850
  44 #define MX6_MMDC_P0_MPMUR0      0x021b08b8
  45
  46 #define MX6_MMDC_P1_MDCTL       0x021b4000
  47 #define MX6_MMDC_P1_MDPDC       0x021b4004
  48 #define MX6_MMDC_P1_MDOTC       0x021b4008
  49 #define MX6_MMDC_P1_MDCFG0      0x021b400c
  50 #define MX6_MMDC_P1_MDCFG1      0x021b4010
  51 #define MX6_MMDC_P1_MDCFG2      0x021b4014
  52 #define MX6_MMDC_P1_MDMISC      0x021b4018
  53 #define MX6_MMDC_P1_MDSCR       0x021b401c
  54 #define MX6_MMDC_P1_MDREF       0x021b4020
  55 #define MX6_MMDC_P1_MDRWD       0x021b402c
  56 #define MX6_MMDC_P1_MDOR        0x021b4030
  57 #define MX6_MMDC_P1_MDASP       0x021b4040
  58 #define MX6_MMDC_P1_MAPSR       0x021b4404
  59 #define MX6_MMDC_P1_MPZQHWCTRL  0x021b4800
  60 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
  61 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
  62 #define MX6_MMDC_P1_MPODTCTRL   0x021b4818
  63 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
  64 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
  65 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
  66 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
  67 #define MX6_MMDC_P1_MPDGCTRL0   0x021b483c
  68 #define MX6_MMDC_P1_MPDGCTRL1   0x021b4840
  69 #define MX6_MMDC_P1_MPRDDLCTL   0x021b4848
  70 #define MX6_MMDC_P1_MPWRDLCTL   0x021b4850
  71 #define MX6_MMDC_P1_MPMUR0      0x021b48b8
  72
  73 #endif  /*__ASM_ARCH_MX6_DDR_H__ */