arch/arm/include/asm/arch-mx6/mx6-ddr.h

   1 /*
   2  * Copyright (C) 2013 Boundary Devices Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __ASM_ARCH_MX6_DDR_H__
   7 #define __ASM_ARCH_MX6_DDR_H__
   8
   9 #ifndef CONFIG_SPL_BUILD
  10 #ifdef CONFIG_MX6Q
  11 #include "mx6q-ddr.h"
  12 #else
  13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  14 #include "mx6dl-ddr.h"
  15 #else
  16 #error "Please select cpu"
  17 #endif  /* CONFIG_MX6DL or CONFIG_MX6S */
  18 #endif  /* CONFIG_MX6Q */
  19 #else
  20
  21 /* MMDC P0/P1 Registers */
  22 struct mmdc_p_regs {
  23         u32 mdctl;
  24         u32 mdpdc;
  25         u32 mdotc;
  26         u32 mdcfg0;
  27         u32 mdcfg1;
  28         u32 mdcfg2;
  29         u32 mdmisc;
  30         u32 mdscr;
  31         u32 mdref;
  32         u32 res1[2];
  33         u32 mdrwd;
  34         u32 mdor;
  35         u32 res2[3];
  36         u32 mdasp;
  37         u32 res3[240];
  38         u32 mapsr;
  39         u32 res4[254];
  40         u32 mpzqhwctrl;
  41         u32 res5[2];
  42         u32 mpwldectrl0;
  43         u32 mpwldectrl1;
  44         u32 res6;
  45         u32 mpodtctrl;
  46         u32 mprddqby0dl;
  47         u32 mprddqby1dl;
  48         u32 mprddqby2dl;
  49         u32 mprddqby3dl;
  50         u32 res7[4];
  51         u32 mpdgctrl0;
  52         u32 mpdgctrl1;
  53         u32 res8;
  54         u32 mprddlctl;
  55         u32 res9;
  56         u32 mpwrdlctl;
  57         u32 res10[25];
  58         u32 mpmur0;
  59 };
  60
  61 /*
  62  * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
  63  */
  64 #define MX6DQ_IOM_DDR_BASE      0x020e0500
  65 struct mx6dq_iomux_ddr_regs {
  66         u32 res1[3];
  67         u32 dram_sdqs5;
  68         u32 dram_dqm5;
  69         u32 dram_dqm4;
  70         u32 dram_sdqs4;
  71         u32 dram_sdqs3;
  72         u32 dram_dqm3;
  73         u32 dram_sdqs2;
  74         u32 dram_dqm2;
  75         u32 res2[16];
  76         u32 dram_cas;
  77         u32 res3[2];
  78         u32 dram_ras;
  79         u32 dram_reset;
  80         u32 res4[2];
  81         u32 dram_sdclk_0;
  82         u32 dram_sdba2;
  83         u32 dram_sdcke0;
  84         u32 dram_sdclk_1;
  85         u32 dram_sdcke1;
  86         u32 dram_sdodt0;
  87         u32 dram_sdodt1;
  88         u32 res5;
  89         u32 dram_sdqs0;
  90         u32 dram_dqm0;
  91         u32 dram_sdqs1;
  92         u32 dram_dqm1;
  93         u32 dram_sdqs6;
  94         u32 dram_dqm6;
  95         u32 dram_sdqs7;
  96         u32 dram_dqm7;
  97 };
  98
  99 #define MX6DQ_IOM_GRP_BASE      0x020e0700
 100 struct mx6dq_iomux_grp_regs {
 101         u32 res1[18];
 102         u32 grp_b7ds;
 103         u32 grp_addds;
 104         u32 grp_ddrmode_ctl;
 105         u32 res2;
 106         u32 grp_ddrpke;
 107         u32 res3[6];
 108         u32 grp_ddrmode;
 109         u32 res4[3];
 110         u32 grp_b0ds;
 111         u32 grp_b1ds;
 112         u32 grp_ctlds;
 113         u32 res5;
 114         u32 grp_b2ds;
 115         u32 grp_ddr_type;
 116         u32 grp_b3ds;
 117         u32 grp_b4ds;
 118         u32 grp_b5ds;
 119         u32 grp_b6ds;
 120 };
 121
 122 #define MX6SDL_IOM_DDR_BASE     0x020e0400
 123 struct mx6sdl_iomux_ddr_regs {
 124         u32 res1[25];
 125         u32 dram_cas;
 126         u32 res2[2];
 127         u32 dram_dqm0;
 128         u32 dram_dqm1;
 129         u32 dram_dqm2;
 130         u32 dram_dqm3;
 131         u32 dram_dqm4;
 132         u32 dram_dqm5;
 133         u32 dram_dqm6;
 134         u32 dram_dqm7;
 135         u32 dram_ras;
 136         u32 dram_reset;
 137         u32 res3[2];
 138         u32 dram_sdba2;
 139         u32 dram_sdcke0;
 140         u32 dram_sdcke1;
 141         u32 dram_sdclk_0;
 142         u32 dram_sdclk_1;
 143         u32 dram_sdodt0;
 144         u32 dram_sdodt1;
 145         u32 dram_sdqs0;
 146         u32 dram_sdqs1;
 147         u32 dram_sdqs2;
 148         u32 dram_sdqs3;
 149         u32 dram_sdqs4;
 150         u32 dram_sdqs5;
 151         u32 dram_sdqs6;
 152         u32 dram_sdqs7;
 153 };
 154
 155 #define MX6SDL_IOM_GRP_BASE     0x020e0700
 156 struct mx6sdl_iomux_grp_regs {
 157         u32 res1[18];
 158         u32 grp_b7ds;
 159         u32 grp_addds;
 160         u32 grp_ddrmode_ctl;
 161         u32 grp_ddrpke;
 162         u32 res2[2];
 163         u32 grp_ddrmode;
 164         u32 grp_b0ds;
 165         u32 res3;
 166         u32 grp_ctlds;
 167         u32 grp_b1ds;
 168         u32 grp_ddr_type;
 169         u32 grp_b2ds;
 170         u32 grp_b3ds;
 171         u32 grp_b4ds;
 172         u32 grp_b5ds;
 173         u32 res4;
 174         u32 grp_b6ds;
 175 };
 176 #endif /* CONFIG_SPL_BUILD */
 177
 178 #define MX6_MMDC_P0_MDCTL       0x021b0000
 179 #define MX6_MMDC_P0_MDPDC       0x021b0004
 180 #define MX6_MMDC_P0_MDOTC       0x021b0008
 181 #define MX6_MMDC_P0_MDCFG0      0x021b000c
 182 #define MX6_MMDC_P0_MDCFG1      0x021b0010
 183 #define MX6_MMDC_P0_MDCFG2      0x021b0014
 184 #define MX6_MMDC_P0_MDMISC      0x021b0018
 185 #define MX6_MMDC_P0_MDSCR       0x021b001c
 186 #define MX6_MMDC_P0_MDREF       0x021b0020
 187 #define MX6_MMDC_P0_MDRWD       0x021b002c
 188 #define MX6_MMDC_P0_MDOR        0x021b0030
 189 #define MX6_MMDC_P0_MDASP       0x021b0040
 190 #define MX6_MMDC_P0_MAPSR       0x021b0404
 191 #define MX6_MMDC_P0_MPZQHWCTRL  0x021b0800
 192 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
 193 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
 194 #define MX6_MMDC_P0_MPODTCTRL   0x021b0818
 195 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
 196 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
 197 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
 198 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
 199 #define MX6_MMDC_P0_MPDGCTRL0   0x021b083c
 200 #define MX6_MMDC_P0_MPDGCTRL1   0x021b0840
 201 #define MX6_MMDC_P0_MPRDDLCTL   0x021b0848
 202 #define MX6_MMDC_P0_MPWRDLCTL   0x021b0850
 203 #define MX6_MMDC_P0_MPMUR0      0x021b08b8
 204
 205 #define MX6_MMDC_P1_MDCTL       0x021b4000
 206 #define MX6_MMDC_P1_MDPDC       0x021b4004
 207 #define MX6_MMDC_P1_MDOTC       0x021b4008
 208 #define MX6_MMDC_P1_MDCFG0      0x021b400c
 209 #define MX6_MMDC_P1_MDCFG1      0x021b4010
 210 #define MX6_MMDC_P1_MDCFG2      0x021b4014
 211 #define MX6_MMDC_P1_MDMISC      0x021b4018
 212 #define MX6_MMDC_P1_MDSCR       0x021b401c
 213 #define MX6_MMDC_P1_MDREF       0x021b4020
 214 #define MX6_MMDC_P1_MDRWD       0x021b402c
 215 #define MX6_MMDC_P1_MDOR        0x021b4030
 216 #define MX6_MMDC_P1_MDASP       0x021b4040
 217 #define MX6_MMDC_P1_MAPSR       0x021b4404
 218 #define MX6_MMDC_P1_MPZQHWCTRL  0x021b4800
 219 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
 220 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
 221 #define MX6_MMDC_P1_MPODTCTRL   0x021b4818
 222 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
 223 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
 224 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
 225 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
 226 #define MX6_MMDC_P1_MPDGCTRL0   0x021b483c
 227 #define MX6_MMDC_P1_MPDGCTRL1   0x021b4840
 228 #define MX6_MMDC_P1_MPRDDLCTL   0x021b4848
 229 #define MX6_MMDC_P1_MPWRDLCTL   0x021b4850
 230 #define MX6_MMDC_P1_MPMUR0      0x021b48b8
 231
 232 #endif  /*__ASM_ARCH_MX6_DDR_H__ */