arch/arm/include/asm/arch-mx6/mx6dl-ddr.h

   1 /*
   2  * Copyright (C) 2013 Boundary Devices Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __ASM_ARCH_MX6DLS_DDR_H__
   7 #define __ASM_ARCH_MX6DLS_DDR_H__
   8
   9 #ifndef CONFIG_MX6DL
  10 #ifndef CONFIG_MX6S
  11 #error "wrong CPU"
  12 #endif
  13 #endif
  14
  15 #define MX6_IOM_DRAM_DQM0       0x020e0470
  16 #define MX6_IOM_DRAM_DQM1       0x020e0474
  17 #define MX6_IOM_DRAM_DQM2       0x020e0478
  18 #define MX6_IOM_DRAM_DQM3       0x020e047c
  19 #define MX6_IOM_DRAM_DQM4       0x020e0480
  20 #define MX6_IOM_DRAM_DQM5       0x020e0484
  21 #define MX6_IOM_DRAM_DQM6       0x020e0488
  22 #define MX6_IOM_DRAM_DQM7       0x020e048c
  23
  24 #define MX6_IOM_DRAM_CAS        0x020e0464
  25 #define MX6_IOM_DRAM_RAS        0x020e0490
  26 #define MX6_IOM_DRAM_RESET      0x020e0494
  27 #define MX6_IOM_DRAM_SDCLK_0    0x020e04ac
  28 #define MX6_IOM_DRAM_SDCLK_1    0x020e04b0
  29 #define MX6_IOM_DRAM_SDBA2      0x020e04a0
  30 #define MX6_IOM_DRAM_SDCKE0     0x020e04a4
  31 #define MX6_IOM_DRAM_SDCKE1     0x020e04a8
  32 #define MX6_IOM_DRAM_SDODT0     0x020e04b4
  33 #define MX6_IOM_DRAM_SDODT1     0x020e04b8
  34
  35 #define MX6_IOM_DRAM_SDQS0      0x020e04bc
  36 #define MX6_IOM_DRAM_SDQS1      0x020e04c0
  37 #define MX6_IOM_DRAM_SDQS2      0x020e04c4
  38 #define MX6_IOM_DRAM_SDQS3      0x020e04c8
  39 #define MX6_IOM_DRAM_SDQS4      0x020e04cc
  40 #define MX6_IOM_DRAM_SDQS5      0x020e04d0
  41 #define MX6_IOM_DRAM_SDQS6      0x020e04d4
  42 #define MX6_IOM_DRAM_SDQS7      0x020e04d8
  43
  44 #define MX6_IOM_GRP_B0DS        0x020e0764
  45 #define MX6_IOM_GRP_B1DS        0x020e0770
  46 #define MX6_IOM_GRP_B2DS        0x020e0778
  47 #define MX6_IOM_GRP_B3DS        0x020e077c
  48 #define MX6_IOM_GRP_B4DS        0x020e0780
  49 #define MX6_IOM_GRP_B5DS        0x020e0784
  50 #define MX6_IOM_GRP_B6DS        0x020e078c
  51 #define MX6_IOM_GRP_B7DS        0x020e0748
  52 #define MX6_IOM_GRP_ADDDS       0x020e074c
  53 #define MX6_IOM_DDRMODE_CTL     0x020e0750
  54 #define MX6_IOM_GRP_DDRPKE      0x020e0754
  55 #define MX6_IOM_GRP_DDRMODE     0x020e0760
  56 #define MX6_IOM_GRP_CTLDS       0x020e076c
  57 #define MX6_IOM_GRP_DDR_TYPE    0x020e0774
  58
  59 #endif  /*__ASM_ARCH_MX6S_DDR_H__ */