]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/include/asm/arch-mxs/regs-timrot.h
2 * Freescale i.MX28 TIMROT Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * Based on code from LTIB:
7 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef __MX28_REGS_TIMROT_H__
13 #define __MX28_REGS_TIMROT_H__
15 #include <asm/imx-common/regs-common.h>
18 struct mxs_timrot_regs
{
19 mxs_reg_32(hw_timrot_rotctrl
)
20 mxs_reg_32(hw_timrot_rotcount
)
21 #if defined(CONFIG_MX23)
22 mxs_reg_32(hw_timrot_timctrl0
)
23 mxs_reg_32(hw_timrot_timcount0
)
24 mxs_reg_32(hw_timrot_timctrl1
)
25 mxs_reg_32(hw_timrot_timcount1
)
26 mxs_reg_32(hw_timrot_timctrl2
)
27 mxs_reg_32(hw_timrot_timcount2
)
28 mxs_reg_32(hw_timrot_timctrl3
)
29 mxs_reg_32(hw_timrot_timcount3
)
30 #elif defined(CONFIG_MX28)
31 mxs_reg_32(hw_timrot_timctrl0
)
32 mxs_reg_32(hw_timrot_running_count0
)
33 mxs_reg_32(hw_timrot_fixed_count0
)
34 mxs_reg_32(hw_timrot_match_count0
)
35 mxs_reg_32(hw_timrot_timctrl1
)
36 mxs_reg_32(hw_timrot_running_count1
)
37 mxs_reg_32(hw_timrot_fixed_count1
)
38 mxs_reg_32(hw_timrot_match_count1
)
39 mxs_reg_32(hw_timrot_timctrl2
)
40 mxs_reg_32(hw_timrot_running_count2
)
41 mxs_reg_32(hw_timrot_fixed_count2
)
42 mxs_reg_32(hw_timrot_match_count2
)
43 mxs_reg_32(hw_timrot_timctrl3
)
44 mxs_reg_32(hw_timrot_running_count3
)
45 mxs_reg_32(hw_timrot_fixed_count3
)
46 mxs_reg_32(hw_timrot_match_count3
)
48 mxs_reg_32(hw_timrot_version
)
52 #define TIMROT_ROTCTRL_SFTRST (1 << 31)
53 #define TIMROT_ROTCTRL_CLKGATE (1 << 30)
54 #define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29)
55 #define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28)
56 #define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27)
57 #define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26)
58 #define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25)
59 #define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22)
60 #define TIMROT_ROTCTRL_STATE_OFFSET 22
61 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
62 #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
63 #define TIMROT_ROTCTRL_RELATIVE (1 << 12)
64 #define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10)
65 #define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10
66 #define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10)
67 #define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10)
68 #define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10)
69 #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
70 #define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
71 #define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
72 #if defined(CONFIG_MX23)
73 #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
74 #elif defined(CONFIG_MX28)
75 #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
77 #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
78 #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
79 #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
80 #define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4)
81 #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
82 #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
83 #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
84 #if defined(CONFIG_MX23)
85 #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4)
86 #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4)
87 #elif defined(CONFIG_MX28)
88 #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
89 #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
90 #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
91 #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
92 #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
94 #if defined(CONFIG_MX23)
95 #define TIMROT_ROTCTRL_SELECT_A_MASK 0x7
96 #elif defined(CONFIG_MX28)
97 #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
99 #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
100 #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
101 #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
102 #define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2
103 #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
104 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
105 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
106 #if defined(CONFIG_MX23)
107 #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6
108 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7
109 #elif defined(CONFIG_MX28)
110 #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
111 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
112 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
113 #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
114 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
117 #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
118 #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
120 #define TIMROT_TIMCTRLn_IRQ (1 << 15)
121 #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
122 #if defined(CONFIG_MX28)
123 #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
125 #define TIMROT_TIMCTRLn_POLARITY (1 << 8)
126 #define TIMROT_TIMCTRLn_UPDATE (1 << 7)
127 #define TIMROT_TIMCTRLn_RELOAD (1 << 6)
128 #define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4)
129 #define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4
130 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4)
131 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4)
132 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4)
133 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4)
134 #define TIMROT_TIMCTRLn_SELECT_MASK 0xf
135 #define TIMROT_TIMCTRLn_SELECT_OFFSET 0
136 #define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0
137 #define TIMROT_TIMCTRLn_SELECT_PWM0 0x1
138 #define TIMROT_TIMCTRLn_SELECT_PWM1 0x2
139 #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
140 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
141 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
142 #if defined(CONFIG_MX23)
143 #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6
144 #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7
145 #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8
146 #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9
147 #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa
148 #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb
149 #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc
150 #elif defined(CONFIG_MX28)
151 #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
152 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
153 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
154 #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9
155 #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa
156 #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb
157 #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc
158 #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
159 #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
160 #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
163 #if defined(CONFIG_MX23)
164 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
165 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
166 #elif defined(CONFIG_MX28)
167 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
168 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
171 #if defined(CONFIG_MX23)
172 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff
173 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
174 #elif defined(CONFIG_MX28)
175 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
176 #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
179 #if defined(CONFIG_MX28)
180 #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
181 #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
184 #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
185 #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
186 #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16)
187 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16)
188 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16)
189 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
190 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
191 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
192 #if defined(CONFIG_MX23)
193 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
194 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
195 #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
196 #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
197 #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
198 #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
199 #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
200 #elif defined(CONFIG_MX28)
201 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
202 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
203 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
204 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16)
205 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16)
206 #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16)
207 #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16)
208 #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
209 #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
210 #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
212 #if defined(CONFIG_MX23)
213 #define TIMROT_TIMCTRL3_IRQ (1 << 15)
214 #define TIMROT_TIMCTRL3_IRQ_EN (1 << 14)
215 #define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10)
217 #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
218 #if defined(CONFIG_MX23)
219 #define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8)
220 #define TIMROT_TIMCTRL3_POLARITY_OFFSET 8
221 #define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8)
222 #define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8)
223 #define TIMROT_TIMCTRL3_UPDATE (1 << 7)
224 #define TIMROT_TIMCTRL3_RELOAD (1 << 6)
225 #define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4)
226 #define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4
227 #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4)
228 #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4)
229 #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4)
230 #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4)
231 #define TIMROT_TIMCTRL3_SELECT_MASK 0xf
232 #define TIMROT_TIMCTRL3_SELECT_OFFSET 0
233 #define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0
234 #define TIMROT_TIMCTRL3_SELECT_PWM0 0x1
235 #define TIMROT_TIMCTRL3_SELECT_PWM1 0x2
236 #define TIMROT_TIMCTRL3_SELECT_PWM2 0x3
237 #define TIMROT_TIMCTRL3_SELECT_PWM3 0x4
238 #define TIMROT_TIMCTRL3_SELECT_PWM4 0x5
239 #define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6
240 #define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7
241 #define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8
242 #define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9
243 #define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa
244 #define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb
245 #define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc
246 #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
247 #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
248 #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff
249 #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0
252 #define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
253 #define TIMROT_VERSION_MAJOR_OFFSET 24
254 #define TIMROT_VERSION_MINOR_MASK (0xff << 16)
255 #define TIMROT_VERSION_MINOR_OFFSET 16
256 #define TIMROT_VERSION_STEP_MASK 0xffff
257 #define TIMROT_VERSION_STEP_OFFSET 0
259 #endif /* __MX28_REGS_TIMROT_H__ */
projects / people / ms / u-boot.git / blob