arch/arm/include/asm/arch-nomadik/mtu.h

   1 /*
   2  * (C) Copyright 2009 Alessandro Rubini
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __ASM_ARCH_MTU_H
  24 #define __ASM_ARCH_MTU_H
  25
  26 /*
  27  * The MTU device hosts four different counters, with 4 set of
  28  * registers. These are register names.
  29  */
  30
  31 #define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  32 #define MTU_RIS         0x04    /* Raw interrupt status */
  33 #define MTU_MIS         0x08    /* Masked interrupt status */
  34 #define MTU_ICR         0x0C    /* Interrupt clear register */
  35
  36 /* per-timer registers take 0..3 as argument */
  37 #define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  38 #define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  39 #define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  40 #define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  41
  42 /* bits for the control register */
  43 #define MTU_CRn_ENA             0x80
  44 #define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  45 #define MTU_CRn_PRESCALE_MASK   0x0c
  46 #define MTU_CRn_PRESCALE_1              0x00
  47 #define MTU_CRn_PRESCALE_16             0x04
  48 #define MTU_CRn_PRESCALE_256            0x08
  49 #define MTU_CRn_32BITS          0x02
  50 #define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  51
  52 /* Other registers are usual amba/primecell registers, currently not used */
  53 #define MTU_ITCR        0xff0
  54 #define MTU_ITOP        0xff4
  55
  56 #define MTU_PERIPH_ID0  0xfe0
  57 #define MTU_PERIPH_ID1  0xfe4
  58 #define MTU_PERIPH_ID2  0xfe8
  59 #define MTU_PERIPH_ID3  0xfeC
  60
  61 #define MTU_PCELL0      0xff0
  62 #define MTU_PCELL1      0xff4
  63 #define MTU_PCELL2      0xff8
  64 #define MTU_PCELL3      0xffC
  65
  66 #endif /* __ASM_ARCH_MTU_H */