arch/arm/include/asm/arch-omap3/mem.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _MEM_H_
  26 #define _MEM_H_
  27
  28 #define CS0             0x0
  29 #define CS1             0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
  30
  31 #ifndef __ASSEMBLY__
  32 enum {
  33         STACKED = 0,
  34         IP_DDR = 1,
  35         COMBO_DDR = 2,
  36         IP_SDR = 3,
  37 };
  38 #endif /* __ASSEMBLY__ */
  39
  40 #define EARLY_INIT      1
  41
  42 /* Slower full frequency range default timings for x32 operation*/
  43 #define SDRC_SHARING    0x00000100
  44 #define SDRC_MR_0_SDR   0x00000031
  45
  46 #define DLL_OFFSET              0
  47 #define DLL_WRITEDDRCLKX2DIS    1
  48 #define DLL_ENADLL              1
  49 #define DLL_LOCKDLL             0
  50 #define DLL_DLLPHASE_72         0
  51 #define DLL_DLLPHASE_90         1
  52
  53 /* rkw - need to find of 90/72 degree recommendation for speed like before */
  54 #define SDP_SDRC_DLLAB_CTRL     ((DLL_ENADLL << 3) | \
  55                                 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
  56
  57 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns
  58  *   ACTIMA
  59  *      TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
  60  *      TDPL (Twr) = 15/6       = 2.5 -> 3
  61  *      TRRD = 12/6     = 2
  62  *      TRCD = 18/6     = 3
  63  *      TRP = 18/6      = 3
  64  *      TRAS = 42/6     = 7
  65  *      TRC = 60/6      = 10
  66  *      TRFC = 72/6     = 12
  67  *   ACTIMB
  68  *      TCKE = 2
  69  *      XSR = 120/6 = 20
  70  */
  71 #define INFINEON_TDAL_165       6
  72 #define INFINEON_TDPL_165       3
  73 #define INFINEON_TRRD_165       2
  74 #define INFINEON_TRCD_165       3
  75 #define INFINEON_TRP_165        3
  76 #define INFINEON_TRAS_165       7
  77 #define INFINEON_TRC_165        10
  78 #define INFINEON_TRFC_165       12
  79 #define INFINEON_V_ACTIMA_165   ((INFINEON_TRFC_165 << 27) |            \
  80                 (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) |  \
  81                 (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |  \
  82                 (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) |   \
  83                 (INFINEON_TDAL_165))
  84
  85 #define INFINEON_TWTR_165       1
  86 #define INFINEON_TCKE_165       2
  87 #define INFINEON_TXP_165        2
  88 #define INFINEON_XSR_165        20
  89 #define INFINEON_V_ACTIMB_165   ((INFINEON_TCKE_165 << 12) |            \
  90                 (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) |     \
  91                 (INFINEON_TWTR_165 << 16))
  92
  93 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns
  94  * ACTIMA
  95  *      TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
  96  *      TDPL (Twr)      = 15/6  = 2.5 -> 3
  97  *      TRRD            = 12/6  = 2
  98  *      TRCD            = 18/6  = 3
  99  *      TRP             = 18/6  = 3
 100  *      TRAS            = 42/6  = 7
 101  *      TRC             = 60/6  = 10
 102  *      TRFC            = 125/6 = 21
 103  * ACTIMB
 104  *      TWTR            = 1
 105  *      TCKE            = 1
 106  *      TXSR            = 138/6 = 23
 107  *      TXP             = 25/6  = 4.1 ~5
 108  */
 109 #define MICRON_TDAL_165         6
 110 #define MICRON_TDPL_165         3
 111 #define MICRON_TRRD_165         2
 112 #define MICRON_TRCD_165         3
 113 #define MICRON_TRP_165          3
 114 #define MICRON_TRAS_165         7
 115 #define MICRON_TRC_165          10
 116 #define MICRON_TRFC_165         21
 117 #define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) |                  \
 118                 (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) |      \
 119                 (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |      \
 120                 (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) |       \
 121                 (MICRON_TDAL_165))
 122
 123 #define MICRON_TWTR_165         1
 124 #define MICRON_TCKE_165         1
 125 #define MICRON_XSR_165          23
 126 #define MICRON_TXP_165          5
 127 #define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) |                  \
 128                 (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
 129                 (MICRON_TWTR_165 << 16))
 130
 131 #ifdef CONFIG_OMAP3_INFINEON_DDR
 132 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165
 133 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165
 134 #endif
 135 #ifdef CONFIG_OMAP3_MICRON_DDR
 136 #define V_ACTIMA_165 MICRON_V_ACTIMA_165
 137 #define V_ACTIMB_165 MICRON_V_ACTIMB_165
 138 #endif
 139
 140 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
 141 #error "Please choose the right DDR type in config header"
 142 #endif
 143
 144 /*
 145  * GPMC settings -
 146  * Definitions is as per the following format
 147  * #define <PART>_GPMC_CONFIG<x> <value>
 148  * Where:
 149  * PART is the part name e.g. STNOR - Intel Strata Flash
 150  * x is GPMC config registers from 1 to 6 (there will be 6 macros)
 151  * Value is corresponding value
 152  *
 153  * For every valid PRCM configuration there should be only one definition of
 154  * the same. if values are independent of the board, this definition will be
 155  * present in this file if values are dependent on the board, then this should
 156  * go into corresponding mem-boardName.h file
 157  *
 158  * Currently valid part Names are (PART):
 159  * STNOR - Intel Strata Flash
 160  * SMNAND - Samsung NAND
 161  * MPDB - H4 MPDB board
 162  * SBNOR - Sibley NOR
 163  * MNAND - Micron Large page x16 NAND
 164  * ONNAND - Samsung One NAND
 165  *
 166  * include/configs/file.h contains the defn - for all CS we are interested
 167  * #define OMAP34XX_GPMC_CSx PART
 168  * #define OMAP34XX_GPMC_CSx_SIZE Size
 169  * #define OMAP34XX_GPMC_CSx_MAP Map
 170  * Where:
 171  * x - CS number
 172  * PART - Part Name as defined above
 173  * SIZE - how big is the mapping to be
 174  *   GPMC_SIZE_128M - 0x8
 175  *   GPMC_SIZE_64M  - 0xC
 176  *   GPMC_SIZE_32M  - 0xE
 177  *   GPMC_SIZE_16M  - 0xF
 178  * MAP  - Map this CS to which address(GPMC address space)- Absolute address
 179  *   >>24 before being used.
 180  */
 181 #define GPMC_SIZE_128M  0x8
 182 #define GPMC_SIZE_64M   0xC
 183 #define GPMC_SIZE_32M   0xE
 184 #define GPMC_SIZE_16M   0xF
 185
 186 #define SMNAND_GPMC_CONFIG1     0x00000800
 187 #define SMNAND_GPMC_CONFIG2     0x00141400
 188 #define SMNAND_GPMC_CONFIG3     0x00141400
 189 #define SMNAND_GPMC_CONFIG4     0x0F010F01
 190 #define SMNAND_GPMC_CONFIG5     0x010C1414
 191 #define SMNAND_GPMC_CONFIG6     0x1F0F0A80
 192 #define SMNAND_GPMC_CONFIG7     0x00000C44
 193
 194 #define M_NAND_GPMC_CONFIG1     0x00001800
 195 #define M_NAND_GPMC_CONFIG2     0x00141400
 196 #define M_NAND_GPMC_CONFIG3     0x00141400
 197 #define M_NAND_GPMC_CONFIG4     0x0F010F01
 198 #define M_NAND_GPMC_CONFIG5     0x010C1414
 199 #define M_NAND_GPMC_CONFIG6     0x1f0f0A80
 200 #define M_NAND_GPMC_CONFIG7     0x00000C44
 201
 202 #define STNOR_GPMC_CONFIG1      0x3
 203 #define STNOR_GPMC_CONFIG2      0x00151501
 204 #define STNOR_GPMC_CONFIG3      0x00060602
 205 #define STNOR_GPMC_CONFIG4      0x11091109
 206 #define STNOR_GPMC_CONFIG5      0x01141F1F
 207 #define STNOR_GPMC_CONFIG6      0x000004c4
 208
 209 #define SIBNOR_GPMC_CONFIG1     0x1200
 210 #define SIBNOR_GPMC_CONFIG2     0x001f1f00
 211 #define SIBNOR_GPMC_CONFIG3     0x00080802
 212 #define SIBNOR_GPMC_CONFIG4     0x1C091C09
 213 #define SIBNOR_GPMC_CONFIG5     0x01131F1F
 214 #define SIBNOR_GPMC_CONFIG6     0x1F0F03C2
 215
 216 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
 217 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
 218 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
 219 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
 220 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
 221 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
 222
 223 #define MPDB_GPMC_CONFIG1       0x00011000
 224 #define MPDB_GPMC_CONFIG2       0x001f1f01
 225 #define MPDB_GPMC_CONFIG3       0x00080803
 226 #define MPDB_GPMC_CONFIG4       0x1c0b1c0a
 227 #define MPDB_GPMC_CONFIG5       0x041f1F1F
 228 #define MPDB_GPMC_CONFIG6       0x1F0F04C4
 229
 230 #define P2_GPMC_CONFIG1 0x0
 231 #define P2_GPMC_CONFIG2 0x0
 232 #define P2_GPMC_CONFIG3 0x0
 233 #define P2_GPMC_CONFIG4 0x0
 234 #define P2_GPMC_CONFIG5 0x0
 235 #define P2_GPMC_CONFIG6 0x0
 236
 237 #define ONENAND_GPMC_CONFIG1    0x00001200
 238 #define ONENAND_GPMC_CONFIG2    0x000F0F01
 239 #define ONENAND_GPMC_CONFIG3    0x00030301
 240 #define ONENAND_GPMC_CONFIG4    0x0F040F04
 241 #define ONENAND_GPMC_CONFIG5    0x010F1010
 242 #define ONENAND_GPMC_CONFIG6    0x1F060000
 243
 244 #define NET_GPMC_CONFIG1        0x00001000
 245 #define NET_GPMC_CONFIG2        0x001e1e01
 246 #define NET_GPMC_CONFIG3        0x00080300
 247 #define NET_GPMC_CONFIG4        0x1c091c09
 248 #define NET_GPMC_CONFIG5        0x04181f1f
 249 #define NET_GPMC_CONFIG6        0x00000FCF
 250 #define NET_GPMC_CONFIG7        0x00000f6c
 251
 252 /* max number of GPMC Chip Selects */
 253 #define GPMC_MAX_CS     8
 254 /* max number of GPMC regs */
 255 #define GPMC_MAX_REG    7
 256
 257 #define PISMO1_NOR      1
 258 #define PISMO1_NAND     2
 259 #define PISMO2_CS0      3
 260 #define PISMO2_CS1      4
 261 #define PISMO1_ONENAND  5
 262 #define DBG_MPDB        6
 263 #define PISMO2_NAND_CS0 7
 264 #define PISMO2_NAND_CS1 8
 265
 266 /* make it readable for the gpmc_init */
 267 #define PISMO1_NOR_BASE         FLASH_BASE
 268 #define PISMO1_NAND_BASE        NAND_BASE
 269 #define PISMO2_CS0_BASE         PISMO2_MAP1
 270 #define PISMO1_ONEN_BASE        ONENAND_MAP
 271 #define DBG_MPDB_BASE           DEBUG_BASE
 272
 273 #endif /* endif _MEM_H_ */