arch/arm/include/asm/arch-rockchip/cru_rk3036.h

   1 /*
   2  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_CRU_RK3036_H
   7 #define _ASM_ARCH_CRU_RK3036_H
   8
   9 #include <common.h>
  10
  11 #define OSC_HZ          (24 * 1000 * 1000)
  12
  13 #define APLL_HZ         (600 * 1000000)
  14 #define GPLL_HZ         (594 * 1000000)
  15
  16 #define CORE_PERI_HZ    150000000
  17 #define CORE_ACLK_HZ    300000000
  18
  19 #define CPU_ACLK_HZ     150000000
  20 #define CPU_HCLK_HZ     300000000
  21 #define CPU_PCLK_HZ     300000000
  22
  23 #define PERI_ACLK_HZ    148500000
  24 #define PERI_HCLK_HZ    148500000
  25 #define PERI_PCLK_HZ    74250000
  26
  27 struct rk3036_cru {
  28         struct rk3036_pll {
  29                 unsigned int con0;
  30                 unsigned int con1;
  31                 unsigned int con2;
  32                 unsigned int con3;
  33         } pll[4];
  34         unsigned int cru_mode_con;
  35         unsigned int cru_clksel_con[35];
  36         unsigned int cru_clkgate_con[11];
  37         unsigned int reserved;
  38         unsigned int cru_glb_srst_fst_value;
  39         unsigned int cru_glb_srst_snd_value;
  40         unsigned int reserved1[2];
  41         unsigned int cru_softrst_con[9];
  42         unsigned int cru_misc_con;
  43         unsigned int reserved2[2];
  44         unsigned int cru_glb_cnt_th;
  45         unsigned int cru_sdmmc_con[2];
  46         unsigned int cru_sdio_con[2];
  47         unsigned int cru_emmc_con[2];
  48         unsigned int reserved3;
  49         unsigned int cru_rst_st;
  50         unsigned int reserved4[0x23];
  51         unsigned int cru_pll_mask_con;
  52 };
  53 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
  54
  55 struct pll_div {
  56         u32 refdiv;
  57         u32 fbdiv;
  58         u32 postdiv1;
  59         u32 postdiv2;
  60         u32 frac;
  61 };
  62
  63 enum {
  64         /* PLLCON0*/
  65         PLL_POSTDIV1_MASK       = 7,
  66         PLL_POSTDIV1_SHIFT      = 12,
  67         PLL_FBDIV_MASK          = 0xfff,
  68         PLL_FBDIV_SHIFT         = 0,
  69
  70         /* PLLCON1 */
  71         PLL_DSMPD_MASK          = 1,
  72         PLL_DSMPD_SHIFT         = 12,
  73         PLL_LOCK_STATUS_MASK    = 1,
  74         PLL_LOCK_STATUS_SHIFT   = 10,
  75         PLL_POSTDIV2_MASK       = 7,
  76         PLL_POSTDIV2_SHIFT      = 6,
  77         PLL_REFDIV_MASK         = 0x3f,
  78         PLL_REFDIV_SHIFT        = 0,
  79         PLL_RST_SHIFT           = 14,
  80
  81         /* CRU_MODE */
  82         GPLL_MODE_MASK          = 3,
  83         GPLL_MODE_SHIFT         = 12,
  84         GPLL_MODE_SLOW          = 0,
  85         GPLL_MODE_NORM,
  86         GPLL_MODE_DEEP,
  87         DPLL_MODE_MASK          = 1,
  88         DPLL_MODE_SHIFT         = 4,
  89         DPLL_MODE_SLOW          = 0,
  90         DPLL_MODE_NORM,
  91         APLL_MODE_MASK          = 1,
  92         APLL_MODE_SHIFT         = 0,
  93         APLL_MODE_SLOW          = 0,
  94         APLL_MODE_NORM,
  95
  96         /* CRU_CLK_SEL0_CON */
  97         CPU_CLK_PLL_SEL_MASK    = 3,
  98         CPU_CLK_PLL_SEL_SHIFT   = 14,
  99         CPU_CLK_PLL_SEL_APLL    = 0,
 100         CPU_CLK_PLL_SEL_DPLL,
 101         CPU_CLK_PLL_SEL_GPLL,
 102         ACLK_CPU_DIV_MASK       = 0x1f,
 103         ACLK_CPU_DIV_SHIFT      = 8,
 104         CORE_CLK_PLL_SEL_MASK   = 1,
 105         CORE_CLK_PLL_SEL_SHIFT  = 7,
 106         CORE_CLK_PLL_SEL_APLL   = 0,
 107         CORE_CLK_PLL_SEL_GPLL,
 108         CORE_DIV_CON_MASK       = 0x1f,
 109         CORE_DIV_CON_SHIFT      = 0,
 110
 111         /* CRU_CLK_SEL1_CON */
 112         CPU_PCLK_DIV_MASK       = 7,
 113         CPU_PCLK_DIV_SHIFT      = 12,
 114         CPU_HCLK_DIV_MASK       = 3,
 115         CPU_HCLK_DIV_SHIFT      = 8,
 116         CORE_ACLK_DIV_MASK      = 7,
 117         CORE_ACLK_DIV_SHIFT     = 4,
 118         CORE_PERI_DIV_MASK      = 0xf,
 119         CORE_PERI_DIV_SHIFT     = 0,
 120
 121         /* CRU_CLKSEL10_CON */
 122         PERI_PLL_SEL_MASK       = 3,
 123         PERI_PLL_SEL_SHIFT      = 14,
 124         PERI_PLL_APLL           = 0,
 125         PERI_PLL_DPLL,
 126         PERI_PLL_GPLL,
 127         PERI_PCLK_DIV_MASK      = 3,
 128         PERI_PCLK_DIV_SHIFT     = 12,
 129         PERI_HCLK_DIV_MASK      = 3,
 130         PERI_HCLK_DIV_SHIFT     = 8,
 131         PERI_ACLK_DIV_MASK      = 0x1f,
 132         PERI_ACLK_DIV_SHIFT     = 0,
 133
 134         /* CRU_CLKSEL11_CON */
 135         SDIO_DIV_MASK           = 0x7f,
 136         SDIO_DIV_SHIFT          = 8,
 137         MMC0_DIV_MASK           = 0x7f,
 138         MMC0_DIV_SHIFT          = 0,
 139
 140         /* CRU_CLKSEL12_CON */
 141         EMMC_PLL_MASK           = 3,
 142         EMMC_PLL_SHIFT          = 12,
 143         EMMC_SEL_APLL           = 0,
 144         EMMC_SEL_DPLL,
 145         EMMC_SEL_GPLL,
 146         EMMC_SEL_24M,
 147         SDIO_PLL_MASK           = 3,
 148         SDIO_PLL_SHIFT          = 10,
 149         SDIO_SEL_APLL           = 0,
 150         SDIO_SEL_DPLL,
 151         SDIO_SEL_GPLL,
 152         SDIO_SEL_24M,
 153         MMC0_PLL_MASK           = 3,
 154         MMC0_PLL_SHIFT          = 8,
 155         MMC0_SEL_APLL           = 0,
 156         MMC0_SEL_DPLL,
 157         MMC0_SEL_GPLL,
 158         MMC0_SEL_24M,
 159         EMMC_DIV_MASK           = 0x7f,
 160         EMMC_DIV_SHIFT          = 0,
 161
 162         /* CRU_SOFTRST5_CON */
 163         DDRCTRL_PSRST_SHIFT     = 11,
 164         DDRCTRL_SRST_SHIFT      = 10,
 165         DDRPHY_PSRST_SHIFT      = 9,
 166         DDRPHY_SRST_SHIFT       = 8,
 167 };
 168 #endif