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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/include/asm/arch-rockchip/cru_rk322x.h
2a2f804f675ea1d2c6bebb8dd6f256c989c2cbba
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_CRU_RK322X_H
7 #define _ASM_ARCH_CRU_RK322X_H
12 #define OSC_HZ (24 * MHz)
14 #define APLL_HZ (600 * MHz)
15 #define GPLL_HZ (594 * MHz)
17 #define CORE_PERI_HZ 150000000
18 #define CORE_ACLK_HZ 300000000
20 #define BUS_ACLK_HZ 148500000
21 #define BUS_HCLK_HZ 148500000
22 #define BUS_PCLK_HZ 74250000
24 #define PERI_ACLK_HZ 148500000
25 #define PERI_HCLK_HZ 148500000
26 #define PERI_PCLK_HZ 74250000
28 /* Private data for the clock driver - used by rockchip_get_cru() */
29 struct rk322x_clk_priv
{
30 struct rk322x_cru
*cru
;
40 unsigned int reserved0
[4];
41 unsigned int cru_mode_con
;
42 unsigned int cru_clksel_con
[35];
43 unsigned int cru_clkgate_con
[16];
44 unsigned int cru_softrst_con
[9];
45 unsigned int cru_misc_con
;
46 unsigned int reserved1
[2];
47 unsigned int cru_glb_cnt_th
;
48 unsigned int reserved2
[3];
49 unsigned int cru_glb_rst_st
;
50 unsigned int reserved3
[(0x1c0 - 0x150) / 4 - 1];
51 unsigned int cru_sdmmc_con
[2];
52 unsigned int cru_sdio_con
[2];
53 unsigned int reserved4
[2];
54 unsigned int cru_emmc_con
[2];
55 unsigned int reserved5
[4];
56 unsigned int cru_glb_srst_fst_value
;
57 unsigned int cru_glb_srst_snd_value
;
58 unsigned int cru_pll_mask_con
;
60 check_member(rk322x_cru
, cru_pll_mask_con
, 0x01f8);
73 PLL_POSTDIV1_SHIFT
= 12,
74 PLL_POSTDIV1_MASK
= 7 << PLL_POSTDIV1_SHIFT
,
76 PLL_FBDIV_MASK
= 0xfff,
81 PLL_PD_MASK
= 1 << PLL_PD_SHIFT
,
83 PLL_DSMPD_MASK
= 1 << PLL_DSMPD_SHIFT
,
84 PLL_LOCK_STATUS_SHIFT
= 10,
85 PLL_LOCK_STATUS_MASK
= 1 << PLL_LOCK_STATUS_SHIFT
,
86 PLL_POSTDIV2_SHIFT
= 6,
87 PLL_POSTDIV2_MASK
= 7 << PLL_POSTDIV2_SHIFT
,
89 PLL_REFDIV_MASK
= 0x3f,
93 GPLL_MODE_MASK
= 1 << GPLL_MODE_SHIFT
,
97 CPLL_MODE_MASK
= 1 << CPLL_MODE_SHIFT
,
101 DPLL_MODE_MASK
= 1 << DPLL_MODE_SHIFT
,
105 APLL_MODE_MASK
= 1 << APLL_MODE_SHIFT
,
109 /* CRU_CLK_SEL0_CON */
110 BUS_ACLK_PLL_SEL_SHIFT
= 13,
111 BUS_ACLK_PLL_SEL_MASK
= 3 << BUS_ACLK_PLL_SEL_SHIFT
,
112 BUS_ACLK_PLL_SEL_APLL
= 0,
113 BUS_ACLK_PLL_SEL_GPLL
,
114 BUS_ACLK_PLL_SEL_HDMIPLL
,
115 BUS_ACLK_DIV_SHIFT
= 8,
116 BUS_ACLK_DIV_MASK
= 0x1f << BUS_ACLK_DIV_SHIFT
,
117 CORE_CLK_PLL_SEL_SHIFT
= 6,
118 CORE_CLK_PLL_SEL_MASK
= 3 << CORE_CLK_PLL_SEL_SHIFT
,
119 CORE_CLK_PLL_SEL_APLL
= 0,
120 CORE_CLK_PLL_SEL_GPLL
,
121 CORE_CLK_PLL_SEL_DPLL
,
122 CORE_DIV_CON_SHIFT
= 0,
123 CORE_DIV_CON_MASK
= 0x1f << CORE_DIV_CON_SHIFT
,
125 /* CRU_CLK_SEL1_CON */
126 BUS_PCLK_DIV_SHIFT
= 12,
127 BUS_PCLK_DIV_MASK
= 7 << BUS_PCLK_DIV_SHIFT
,
128 BUS_HCLK_DIV_SHIFT
= 8,
129 BUS_HCLK_DIV_MASK
= 3 << BUS_HCLK_DIV_SHIFT
,
130 CORE_ACLK_DIV_SHIFT
= 4,
131 CORE_ACLK_DIV_MASK
= 7 << CORE_ACLK_DIV_SHIFT
,
132 CORE_PERI_DIV_SHIFT
= 0,
133 CORE_PERI_DIV_MASK
= 0xf << CORE_PERI_DIV_SHIFT
,
135 /* CRU_CLKSEL5_CON */
136 GMAC_OUT_PLL_SHIFT
= 15,
137 GMAC_OUT_PLL_MASK
= 1 << GMAC_OUT_PLL_SHIFT
,
138 GMAC_OUT_DIV_SHIFT
= 8,
139 GMAC_OUT_DIV_MASK
= 0x1f << GMAC_OUT_DIV_SHIFT
,
140 MAC_PLL_SEL_SHIFT
= 7,
141 MAC_PLL_SEL_MASK
= 1 << MAC_PLL_SEL_SHIFT
,
142 RMII_EXTCLK_SLE_SHIFT
= 5,
143 RMII_EXTCLK_SEL_MASK
= 1 << RMII_EXTCLK_SLE_SHIFT
,
144 RMII_EXTCLK_SEL_INT
= 0,
146 CLK_MAC_DIV_SHIFT
= 0,
147 CLK_MAC_DIV_MASK
= 0x1f << CLK_MAC_DIV_SHIFT
,
149 /* CRU_CLKSEL10_CON */
150 PERI_PCLK_DIV_SHIFT
= 12,
151 PERI_PCLK_DIV_MASK
= 7 << PERI_PCLK_DIV_SHIFT
,
152 PERI_PLL_SEL_SHIFT
= 10,
153 PERI_PLL_SEL_MASK
= 3 << PERI_PLL_SEL_SHIFT
,
157 PERI_HCLK_DIV_SHIFT
= 8,
158 PERI_HCLK_DIV_MASK
= 3 << PERI_HCLK_DIV_SHIFT
,
159 PERI_ACLK_DIV_SHIFT
= 0,
160 PERI_ACLK_DIV_MASK
= 0x1f << PERI_ACLK_DIV_SHIFT
,
162 /* CRU_CLKSEL11_CON */
164 EMMC_PLL_MASK
= 3 << EMMC_PLL_SHIFT
,
170 SDIO_PLL_MASK
= 3 << SDIO_PLL_SHIFT
,
176 MMC0_PLL_MASK
= 3 << MMC0_PLL_SHIFT
,
182 MMC0_DIV_MASK
= 0xff << MMC0_DIV_SHIFT
,
184 /* CRU_CLKSEL12_CON */
186 EMMC_DIV_MASK
= 0xff << EMMC_DIV_SHIFT
,
188 SDIO_DIV_MASK
= 0xff << SDIO_DIV_SHIFT
,
190 /* CRU_CLKSEL26_CON */
191 DDR_CLK_PLL_SEL_SHIFT
= 8,
192 DDR_CLK_PLL_SEL_MASK
= 3 << DDR_CLK_PLL_SEL_SHIFT
,
193 DDR_CLK_SEL_DPLL
= 0,
196 DDR_DIV_SEL_SHIFT
= 0,
197 DDR_DIV_SEL_MASK
= 3 << DDR_DIV_SEL_SHIFT
,
199 /* CRU_CLKSEL27_CON */
200 VOP_DCLK_DIV_SHIFT
= 8,
201 VOP_DCLK_DIV_MASK
= 0xff << VOP_DCLK_DIV_SHIFT
,
202 VOP_PLL_SEL_SHIFT
= 1,
203 VOP_PLL_SEL_MASK
= 1 << VOP_PLL_SEL_SHIFT
,
205 /* CRU_CLKSEL29_CON */
206 GMAC_CLK_SRC_SHIFT
= 12,
207 GMAC_CLK_SRC_MASK
= 1 << GMAC_CLK_SRC_SHIFT
,
209 /* CRU_SOFTRST5_CON */
210 DDRCTRL_PSRST_SHIFT
= 11,
211 DDRCTRL_SRST_SHIFT
= 10,
212 DDRPHY_PSRST_SHIFT
= 9,
213 DDRPHY_SRST_SHIFT
= 8,