arch/arm/include/asm/arch-rockchip/ddr_rk3368.h

   1 /*
   2  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef __ASM_ARCH_DDR_RK3368_H__
   8 #define __ASM_ARCH_DDR_RK3368_H__
   9
  10 /*
  11  * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
  12  * in a few details. Most notably, it has an additional field to track
  13  * tREFI in controller cycles (i.e. trefi_mem_ddr3).
  14  */
  15 struct rk3368_ddr_pctl {
  16         u32 scfg;
  17         u32 sctl;
  18         u32 stat;
  19         u32 intrstat;
  20         u32 reserved0[12];
  21         u32 mcmd;
  22         u32 powctl;
  23         u32 powstat;
  24         u32 cmdtstat;
  25         u32 cmdtstaten;
  26         u32 reserved1[3];
  27         u32 mrrcfg0;
  28         u32 mrrstat0;
  29         u32 mrrstat1;
  30         u32 reserved2[4];
  31         u32 mcfg1;
  32         u32 mcfg;
  33         u32 ppcfg;
  34         u32 mstat;
  35         u32 lpddr2zqcfg;
  36         u32 reserved3;
  37         u32 dtupdes;
  38         u32 dtuna;
  39         u32 dtune;
  40         u32 dtuprd0;
  41         u32 dtuprd1;
  42         u32 dtuprd2;
  43         u32 dtuprd3;
  44         u32 dtuawdt;
  45         u32 reserved4[3];
  46         u32 togcnt1u;
  47         u32 tinit;
  48         u32 trsth;
  49         u32 togcnt100n;
  50         u32 trefi;
  51         u32 tmrd;
  52         u32 trfc;
  53         u32 trp;
  54         u32 trtw;
  55         u32 tal;
  56         u32 tcl;
  57         u32 tcwl;
  58         u32 tras;
  59         u32 trc;
  60         u32 trcd;
  61         u32 trrd;
  62         u32 trtp;
  63         u32 twr;
  64         u32 twtr;
  65         u32 texsr;
  66         u32 txp;
  67         u32 txpdll;
  68         u32 tzqcs;
  69         u32 tzqcsi;
  70         u32 tdqs;
  71         u32 tcksre;
  72         u32 tcksrx;
  73         u32 tcke;
  74         u32 tmod;
  75         u32 trstl;
  76         u32 tzqcl;
  77         u32 tmrr;
  78         u32 tckesr;
  79         u32 tdpd;
  80         u32 trefi_mem_ddr3;
  81         u32 reserved5[45];
  82         u32 dtuwactl;
  83         u32 dturactl;
  84         u32 dtucfg;
  85         u32 dtuectl;
  86         u32 dtuwd0;
  87         u32 dtuwd1;
  88         u32 dtuwd2;
  89         u32 dtuwd3;
  90         u32 dtuwdm;
  91         u32 dturd0;
  92         u32 dturd1;
  93         u32 dturd2;
  94         u32 dturd3;
  95         u32 dtulfsrwd;
  96         u32 dtulfsrrd;
  97         u32 dtueaf;
  98         u32 dfitctrldelay;
  99         u32 dfiodtcfg;
 100         u32 dfiodtcfg1;
 101         u32 dfiodtrankmap;
 102         u32 dfitphywrdata;
 103         u32 dfitphywrlat;
 104         u32 reserved7[2];
 105         u32 dfitrddataen;
 106         u32 dfitphyrdlat;
 107         u32 reserved8[2];
 108         u32 dfitphyupdtype0;
 109         u32 dfitphyupdtype1;
 110         u32 dfitphyupdtype2;
 111         u32 dfitphyupdtype3;
 112         u32 dfitctrlupdmin;
 113         u32 dfitctrlupdmax;
 114         u32 dfitctrlupddly;
 115         u32 reserved9;
 116         u32 dfiupdcfg;
 117         u32 dfitrefmski;
 118         u32 dfitctrlupdi;
 119         u32 reserved10[4];
 120         u32 dfitrcfg0;
 121         u32 dfitrstat0;
 122         u32 dfitrwrlvlen;
 123         u32 dfitrrdlvlen;
 124         u32 dfitrrdlvlgateen;
 125         u32 dfiststat0;
 126         u32 dfistcfg0;
 127         u32 dfistcfg1;
 128         u32 reserved11;
 129         u32 dfitdramclken;
 130         u32 dfitdramclkdis;
 131         u32 dfistcfg2;
 132         u32 dfistparclr;
 133         u32 dfistparlog;
 134         u32 reserved12[3];
 135         u32 dfilpcfg0;
 136         u32 reserved13[3];
 137         u32 dfitrwrlvlresp0;
 138         u32 dfitrwrlvlresp1;
 139         u32 dfitrwrlvlresp2;
 140         u32 dfitrrdlvlresp0;
 141         u32 dfitrrdlvlresp1;
 142         u32 dfitrrdlvlresp2;
 143         u32 dfitrwrlvldelay0;
 144         u32 dfitrwrlvldelay1;
 145         u32 dfitrwrlvldelay2;
 146         u32 dfitrrdlvldelay0;
 147         u32 dfitrrdlvldelay1;
 148         u32 dfitrrdlvldelay2;
 149         u32 dfitrrdlvlgatedelay0;
 150         u32 dfitrrdlvlgatedelay1;
 151         u32 dfitrrdlvlgatedelay2;
 152         u32 dfitrcmd;
 153         u32 reserved14[46];
 154         u32 ipvr;
 155         u32 iptr;
 156 };
 157 check_member(rk3368_ddr_pctl, iptr, 0x03fc);
 158
 159 struct rk3368_ddrphy {
 160         u32 reg[0x100];
 161 };
 162 check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
 163
 164 struct rk3368_msch {
 165         u32 coreid;
 166         u32 revisionid;
 167         u32 ddrconf;
 168         u32 ddrtiming;
 169         u32 ddrmode;
 170         u32 readlatency;
 171         u32 reserved1[8];
 172         u32 activate;
 173         u32 devtodev;
 174 };
 175 check_member(rk3368_msch, devtodev, 0x003c);
 176
 177 /* GRF_SOC_CON0 */
 178 enum {
 179         NOC_RSP_ERR_STALL = BIT(9),
 180         MOBILE_DDR_SEL = BIT(4),
 181         DDR0_16BIT_EN = BIT(3),
 182         MSCH0_MAINDDR3_DDR3 = BIT(2),
 183         MSCH0_MAINPARTIALPOP = BIT(1),
 184         UPCTL_C_ACTIVE = BIT(0),
 185 };
 186
 187 #endif