arch/arm/include/asm/arch-rockchip/grf_rk3128.h

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_GRF_RK3128_H
   7 #define _ASM_ARCH_GRF_RK3128_H
   8
   9 #include <common.h>
  10
  11 struct rk3128_grf {
  12         unsigned int reserved[0x2a];
  13         unsigned int gpio0a_iomux;
  14         unsigned int gpio0b_iomux;
  15         unsigned int gpio0c_iomux;
  16         unsigned int gpio0d_iomux;
  17         unsigned int gpio1a_iomux;
  18         unsigned int gpio1b_iomux;
  19         unsigned int gpio1c_iomux;
  20         unsigned int gpio1d_iomux;
  21         unsigned int gpio2a_iomux;
  22         unsigned int gpio2b_iomux;
  23         unsigned int gpio2c_iomux;
  24         unsigned int gpio2d_iomux;
  25         unsigned int gpio3a_iomux;
  26         unsigned int gpio3b_iomux;
  27         unsigned int gpio3c_iomux;
  28         unsigned int gpio3d_iomux;
  29         unsigned int gpio2c_iomux2;
  30         unsigned int grf_cif_iomux;
  31         unsigned int grf_cif_iomux1;
  32         unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
  33         unsigned int gpio0l_pull;
  34         unsigned int gpio0h_pull;
  35         unsigned int gpio1l_pull;
  36         unsigned int gpio1h_pull;
  37         unsigned int gpio2l_pull;
  38         unsigned int gpio2h_pull;
  39         unsigned int gpio3l_pull;
  40         unsigned int gpio3h_pull;
  41         unsigned int reserved2;
  42         unsigned int soc_con0;
  43         unsigned int soc_con1;
  44         unsigned int soc_con2;
  45         unsigned int soc_status0;
  46         unsigned int reserved3[6];
  47         unsigned int mac_con0;
  48         unsigned int mac_con1;
  49         unsigned int reserved4[4];
  50         unsigned int uoc0_con0;
  51         unsigned int reserved5;
  52         unsigned int uoc1_con1;
  53         unsigned int uoc1_con2;
  54         unsigned int uoc1_con3;
  55         unsigned int uoc1_con4;
  56         unsigned int uoc1_con5;
  57         unsigned int reserved6;
  58         unsigned int ddrc_stat;
  59         unsigned int reserved9;
  60         unsigned int soc_status1;
  61         unsigned int cpu_con0;
  62         unsigned int cpu_con1;
  63         unsigned int cpu_con2;
  64         unsigned int cpu_con3;
  65         unsigned int reserved10;
  66         unsigned int reserved11;
  67         unsigned int cpu_status0;
  68         unsigned int cpu_status1;
  69         unsigned int os_reg[8];
  70         unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
  71         unsigned int usbphy0_con[8];
  72         unsigned int usbphy1_con[8];
  73         unsigned int uoc_status0;
  74         unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
  75         unsigned int chip_tag;
  76         unsigned int sdmmc_det_cnt;
  77 };
  78 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
  79
  80 struct rk3128_pmu {
  81         unsigned int wakeup_cfg;
  82         unsigned int pwrdn_con;
  83         unsigned int pwrdn_st;
  84         unsigned int idle_req;
  85         unsigned int idle_st;
  86         unsigned int pwrmode_con;
  87         unsigned int pwr_state;
  88         unsigned int osc_cnt;
  89         unsigned int core_pwrdwn_cnt;
  90         unsigned int core_pwrup_cnt;
  91         unsigned int sft_con;
  92         unsigned int ddr_sref_st;
  93         unsigned int int_con;
  94         unsigned int int_st;
  95         unsigned int sys_reg[4];
  96 };
  97 check_member(rk3128_pmu, int_st, 0x34);
  98
  99 /* GRF_GPIO0A_IOMUX */
 100 enum {
 101         GPIO0A7_SHIFT           = 14,
 102         GPIO0A7_MASK            = 3 << GPIO0A7_SHIFT,
 103         GPIO0A7_GPIO            = 0,
 104         GPIO0A7_I2C3_SDA,
 105
 106         GPIO0A6_SHIFT           = 12,
 107         GPIO0A6_MASK            = 3 << GPIO0A6_SHIFT,
 108         GPIO0A6_GPIO            = 0,
 109         GPIO0A6_I2C3_SCL,
 110
 111         GPIO0A3_SHIFT           = 6,
 112         GPIO0A3_MASK            = 3 << GPIO0A3_SHIFT,
 113         GPIO0A3_GPIO            = 0,
 114         GPIO0A3_I2C1_SDA,
 115
 116         GPIO0A2_SHIFT           = 4,
 117         GPIO0A2_MASK            = 1 << GPIO0A2_SHIFT,
 118         GPIO0A2_GPIO            = 0,
 119         GPIO0A2_I2C1_SCL,
 120
 121         GPIO0A1_SHIFT           = 2,
 122         GPIO0A1_MASK            = 1 << GPIO0A1_SHIFT,
 123         GPIO0A1_GPIO            = 0,
 124         GPIO0A1_I2C0_SDA,
 125
 126         GPIO0A0_SHIFT           = 0,
 127         GPIO0A0_MASK            = 1 << GPIO0A0_SHIFT,
 128         GPIO0A0_GPIO            = 0,
 129         GPIO0A0_I2C0_SCL,
 130 };
 131
 132 /* GRF_GPIO0B_IOMUX */
 133 enum {
 134         GPIO0B6_SHIFT           = 12,
 135         GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
 136         GPIO0B6_GPIO            = 0,
 137         GPIO0B6_I2S_SDI,
 138         GPIO0B6_SPI_CSN0,
 139
 140         GPIO0B5_SHIFT           = 10,
 141         GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
 142         GPIO0B5_GPIO            = 0,
 143         GPIO0B5_I2S_SDO,
 144         GPIO0B5_SPI_RXD,
 145
 146         GPIO0B4_SHIFT           = 8,
 147         GPIO0B4_MASK            = 1 << GPIO0B4_SHIFT,
 148         GPIO0B4_GPIO            = 0,
 149         GPIO0B4_I2S_LRCKTX,
 150
 151         GPIO0B3_SHIFT           = 6,
 152         GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
 153         GPIO0B3_GPIO            = 0,
 154         GPIO0B3_I2S_LRCKRX,
 155         GPIO0B3_SPI_TXD,
 156
 157         GPIO0B1_SHIFT           = 2,
 158         GPIO0B1_MASK            = 3,
 159         GPIO0B1_GPIO            = 0,
 160         GPIO0B1_I2S_SCLK,
 161         GPIO0B1_SPI_CLK,
 162
 163         GPIO0B0_SHIFT           = 0,
 164         GPIO0B0_MASK            = 3,
 165         GPIO0B0_GPIO            = 0,
 166         GPIO0B0_I2S1_MCLK,
 167 };
 168
 169 /* GRF_GPIO0D_IOMUX */
 170 enum {
 171         GPIO0D4_SHIFT           = 8,
 172         GPIO0D4_MASK            = 1 << GPIO0D4_SHIFT,
 173         GPIO0D4_GPIO            = 0,
 174         GPIO0D4_PWM2,
 175
 176         GPIO0D3_SHIFT           = 6,
 177         GPIO0D3_MASK            = 1 << GPIO0D3_SHIFT,
 178         GPIO0D3_GPIO            = 0,
 179         GPIO0D3_PWM1,
 180
 181         GPIO0D2_SHIFT           = 4,
 182         GPIO0D2_MASK            = 1 << GPIO0D2_SHIFT,
 183         GPIO0D2_GPIO            = 0,
 184         GPIO0D2_PWM0,
 185
 186         GPIO0D1_SHIFT           = 2,
 187         GPIO0D1_MASK            = 1 << GPIO0D1_SHIFT,
 188         GPIO0D1_GPIO            = 0,
 189         GPIO0D1_UART2_CTSN,
 190
 191         GPIO0D0_SHIFT           = 0,
 192         GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
 193         GPIO0D0_GPIO            = 0,
 194         GPIO0D0_UART2_RTSN,
 195         GPIO0D0_PMIC_SLEEP,
 196 };
 197
 198 /* GRF_GPIO1A_IOMUX */
 199 enum {
 200         GPIO1A5_SHIFT           = 10,
 201         GPIO1A5_MASK            = 3 << GPIO1A5_SHIFT,
 202         GPIO1A5_GPIO            = 0,
 203         GPIO1A5_I2S_SDI,
 204         GPIO1A5_SDMMC_DATA3,
 205
 206         GPIO1A4_SHIFT           = 8,
 207         GPIO1A4_MASK            = 3 << GPIO1A4_SHIFT,
 208         GPIO1A4_GPIO            = 0,
 209         GPIO1A4_I2S_SD0,
 210         GPIO1A4_SDMMC_DATA2,
 211
 212         GPIO1A3_SHIFT           = 6,
 213         GPIO1A3_MASK            = 1 << GPIO1A3_SHIFT,
 214         GPIO1A3_GPIO            = 0,
 215         GPIO1A3_I2S_LRCKTX,
 216
 217         GPIO1A2_SHIFT           = 4,
 218         GPIO1A2_MASK            = 3 << GPIO1A2_SHIFT,
 219         GPIO1A2_GPIO            = 0,
 220         GPIO1A2_I2S_LRCKRX,
 221         GPIO1A2_SDMMC_DATA1,
 222
 223         GPIO1A1_SHIFT           = 2,
 224         GPIO1A1_MASK            = 3 << GPIO1A1_SHIFT,
 225         GPIO1A1_GPIO            = 0,
 226         GPIO1A1_I2S_SCLK,
 227         GPIO1A1_SDMMC_DATA0,
 228         GPIO1A1_PMIC_SLEEP,
 229
 230         GPIO1A0_SHIFT           = 0,
 231         GPIO1A0_MASK            = 3,
 232         GPIO1A0_GPIO            = 0,
 233         GPIO1A0_I2S_MCLK,
 234         GPIO1A0_SDMMC_CLKOUT,
 235         GPIO1A0_XIN32K,
 236
 237 };
 238
 239 /* GRF_GPIO1B_IOMUX */
 240 enum {
 241         GPIO1B7_SHIFT           = 14,
 242         GPIO1B7_MASK            = 1 << GPIO1B7_SHIFT,
 243         GPIO1B7_GPIO            = 0,
 244         GPIO1B7_MMC0_CMD,
 245
 246         GPIO1B6_SHIFT           = 12,
 247         GPIO1B6_MASK            = 1 << GPIO1B6_SHIFT,
 248         GPIO1B6_GPIO            = 0,
 249         GPIO1B6_MMC_PWREN,
 250
 251         GPIO1B2_SHIFT           = 4,
 252         GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
 253         GPIO1B2_GPIO            = 0,
 254         GPIO1B2_SPI_RXD,
 255         GPIO1B2_UART1_SIN,
 256
 257         GPIO1B1_SHIFT           = 2,
 258         GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
 259         GPIO1B1_GPIO            = 0,
 260         GPIO1B1_SPI_TXD,
 261         GPIO1B1_UART1_SOUT,
 262
 263         GPIO1B0_SHIFT           = 0,
 264         GPIO1B0_MASK            = 3 << GPIO1B0_SHIFT,
 265         GPIO1B0_GPIO            = 0,
 266         GPIO1B0_SPI_CLK,
 267         GPIO1B0_UART1_CTSN
 268 };
 269
 270 /* GRF_GPIO1C_IOMUX */
 271 enum {
 272         GPIO1C6_SHIFT           = 12,
 273         GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
 274         GPIO1C6_GPIO            = 0,
 275         GPIO1C6_NAND_CS2,
 276         GPIO1C6_EMMC_CMD,
 277
 278         GPIO1C5_SHIFT           = 10,
 279         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
 280         GPIO1C5_GPIO            = 0,
 281         GPIO1C5_MMC0_D3,
 282         GPIO1C5_JTAG_TMS,
 283
 284         GPIO1C4_SHIFT           = 8,
 285         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 286         GPIO1C4_GPIO            = 0,
 287         GPIO1C4_MMC0_D2,
 288         GPIO1C4_JTAG_TCK,
 289
 290         GPIO1C3_SHIFT           = 6,
 291         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 292         GPIO1C3_GPIO            = 0,
 293         GPIO1C3_MMC0_D1,
 294         GPIO1C3_UART2_RX,
 295
 296         GPIO1C2_SHIFT           = 4,
 297         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
 298         GPIO1C2_GPIO            = 0,
 299         GPIO1C2_MMC0_D0,
 300         GPIO1C2_UART2_TX,
 301
 302         GPIO1C1_SHIFT           = 2,
 303         GPIO1C1_MASK            = 1 << GPIO1C1_SHIFT,
 304         GPIO1C1_GPIO            = 0,
 305         GPIO1C1_MMC0_DETN,
 306
 307         GPIO1C0_SHIFT           = 0,
 308         GPIO1C0_MASK            = 1 << GPIO1C0_SHIFT,
 309         GPIO1C0_GPIO            = 0,
 310         GPIO1C0_MMC0_CLKOUT,
 311 };
 312
 313 /* GRF_GPIO1D_IOMUX */
 314 enum {
 315         GPIO1D7_SHIFT           = 14,
 316         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 317         GPIO1D7_GPIO            = 0,
 318         GPIO1D7_NAND_D7,
 319         GPIO1D7_EMMC_D7,
 320         GPIO1D7_SPI_CSN1,
 321
 322         GPIO1D6_SHIFT           = 12,
 323         GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
 324         GPIO1D6_GPIO            = 0,
 325         GPIO1D6_NAND_D6,
 326         GPIO1D6_EMMC_D6,
 327         GPIO1D6_SPI_CSN0,
 328
 329         GPIO1D5_SHIFT           = 10,
 330         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 331         GPIO1D5_GPIO            = 0,
 332         GPIO1D5_NAND_D5,
 333         GPIO1D5_EMMC_D5,
 334         GPIO1D5_SPI_TXD1,
 335
 336         GPIO1D4_SHIFT           = 8,
 337         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 338         GPIO1D4_GPIO            = 0,
 339         GPIO1D4_NAND_D4,
 340         GPIO1D4_EMMC_D4,
 341         GPIO1D4_SPI_RXD1,
 342
 343         GPIO1D3_SHIFT           = 6,
 344         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 345         GPIO1D3_GPIO            = 0,
 346         GPIO1D3_NAND_D3,
 347         GPIO1D3_EMMC_D3,
 348         GPIO1D3_SFC_SIO3,
 349
 350         GPIO1D2_SHIFT           = 4,
 351         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 352         GPIO1D2_GPIO            = 0,
 353         GPIO1D2_NAND_D2,
 354         GPIO1D2_EMMC_D2,
 355         GPIO1D2_SFC_SIO2,
 356
 357         GPIO1D1_SHIFT           = 2,
 358         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 359         GPIO1D1_GPIO            = 0,
 360         GPIO1D1_NAND_D1,
 361         GPIO1D1_EMMC_D1,
 362         GPIO1D1_SFC_SIO1,
 363
 364         GPIO1D0_SHIFT           = 0,
 365         GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
 366         GPIO1D0_GPIO            = 0,
 367         GPIO1D0_NAND_D0,
 368         GPIO1D0_EMMC_D0,
 369         GPIO1D0_SFC_SIO0,
 370 };
 371
 372 /* GRF_GPIO2A_IOMUX */
 373 enum {
 374         GPIO2A7_SHIFT           = 14,
 375         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 376         GPIO2A7_GPIO            = 0,
 377         GPIO2A7_NAND_DQS,
 378         GPIO2A7_EMMC_CLKOUT,
 379
 380         GPIO2A6_SHIFT           = 12,
 381         GPIO2A6_MASK            = 1 << GPIO2A6_SHIFT,
 382         GPIO2A6_GPIO            = 0,
 383         GPIO2A6_NAND_CS0,
 384
 385         GPIO2A5_SHIFT           = 10,
 386         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 387         GPIO2A5_GPIO            = 0,
 388         GPIO2A5_NAND_WP,
 389         GPIO2A5_EMMC_PWREN,
 390
 391         GPIO2A4_SHIFT           = 8,
 392         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 393         GPIO2A4_GPIO            = 0,
 394         GPIO2A4_NAND_RDY,
 395         GPIO2A4_EMMC_CMD,
 396         GPIO2A3_SFC_CLK,
 397
 398         GPIO2A3_SHIFT           = 6,
 399         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 400         GPIO2A3_GPIO            = 0,
 401         GPIO2A3_NAND_RDN,
 402         GPIO2A4_SFC_CSN1,
 403
 404         GPIO2A2_SHIFT           = 4,
 405         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 406         GPIO2A2_GPIO            = 0,
 407         GPIO2A2_NAND_WRN,
 408         GPIO2A4_SFC_CSN0,
 409
 410         GPIO2A1_SHIFT           = 2,
 411         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 412         GPIO2A1_GPIO            = 0,
 413         GPIO2A1_NAND_CLE,
 414         GPIO2A1_EMMC_CLKOUT,
 415
 416         GPIO2A0_SHIFT           = 0,
 417         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 418         GPIO2A0_GPIO            = 0,
 419         GPIO2A0_NAND_ALE,
 420         GPIO2A0_SPI_CLK,
 421 };
 422
 423 /* GRF_GPIO2B_IOMUX */
 424 enum {
 425         GPIO2B7_SHIFT           = 14,
 426         GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
 427         GPIO2B7_GPIO            = 0,
 428         GPIO2B7_LCDC0_D13,
 429         GPIO2B7_EBC_SDCE5,
 430         GPIO2B7_GMAC_RXER,
 431
 432         GPIO2B6_SHIFT           = 12,
 433         GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
 434         GPIO2B6_GPIO            = 0,
 435         GPIO2B6_LCDC0_D12,
 436         GPIO2B6_EBC_SDCE4,
 437         GPIO2B6_GMAC_CLK,
 438
 439         GPIO2B5_SHIFT           = 10,
 440         GPIO2B5_MASK            = 3 << GPIO2B5_SHIFT,
 441         GPIO2B5_GPIO            = 0,
 442         GPIO2B5_LCDC0_D11,
 443         GPIO2B5_EBC_SDCE3,
 444         GPIO2B5_GMAC_TXEN,
 445
 446         GPIO2B4_SHIFT           = 8,
 447         GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
 448         GPIO2B4_GPIO            = 0,
 449         GPIO2B4_LCDC0_D10,
 450         GPIO2B4_EBC_SDCE2,
 451         GPIO2B4_GMAC_MDIO,
 452
 453         GPIO2B3_SHIFT           = 6,
 454         GPIO2B3_MASK            = 3 << GPIO2B3_SHIFT,
 455         GPIO2B3_GPIO            = 0,
 456         GPIO2B3_LCDC0_DEN,
 457         GPIO2B3_EBC_GDCLK,
 458         GPIO2B3_GMAC_RXCLK,
 459
 460         GPIO2B2_SHIFT           = 4,
 461         GPIO2B2_MASK            = 3 << GPIO2B2_SHIFT,
 462         GPIO2B2_GPIO            = 0,
 463         GPIO2B2_LCDC0_VSYNC,
 464         GPIO2B2_EBC_SDOE,
 465         GPIO2B2_GMAC_CRS,
 466
 467         GPIO2B1_SHIFT           = 2,
 468         GPIO2B1_MASK            = 3 << GPIO2B1_SHIFT,
 469         GPIO2B1_GPIO            = 0,
 470         GPIO2B1_LCDC0_HSYNC,
 471         GPIO2B1_EBC_SDLE,
 472         GPIO2B1_GMAC_TXCLK,
 473
 474         GPIO2B0_SHIFT           = 0,
 475         GPIO2B0_MASK            = 3 << GPIO2B0_SHIFT,
 476         GPIO2B0_GPIO            = 0,
 477         GPIO2B0_LCDC0_DCLK,
 478         GPIO2B0_EBC_SDCLK,
 479         GPIO2B0_GMAC_RXDV,
 480 };
 481
 482 /* GRF_GPIO2C_IOMUX */
 483 enum {
 484         GPIO2C3_SHIFT           = 6,
 485         GPIO2C3_MASK            = 3 << GPIO2C3_SHIFT,
 486         GPIO2C3_GPIO            = 0,
 487         GPIO2C3_LCDC0_D17,
 488         GPIO2C3_EBC_GDPWR0,
 489         GPIO2C3_GMAC_TXD0,
 490
 491         GPIO2C2_SHIFT           = 4,
 492         GPIO2C2_MASK            = 3 << GPIO2C2_SHIFT,
 493         GPIO2C2_GPIO            = 0,
 494         GPIO2C2_LCDC0_D16,
 495         GPIO2C2_EBC_GDSP,
 496         GPIO2C2_GMAC_TXD1,
 497
 498         GPIO2C1_SHIFT           = 2,
 499         GPIO2C1_MASK            = 3 << GPIO2C1_SHIFT,
 500         GPIO2C1_GPIO            = 0,
 501         GPIO2C1_LCDC0_D15,
 502         GPIO2C1_EBC_GDOE,
 503         GPIO2C1_GMAC_RXD0,
 504
 505         GPIO2C0_SHIFT           = 0,
 506         GPIO2C0_MASK            = 3 << GPIO2C0_SHIFT,
 507         GPIO2C0_GPIO            = 0,
 508         GPIO2C0_LCDC0_D14,
 509         GPIO2C0_EBC_VCOM,
 510         GPIO2C0_GMAC_RXD1,
 511 };
 512
 513 /* GRF_GPIO2D_IOMUX */
 514 enum {
 515         GPIO2D6_SHIFT           = 12,
 516         GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
 517         GPIO2D6_GPIO            = 0,
 518         GPIO2D6_LCDC0_D22,
 519         GPIO2D6_GMAC_COL        = 4,
 520
 521         GPIO2D1_SHIFT           = 2,
 522         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 523         GPIO2D1_GPIO            = 0,
 524         GPIO2D1_GMAC_MDC        = 3,
 525 };
 526
 527 /* GRF_GPIO2C_IOMUX2 */
 528 enum {
 529         GPIO2C7_SHIFT           = 12,
 530         GPIO2C7_MASK            = 7 << GPIO2C7_SHIFT,
 531         GPIO2C7_GPIO            = 0,
 532         GPIO2C7_GMAC_TXD3       = 4,
 533
 534         GPIO2C6_SHIFT           = 12,
 535         GPIO2C6_MASK            = 7 << GPIO2C6_SHIFT,
 536         GPIO2C6_GPIO            = 0,
 537         GPIO2C6_GMAC_TXD2       = 4,
 538
 539         GPIO2C5_SHIFT           = 4,
 540         GPIO2C5_MASK            = 7 << GPIO2C5_SHIFT,
 541         GPIO2C5_GPIO            = 0,
 542         GPIO2C5_I2C2_SCL        = 3,
 543         GPIO2C5_GMAC_RXD2,
 544
 545         GPIO2C4_SHIFT           = 0,
 546         GPIO2C4_MASK            = 7 << GPIO2C4_SHIFT,
 547         GPIO2C4_GPIO            = 0,
 548         GPIO2C4_I2C2_SDA        = 3,
 549         GPIO2C4_GMAC_RXD2,
 550 };
 551 #endif