arch/arm/include/asm/arch-stm32f7/rcc.h

   1 /*
   2  * (C) Copyright 2016
   3  * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _STM32_RCC_H
   9 #define _STM32_RCC_H
  10
  11 #define RCC_CR          0x00    /* clock control */
  12 #define RCC_PLLCFGR     0x04    /* PLL configuration */
  13 #define RCC_CFGR        0x08    /* clock configuration */
  14 #define RCC_CIR         0x0C    /* clock interrupt */
  15 #define RCC_AHB1RSTR    0x10    /* AHB1 peripheral reset */
  16 #define RCC_AHB2RSTR    0x14    /* AHB2 peripheral reset */
  17 #define RCC_AHB3RSTR    0x18    /* AHB3 peripheral reset */
  18 #define RCC_APB1RSTR    0x20    /* APB1 peripheral reset */
  19 #define RCC_APB2RSTR    0x24    /* APB2 peripheral reset */
  20 #define RCC_AHB1ENR     0x30    /* AHB1 peripheral clock enable */
  21 #define RCC_AHB2ENR     0x34    /* AHB2 peripheral clock enable */
  22 #define RCC_AHB3ENR     0x38    /* AHB3 peripheral clock enable */
  23 #define RCC_APB1ENR     0x40    /* APB1 peripheral clock enable */
  24 #define RCC_APB2ENR     0x44    /* APB2 peripheral clock enable */
  25 #define RCC_AHB1LPENR   0x50    /* periph clk enable in low pwr mode */
  26 #define RCC_AHB2LPENR   0x54    /* AHB2 periph clk enable in low pwr mode */
  27 #define RCC_AHB3LPENR   0x58    /* AHB3 periph clk enable in low pwr mode */
  28 #define RCC_APB1LPENR   0x60    /* APB1 periph clk enable in low pwr mode */
  29 #define RCC_APB2LPENR   0x64    /* APB2 periph clk enable in low pwr mode */
  30 #define RCC_BDCR        0x70    /* Backup domain control */
  31 #define RCC_CSR         0x74    /* clock control & status */
  32 #define RCC_SSCGR       0x80    /* spread spectrum clock generation */
  33 #define RCC_PLLI2SCFGR  0x84    /* PLLI2S configuration */
  34 #define RCC_PLLSAICFG   0x88    /* PLLSAI configuration */
  35 #define RCC_DCKCFG1     0x8C    /* dedicated clocks configuration register */
  36 #define RCC_DCKCFG2     0x90    /* dedicated clocks configuration register */
  37
  38 #define RCC_APB1ENR_TIM2EN              (1 << 0)
  39 #define RCC_APB1ENR_PWREN               (1 << 28)
  40
  41 /*
  42  * RCC USART specific definitions
  43  */
  44 #define RCC_ENR_USART1EN                (1 << 4)
  45 #define RCC_ENR_USART2EN                (1 << 17)
  46 #define RCC_ENR_USART3EN                (1 << 18)
  47 #define RCC_ENR_USART6EN                (1 <<  5)
  48
  49 /*
  50  * RCC GPIO specific definitions
  51  */
  52 #define RCC_ENR_GPIO_A_EN               (1 << 0)
  53 #define RCC_ENR_GPIO_B_EN               (1 << 1)
  54 #define RCC_ENR_GPIO_C_EN               (1 << 2)
  55 #define RCC_ENR_GPIO_D_EN               (1 << 3)
  56 #define RCC_ENR_GPIO_E_EN               (1 << 4)
  57 #define RCC_ENR_GPIO_F_EN               (1 << 5)
  58 #define RCC_ENR_GPIO_G_EN               (1 << 6)
  59 #define RCC_ENR_GPIO_H_EN               (1 << 7)
  60 #define RCC_ENR_GPIO_I_EN               (1 << 8)
  61 #define RCC_ENR_GPIO_J_EN               (1 << 9)
  62 #define RCC_ENR_GPIO_K_EN               (1 << 10)
  63
  64 #endif