arch/arm/include/asm/arch-sunxi/nand.h

   1 /*
   2  * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _SUNXI_NAND_H
   8 #define _SUNXI_NAND_H
   9
  10 #include <linux/types.h>
  11
  12 struct sunxi_nand
  13 {
  14         u32 ctl;                /* 0x000 Configure and control */
  15         u32 st;                 /* 0x004 Status information */
  16         u32 intr;               /* 0x008 Interrupt control */
  17         u32 timing_ctl;         /* 0x00C Timing control */
  18         u32 timing_cfg;         /* 0x010 Timing configure */
  19         u32 addr_low;           /* 0x014 Low word address */
  20         u32 addr_high;          /* 0x018 High word address */
  21         u32 block_num;          /* 0x01C Data block number */
  22         u32 data_cnt;           /* 0x020 Data counter for transfer */
  23         u32 cmd;                /* 0x024 NDFC commands */
  24         u32 rcmd_set;           /* 0x028 Read command set for vendor NAND mem */
  25         u32 wcmd_set;           /* 0x02C Write command set */
  26         u32 io_data;            /* 0x030 IO data */
  27         u32 ecc_ctl;            /* 0x034 ECC configure and control */
  28         u32 ecc_st;             /* 0x038 ECC status and operation info */
  29         u32 efr;                /* 0x03C Enhanced feature */
  30         u32 err_cnt0;           /* 0x040 Corrected error bit counter 0 */
  31         u32 err_cnt1;           /* 0x044 Corrected error bit counter 1 */
  32         u32 user_data[16];      /* 0x050[16] User data field */
  33         u32 efnand_st;          /* 0x090 EFNAND status */
  34         u32 res0[3];
  35         u32 spare_area;         /* 0x0A0 Spare area configure */
  36         u32 pat_id;             /* 0x0A4 Pattern ID register */
  37         u32 rdata_sta_ctl;      /* 0x0A8 Read data status control */
  38         u32 rdata_sta_0;        /* 0x0AC Read data status 0 */
  39         u32 rdata_sta_1;        /* 0x0B0 Read data status 1 */
  40         u32 res1[3];
  41         u32 mdma_addr;          /* 0x0C0 MBUS DMA Address */
  42         u32 mdma_cnt;           /* 0x0C4 MBUS DMA data counter */
  43 };
  44
  45 #define SUNXI_NAND_CTL_EN                       (1 << 0)
  46 #define SUNXI_NAND_CTL_RST                      (1 << 1)
  47 #define SUNXI_NAND_CTL_PAGE_SIZE(a)             ((fls(a) - 11) << 8)
  48 #define SUNXI_NAND_CTL_RAM_METHOD_DMA           (1 << 14)
  49
  50 #define SUNXI_NAND_ST_CMD_INT                   (1 << 1)
  51 #define SUNXI_NAND_ST_DMA_INT                   (1 << 2)
  52 #define SUNXI_NAND_ST_FIFO_FULL                 (1 << 3)
  53
  54 #define SUNXI_NAND_CMD_ADDR_CYCLES(a)           ((a - 1) << 16);
  55 #define SUNXI_NAND_CMD_SEND_CMD1                (1 << 22)
  56 #define SUNXI_NAND_CMD_WAIT_FLAG                (1 << 23)
  57 #define SUNXI_NAND_CMD_ORDER_INTERLEAVE         0
  58 #define SUNXI_NAND_CMD_ORDER_SEQ                (1 << 25)
  59
  60 #define SUNXI_NAND_ECC_CTL_ECC_EN               (1 << 0)
  61 #define SUNXI_NAND_ECC_CTL_PIPELINE             (1 << 3)
  62 #define SUNXI_NAND_ECC_CTL_BS_512B              (1 << 5)
  63 #define SUNXI_NAND_ECC_CTL_RND_EN               (1 << 9)
  64 #define SUNXI_NAND_ECC_CTL_MODE(a)              ((a) << 12)
  65 #define SUNXI_NAND_ECC_CTL_RND_SEED(a)          ((a) << 16)
  66
  67 #endif /* _SUNXI_NAND_H */