arch/arm/include/asm/arch-tegra/clk_rst.h

   1 /*
   2  *  (C) Copyright 2010,2011
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA_CLK_RST_H_
   9 #define _TEGRA_CLK_RST_H_
  10
  11 /* PLL registers - there are several PLLs in the clock controller */
  12 struct clk_pll {
  13         uint pll_base;          /* the control register */
  14         uint pll_out[2];        /* output control */
  15         uint pll_misc;          /* other misc things */
  16 };
  17
  18 /* PLL registers - there are several PLLs in the clock controller */
  19 struct clk_pll_simple {
  20         uint pll_base;          /* the control register */
  21         uint pll_misc;          /* other misc things */
  22 };
  23
  24 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
  25 struct clk_set_clr {
  26         uint set;
  27         uint clr;
  28 };
  29
  30 /*
  31  * Most PLLs use the clk_pll structure, but some have a simpler two-member
  32  * structure for which we use clk_pll_simple. The reason for this non-
  33  * othogonal setup is not stated.
  34  */
  35 enum {
  36         TEGRA_CLK_PLLS          = 6,    /* Number of normal PLLs */
  37         TEGRA_CLK_SIMPLE_PLLS   = 3,    /* Number of simple PLLs */
  38         TEGRA_CLK_REGS          = 3,    /* Number of clock enable regs L/H/U */
  39         TEGRA_CLK_SOURCES       = 64,   /* Number of ppl clock sources L/H/U */
  40         TEGRA_CLK_REGS_VW       = 2,    /* Number of clock enable regs V/W */
  41         TEGRA_CLK_SOURCES_VW    = 32,   /* Number of ppl clock sources V/W*/
  42 };
  43
  44 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
  45 struct clk_rst_ctlr {
  46         uint crc_rst_src;                       /* _RST_SOURCE_0,0x00 */
  47         uint crc_rst_dev[TEGRA_CLK_REGS];       /* _RST_DEVICES_L/H/U_0 */
  48         uint crc_clk_out_enb[TEGRA_CLK_REGS];   /* _CLK_OUT_ENB_L/H/U_0 */
  49         uint crc_reserved0;             /* reserved_0,          0x1C */
  50         uint crc_cclk_brst_pol;         /* _CCLK_BURST_POLICY_0,0x20 */
  51         uint crc_super_cclk_div;        /* _SUPER_CCLK_DIVIDER_0,0x24 */
  52         uint crc_sclk_brst_pol;         /* _SCLK_BURST_POLICY_0, 0x28 */
  53         uint crc_super_sclk_div;        /* _SUPER_SCLK_DIVIDER_0,0x2C */
  54         uint crc_clk_sys_rate;          /* _CLK_SYSTEM_RATE_0,  0x30 */
  55         uint crc_prog_dly_clk;          /* _PROG_DLY_CLK_0,     0x34 */
  56         uint crc_aud_sync_clk_rate;     /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
  57         uint crc_reserved1;             /* reserved_1,          0x3C */
  58         uint crc_cop_clk_skip_plcy;     /* _COP_CLK_SKIP_POLICY_0,0x40 */
  59         uint crc_clk_mask_arm;          /* _CLK_MASK_ARM_0,     0x44 */
  60         uint crc_misc_clk_enb;          /* _MISC_CLK_ENB_0,     0x48 */
  61         uint crc_clk_cpu_cmplx;         /* _CLK_CPU_CMPLX_0,    0x4C */
  62         uint crc_osc_ctrl;              /* _OSC_CTRL_0,         0x50 */
  63         uint crc_pll_lfsr;              /* _PLL_LFSR_0,         0x54 */
  64         uint crc_osc_freq_det;          /* _OSC_FREQ_DET_0,     0x58 */
  65         uint crc_osc_freq_det_stat;     /* _OSC_FREQ_DET_STATUS_0,0x5C */
  66         uint crc_reserved2[8];          /* reserved_2[8],       0x60-7C */
  67
  68         struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
  69
  70         /* PLLs from 0xe0 to 0xf4    */
  71         struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
  72
  73         uint crc_reserved10;            /* _reserved_10,        0xF8 */
  74         uint crc_reserved11;            /* _reserved_11,        0xFC */
  75
  76         uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...       0x100-1fc */
  77
  78         uint crc_reserved20[64];        /* _reserved_20,        0x200-2fc */
  79
  80         /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
  81         struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
  82
  83         uint crc_reserved30[2];         /* _reserved_30,        0x318, 0x31c */
  84
  85         /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
  86         struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
  87
  88         uint crc_reserved31[2];         /* _reserved_31,        0x338, 0x33c */
  89
  90         uint crc_cpu_cmplx_set;         /* _RST_CPU_CMPLX_SET_0,    0x340 */
  91         uint crc_cpu_cmplx_clr;         /* _RST_CPU_CMPLX_CLR_0,    0x344 */
  92
  93         /* Additional (T30) registers */
  94         uint crc_clk_cpu_cmplx_set;     /* _CLK_CPU_CMPLX_SET_0,    0x348 */
  95         uint crc_clk_cpu_cmplx_clr;     /* _CLK_CPU_CMPLX_SET_0,    0x34c */
  96
  97         uint crc_reserved32[2];         /* _reserved_32,      0x350,0x354 */
  98
  99         uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
 100         uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
 101         uint crc_cclkg_brst_pol;        /* _CCLKG_BURST_POLICY_0,   0x368 */
 102         uint crc_super_cclkg_div;       /* _SUPER_CCLKG_DIVIDER_0,  0x36C */
 103         uint crc_cclklp_brst_pol;       /* _CCLKLP_BURST_POLICY_0,  0x370 */
 104         uint crc_super_cclkp_div;       /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
 105         uint crc_clk_cpug_cmplx;        /* _CLK_CPUG_CMPLX_0,       0x378 */
 106         uint crc_clk_cpulp_cmplx;       /* _CLK_CPULP_CMPLX_0,      0x37C */
 107         uint crc_cpu_softrst_ctrl;      /* _CPU_SOFTRST_CTRL_0,     0x380 */
 108         uint crc_cpu_softrst_ctrl1;     /* _CPU_SOFTRST_CTR1L_0,    0x384 */
 109         uint crc_cpu_softrst_ctrl2;     /* _CPU_SOFTRST_CTRL2_0,    0x388 */
 110         uint crc_reserved33[9];         /* _reserved_33,        0x38c-3ac */
 111         uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
 112         /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
 113         struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 114         /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
 115         struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
 116         /* Additional (T114) registers */
 117         uint crc_rst_cpug_cmplx_set;    /* _RST_CPUG_CMPLX_SET_0,  0x450 */
 118         uint crc_rst_cpug_cmplx_clr;    /* _RST_CPUG_CMPLX_CLR_0,  0x454 */
 119         uint crc_rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0, 0x458 */
 120         uint crc_rst_cpulp_cmplx_clr;   /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
 121         uint crc_clk_cpug_cmplx_set;    /* _CLK_CPUG_CMPLX_SET_0,  0x460 */
 122         uint crc_clk_cpug_cmplx_clr;    /* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
 123         uint crc_clk_cpulp_cmplx_set;   /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
 124         uint crc_clk_cpulp_cmplx_clr;   /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
 125         uint crc_cpu_cmplx_status;      /* _CPU_CMPLX_STATUS_0,    0x470 */
 126         uint crc_reserved40[1];         /* _reserved_40,        0x474 */
 127         uint crc_intstatus;             /* __INTSTATUS_0,       0x478 */
 128         uint crc_intmask;               /* __INTMASK_0,         0x47C */
 129         uint crc_utmip_pll_cfg0;        /* _UTMIP_PLL_CFG0_0,   0x480 */
 130         uint crc_utmip_pll_cfg1;        /* _UTMIP_PLL_CFG1_0,   0x484 */
 131         uint crc_utmip_pll_cfg2;        /* _UTMIP_PLL_CFG2_0,   0x488 */
 132
 133         uint crc_plle_aux;              /* _PLLE_AUX_0,         0x48C */
 134         uint crc_sata_pll_cfg0;         /* _SATA_PLL_CFG0_0,    0x490 */
 135         uint crc_sata_pll_cfg1;         /* _SATA_PLL_CFG1_0,    0x494 */
 136         uint crc_pcie_pll_cfg0;         /* _PCIE_PLL_CFG0_0,    0x498 */
 137
 138         uint crc_prog_audio_dly_clk;    /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
 139         uint crc_audio_sync_clk_i2s0;   /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
 140         uint crc_audio_sync_clk_i2s1;   /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
 141         uint crc_audio_sync_clk_i2s2;   /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
 142         uint crc_audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
 143         uint crc_audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
 144         uint crc_audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
 145 };
 146
 147 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
 148 #define CPU3_CLK_STP_SHIFT      11
 149 #define CPU2_CLK_STP_SHIFT      10
 150 #define CPU1_CLK_STP_SHIFT      9
 151 #define CPU0_CLK_STP_SHIFT      8
 152 #define CPU0_CLK_STP_MASK       (1U << CPU0_CLK_STP_SHIFT)
 153
 154 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */
 155 #define PLL_BYPASS_SHIFT        31
 156 #define PLL_BYPASS_MASK         (1U << PLL_BYPASS_SHIFT)
 157
 158 #define PLL_ENABLE_SHIFT        30
 159 #define PLL_ENABLE_MASK         (1U << PLL_ENABLE_SHIFT)
 160
 161 #define PLL_BASE_OVRRIDE_MASK   (1U << 28)
 162
 163 #define PLL_DIVP_SHIFT          20
 164 #define PLL_DIVP_MASK           (7U << PLL_DIVP_SHIFT)
 165
 166 #define PLL_DIVN_SHIFT          8
 167 #define PLL_DIVN_MASK           (0x3ffU << PLL_DIVN_SHIFT)
 168
 169 #define PLL_DIVM_SHIFT          0
 170 #define PLL_DIVM_MASK           (0x1f << PLL_DIVM_SHIFT)
 171
 172 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
 173 #define PLL_OUT_RSTN            (1 << 0)
 174 #define PLL_OUT_CLKEN           (1 << 1)
 175 #define PLL_OUT_OVRRIDE         (1 << 2)
 176
 177 #define PLL_OUT_RATIO_SHIFT     8
 178 #define PLL_OUT_RATIO_MASK      (0xffU << PLL_OUT_RATIO_SHIFT)
 179
 180 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
 181 #define PLL_DCCON_SHIFT         20
 182 #define PLL_DCCON_MASK          (1U << PLL_DCCON_SHIFT)
 183
 184 #define PLL_LOCK_ENABLE_SHIFT   18
 185 #define PLL_LOCK_ENABLE_MASK    (1U << PLL_LOCK_ENABLE_SHIFT)
 186
 187 #define PLL_CPCON_SHIFT         8
 188 #define PLL_CPCON_MASK          (15U << PLL_CPCON_SHIFT)
 189
 190 #define PLL_LFCON_SHIFT         4
 191 #define PLL_LFCON_MASK          (15U << PLL_LFCON_SHIFT)
 192
 193 #define PLLU_VCO_FREQ_SHIFT     20
 194 #define PLLU_VCO_FREQ_MASK      (1U << PLLU_VCO_FREQ_SHIFT)
 195
 196 #define PLLP_OUT1_OVR           (1 << 2)
 197 #define PLLP_OUT2_OVR           (1 << 18)
 198 #define PLLP_OUT3_OVR           (1 << 2)
 199 #define PLLP_OUT4_OVR           (1 << 18)
 200 #define PLLP_OUT1_RATIO         8
 201 #define PLLP_OUT2_RATIO         24
 202 #define PLLP_OUT3_RATIO         8
 203 #define PLLP_OUT4_RATIO         24
 204
 205 enum {
 206         IN_408_OUT_204_DIVISOR = 2,
 207         IN_408_OUT_102_DIVISOR = 6,
 208         IN_408_OUT_48_DIVISOR = 15,
 209         IN_408_OUT_9_6_DIVISOR = 83,
 210 };
 211
 212 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
 213 #define PLLU_POWERDOWN          (1 << 16)
 214 #define PLL_ENABLE_POWERDOWN    (1 << 14)
 215 #define PLL_ACTIVE_POWERDOWN    (1 << 12)
 216
 217 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
 218 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN         (1 << 4)
 219 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN         (1 << 2)
 220 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN         (1 << 0)
 221
 222 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
 223 #define OSC_XOBP_SHIFT          1
 224 #define OSC_XOBP_MASK           (1U << OSC_XOBP_SHIFT)
 225
 226 /*
 227  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
 228  * but can be 16. We could use knowledge we have to restrict the mask in
 229  * the 8-bit cases (the divider_bits value returned by
 230  * get_periph_clock_source()) but it does not seem worth it since the code
 231  * already checks the ranges of values it is writing, in clk_get_divider().
 232  */
 233 #define OUT_CLK_DIVISOR_SHIFT   0
 234 #define OUT_CLK_DIVISOR_MASK    (0xffff << OUT_CLK_DIVISOR_SHIFT)
 235
 236 #define OUT_CLK_SOURCE_SHIFT    30
 237 #define OUT_CLK_SOURCE_MASK     (3U << OUT_CLK_SOURCE_SHIFT)
 238
 239 #define OUT_CLK_SOURCE4_SHIFT   28
 240 #define OUT_CLK_SOURCE4_MASK    (15U << OUT_CLK_SOURCE4_SHIFT)
 241
 242 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
 243 #define SCLK_SYS_STATE_SHIFT    28U
 244 #define SCLK_SYS_STATE_MASK     (15U << SCLK_SYS_STATE_SHIFT)
 245 enum {
 246         SCLK_SYS_STATE_STDBY,
 247         SCLK_SYS_STATE_IDLE,
 248         SCLK_SYS_STATE_RUN,
 249         SCLK_SYS_STATE_IRQ = 4U,
 250         SCLK_SYS_STATE_FIQ = 8U,
 251 };
 252 #define SCLK_COP_FIQ_MASK       (1 << 27)
 253 #define SCLK_CPU_FIQ_MASK       (1 << 26)
 254 #define SCLK_COP_IRQ_MASK       (1 << 25)
 255 #define SCLK_CPU_IRQ_MASK       (1 << 24)
 256
 257 #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT           12
 258 #define SCLK_SWAKEUP_FIQ_SOURCE_MASK            \
 259                 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
 260 #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT           8
 261 #define SCLK_SWAKEUP_IRQ_SOURCE_MASK            \
 262                 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
 263 #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT           4
 264 #define SCLK_SWAKEUP_RUN_SOURCE_MASK            \
 265                 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
 266 #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT          0
 267
 268 #define SCLK_SWAKEUP_IDLE_SOURCE_MASK           \
 269                 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
 270 enum {
 271         SCLK_SOURCE_CLKM,
 272         SCLK_SOURCE_PLLC_OUT1,
 273         SCLK_SOURCE_PLLP_OUT4,
 274         SCLK_SOURCE_PLLP_OUT3,
 275         SCLK_SOURCE_PLLP_OUT2,
 276         SCLK_SOURCE_CLKD,
 277         SCLK_SOURCE_CLKS,
 278         SCLK_SOURCE_PLLM_OUT1,
 279 };
 280 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
 281 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
 282 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
 283 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
 284
 285 /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
 286 #define SUPER_SCLK_ENB_SHIFT            31U
 287 #define SUPER_SCLK_ENB_MASK             (1U << 31)
 288 #define SUPER_SCLK_DIVIDEND_SHIFT       8
 289 #define SUPER_SCLK_DIVIDEND_MASK        (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
 290 #define SUPER_SCLK_DIVISOR_SHIFT        0
 291 #define SUPER_SCLK_DIVISOR_MASK         (0xff << SUPER_SCLK_DIVISOR_SHIFT)
 292
 293 /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
 294 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
 295 #define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
 296 #define CLK_SYS_RATE_AHB_RATE_SHIFT     4
 297 #define CLK_SYS_RATE_AHB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 298 #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
 299 #define CLK_SYS_RATE_PCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
 300 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
 301 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 302
 303 /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
 304 #define CLR_CPURESET0   (1 << 0)
 305 #define CLR_CPURESET1   (1 << 1)
 306 #define CLR_CPURESET2   (1 << 2)
 307 #define CLR_CPURESET3   (1 << 3)
 308 #define CLR_DBGRESET0   (1 << 12)
 309 #define CLR_DBGRESET1   (1 << 13)
 310 #define CLR_DBGRESET2   (1 << 14)
 311 #define CLR_DBGRESET3   (1 << 15)
 312 #define CLR_CORERESET0  (1 << 16)
 313 #define CLR_CORERESET1  (1 << 17)
 314 #define CLR_CORERESET2  (1 << 18)
 315 #define CLR_CORERESET3  (1 << 19)
 316 #define CLR_CXRESET0    (1 << 20)
 317 #define CLR_CXRESET1    (1 << 21)
 318 #define CLR_CXRESET2    (1 << 22)
 319 #define CLR_CXRESET3    (1 << 23)
 320 #define CLR_NONCPURESET (1 << 29)
 321
 322 #endif  /* _TEGRA_CLK_RST_H_ */